drivers/mmc/s5p_sdhci.c

   1 /*
   2  * (C) Copyright 2012 SAMSUNG Electronics
   3  * Jaehoon Chung <jh80.chung@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <malloc.h>
  10 #include <sdhci.h>
  11 #include <asm/arch/mmc.h>
  12 #include <asm/arch/clk.h>
  13
  14 static char *S5P_NAME = "SAMSUNG SDHCI";
  15 static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
  16 {
  17         unsigned long val, ctrl;
  18         /*
  19          * SELCLKPADDS[17:16]
  20          * 00 = 2mA
  21          * 01 = 4mA
  22          * 10 = 7mA
  23          * 11 = 9mA
  24          */
  25         sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4);
  26
  27         val = sdhci_readl(host, SDHCI_CONTROL2);
  28         val &= SDHCI_CTRL2_SELBASECLK_SHIFT;
  29
  30         val |=  SDHCI_CTRL2_ENSTAASYNCCLR |
  31                 SDHCI_CTRL2_ENCMDCNFMSK |
  32                 SDHCI_CTRL2_ENFBCLKRX |
  33                 SDHCI_CTRL2_ENCLKOUTHOLD;
  34
  35         sdhci_writel(host, val, SDHCI_CONTROL2);
  36
  37         /*
  38          * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7]
  39          * FCSel[1:0] : Rx Feedback Clock Delay Control
  40          *      Inverter delay means10ns delay if SDCLK 50MHz setting
  41          *      01 = Delay1 (basic delay)
  42          *      11 = Delay2 (basic delay + 2ns)
  43          *      00 = Delay3 (inverter delay)
  44          *      10 = Delay4 (inverter delay + 2ns)
  45          */
  46         val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1;
  47         sdhci_writel(host, val, SDHCI_CONTROL3);
  48
  49         /*
  50          * SELBASECLK[5:4]
  51          * 00/01 = HCLK
  52          * 10 = EPLL
  53          * 11 = XTI or XEXTCLK
  54          */
  55         ctrl = sdhci_readl(host, SDHCI_CONTROL2);
  56         ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3);
  57         ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2);
  58         sdhci_writel(host, ctrl, SDHCI_CONTROL2);
  59 }
  60
  61 int s5p_sdhci_init(u32 regbase, int index, int bus_width)
  62 {
  63         struct sdhci_host *host = NULL;
  64         host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
  65         if (!host) {
  66                 printf("sdhci__host malloc fail!\n");
  67                 return 1;
  68         }
  69
  70         host->name = S5P_NAME;
  71         host->ioaddr = (void *)regbase;
  72
  73         host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
  74                 SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
  75                 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
  76         host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  77         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
  78
  79         host->set_control_reg = &s5p_sdhci_set_control_reg;
  80         host->set_clock = set_mmc_clk;
  81         host->index = index;
  82
  83         host->host_caps = MMC_MODE_HC;
  84         if (bus_width == 8)
  85                 host->host_caps |= MMC_MODE_8BIT;
  86
  87         return add_sdhci(host, 52000000, 400000);
  88 }