1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2013 Google, Inc
9 #include <dt-structs.h>
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/arch-rockchip/periph.h>
18 #include <linux/err.h>
20 struct rockchip_mmc_plat {
21 #if CONFIG_IS_ENABLED(OF_PLATDATA)
22 struct dtd_rockchip_rk3288_dw_mshc dtplat;
24 struct mmc_config cfg;
28 struct rockchip_dwmmc_priv {
30 struct dwmci_host host;
36 static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
38 struct udevice *dev = host->priv;
39 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
42 ret = clk_set_rate(&priv->clk, freq);
44 debug("%s: err=%d\n", __func__, ret);
51 static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
53 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
54 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
55 struct dwmci_host *host = &priv->host;
57 host->name = dev->name;
58 host->ioaddr = dev_read_addr_ptr(dev);
59 host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
60 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
63 /* use non-removeable as sdcard and emmc as judgement */
64 if (dev_read_bool(dev, "non-removable"))
69 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
71 if (priv->fifo_depth < 0)
73 priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
75 #ifdef CONFIG_SPL_BUILD
77 priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode");
81 * 'clock-freq-min-max' is deprecated
82 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
84 if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
85 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
90 priv->minmax[0] = 400000; /* 400 kHz */
91 priv->minmax[1] = val;
93 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
100 static int rockchip_dwmmc_probe(struct udevice *dev)
102 struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
103 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
104 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
105 struct dwmci_host *host = &priv->host;
106 struct udevice *pwr_dev __maybe_unused;
109 #if CONFIG_IS_ENABLED(OF_PLATDATA)
110 struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
112 host->name = dev->name;
113 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
114 host->buswidth = dtplat->bus_width;
115 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
118 priv->fifo_depth = dtplat->fifo_depth;
120 priv->minmax[0] = 400000; /* 400 kHz */
121 priv->minmax[1] = dtplat->max_frequency;
123 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
127 ret = clk_get_by_index(dev, 0, &priv->clk);
131 host->fifoth_val = MSIZE(0x2) |
132 RX_WMARK(priv->fifo_depth / 2 - 1) |
133 TX_WMARK(priv->fifo_depth / 2);
135 host->fifo_mode = priv->fifo_mode;
138 /* Enable power if needed */
139 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
142 ret = pwrseq_set_power(pwr_dev, true);
147 dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
148 host->mmc = &plat->mmc;
149 host->mmc->priv = &priv->host;
150 host->mmc->dev = dev;
151 upriv->mmc = host->mmc;
153 return dwmci_probe(dev);
156 static int rockchip_dwmmc_bind(struct udevice *dev)
158 struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
160 return dwmci_bind(dev, &plat->mmc, &plat->cfg);
163 static const struct udevice_id rockchip_dwmmc_ids[] = {
164 { .compatible = "rockchip,rk2928-dw-mshc" },
165 { .compatible = "rockchip,rk3288-dw-mshc" },
169 U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
170 .name = "rockchip_rk3288_dw_mshc",
172 .of_match = rockchip_dwmmc_ids,
173 .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
174 .ops = &dm_dwmci_ops,
175 .bind = rockchip_dwmmc_bind,
176 .probe = rockchip_dwmmc_probe,
177 .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
178 .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
182 static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
184 struct gpio_desc reset;
187 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
190 dm_gpio_set_value(&reset, 1);
192 dm_gpio_set_value(&reset, 0);
198 static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
199 .set_power = rockchip_dwmmc_pwrseq_set_power,
202 static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
203 { .compatible = "mmc-pwrseq-emmc" },
207 U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
208 .name = "mmc_pwrseq_emmc",
210 .of_match = rockchip_dwmmc_pwrseq_ids,
211 .ops = &rockchip_dwmmc_pwrseq_ops,