drivers/mmc/renesas-sdhi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <fdtdec.h>
   9 #include <mmc.h>
  10 #include <dm.h>
  11 #include <linux/compat.h>
  12 #include <linux/dma-direction.h>
  13 #include <linux/io.h>
  14 #include <linux/sizes.h>
  15 #include <power/regulator.h>
  16 #include <asm/unaligned.h>
  17
  18 #include "tmio-common.h"
  19
  20 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  21
  22 /* SCC registers */
  23 #define RENESAS_SDHI_SCC_DTCNTL                 0x800
  24 #define   RENESAS_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
  25 #define   RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
  26 #define   RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK           0xff
  27 #define RENESAS_SDHI_SCC_TAPSET                 0x804
  28 #define RENESAS_SDHI_SCC_DT2FF                  0x808
  29 #define RENESAS_SDHI_SCC_CKSEL                  0x80c
  30 #define   RENESAS_SDHI_SCC_CKSEL_DTSEL          BIT(0)
  31 #define RENESAS_SDHI_SCC_RVSCNTL                        0x810
  32 #define   RENESAS_SDHI_SCC_RVSCNTL_RVSEN                BIT(0)
  33 #define RENESAS_SDHI_SCC_RVSREQ                 0x814
  34 #define   RENESAS_SDHI_SCC_RVSREQ_RVSERR                BIT(2)
  35 #define RENESAS_SDHI_SCC_SMPCMP                 0x818
  36 #define RENESAS_SDHI_SCC_TMPPORT2                       0x81c
  37 #define   RENESAS_SDHI_SCC_TMPPORT2_HS400EN             BIT(31)
  38 #define   RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL           BIT(4)
  39
  40 #define RENESAS_SDHI_MAX_TAP 3
  41
  42 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
  43 {
  44         u32 reg;
  45
  46         /* Initialize SCC */
  47         tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
  48
  49         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  50         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
  51         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  52
  53         /* Set sampling clock selection range */
  54         tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
  55                            RENESAS_SDHI_SCC_DTCNTL);
  56
  57         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
  58         reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
  59         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
  60
  61         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
  62         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
  63         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
  64
  65         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  66         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  67         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  68
  69         tmio_sd_writel(priv, 0x300 /* scc_tappos */,
  70                            RENESAS_SDHI_SCC_DT2FF);
  71
  72         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  73         reg |= TMIO_SD_CLKCTL_SCLKEN;
  74         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  75
  76         /* Read TAPNUM */
  77         return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
  78                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
  79                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
  80 }
  81
  82 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
  83 {
  84         u32 reg;
  85
  86         /* Reset SCC */
  87         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  88         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
  89         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  90
  91         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
  92         reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
  93         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
  94
  95         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
  96         reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
  97                  RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
  98         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
  99
 100         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 101         reg |= TMIO_SD_CLKCTL_SCLKEN;
 102         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 103
 104         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 105         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 106         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 107
 108         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 109         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 110         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 111 }
 112
 113 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
 114                                        unsigned long tap)
 115 {
 116         /* Set sampling clock position */
 117         tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
 118 }
 119
 120 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
 121 {
 122         /* Get comparison of sampling data */
 123         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
 124 }
 125
 126 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
 127                                      unsigned int tap_num, unsigned int taps,
 128                                      unsigned int smpcmp)
 129 {
 130         unsigned long tap_cnt;  /* counter of tuning success */
 131         unsigned long tap_set;  /* tap position */
 132         unsigned long tap_start;/* start position of tuning success */
 133         unsigned long tap_end;  /* end position of tuning success */
 134         unsigned long ntap;     /* temporary counter of tuning success */
 135         unsigned long match_cnt;/* counter of matching data */
 136         unsigned long i;
 137         bool select = false;
 138         u32 reg;
 139
 140         /* Clear SCC_RVSREQ */
 141         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 142
 143         /* Merge the results */
 144         for (i = 0; i < tap_num * 2; i++) {
 145                 if (!(taps & BIT(i))) {
 146                         taps &= ~BIT(i % tap_num);
 147                         taps &= ~BIT((i % tap_num) + tap_num);
 148                 }
 149                 if (!(smpcmp & BIT(i))) {
 150                         smpcmp &= ~BIT(i % tap_num);
 151                         smpcmp &= ~BIT((i % tap_num) + tap_num);
 152                 }
 153         }
 154
 155         /*
 156          * Find the longest consecutive run of successful probes.  If that
 157          * is more than RENESAS_SDHI_MAX_TAP probes long then use the
 158          * center index as the tap.
 159          */
 160         tap_cnt = 0;
 161         ntap = 0;
 162         tap_start = 0;
 163         tap_end = 0;
 164         for (i = 0; i < tap_num * 2; i++) {
 165                 if (taps & BIT(i))
 166                         ntap++;
 167                 else {
 168                         if (ntap > tap_cnt) {
 169                                 tap_start = i - ntap;
 170                                 tap_end = i - 1;
 171                                 tap_cnt = ntap;
 172                         }
 173                         ntap = 0;
 174                 }
 175         }
 176
 177         if (ntap > tap_cnt) {
 178                 tap_start = i - ntap;
 179                 tap_end = i - 1;
 180                 tap_cnt = ntap;
 181         }
 182
 183         /*
 184          * If all of the TAP is OK, the sampling clock position is selected by
 185          * identifying the change point of data.
 186          */
 187         if (tap_cnt == tap_num * 2) {
 188                 match_cnt = 0;
 189                 ntap = 0;
 190                 tap_start = 0;
 191                 tap_end = 0;
 192                 for (i = 0; i < tap_num * 2; i++) {
 193                         if (smpcmp & BIT(i))
 194                                 ntap++;
 195                         else {
 196                                 if (ntap > match_cnt) {
 197                                         tap_start = i - ntap;
 198                                         tap_end = i - 1;
 199                                         match_cnt = ntap;
 200                                 }
 201                                 ntap = 0;
 202                         }
 203                 }
 204                 if (ntap > match_cnt) {
 205                         tap_start = i - ntap;
 206                         tap_end = i - 1;
 207                         match_cnt = ntap;
 208                 }
 209                 if (match_cnt)
 210                         select = true;
 211         } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
 212                 select = true;
 213
 214         if (select)
 215                 tap_set = ((tap_start + tap_end) / 2) % tap_num;
 216         else
 217                 return -EIO;
 218
 219         /* Set SCC */
 220         tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
 221
 222         /* Enable auto re-tuning */
 223         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 224         reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 225         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 226
 227         return 0;
 228 }
 229
 230 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
 231 {
 232         struct tmio_sd_priv *priv = dev_get_priv(dev);
 233         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 234         struct mmc *mmc = upriv->mmc;
 235         unsigned int tap_num;
 236         unsigned int taps = 0, smpcmp = 0;
 237         int i, ret = 0;
 238         u32 caps;
 239
 240         /* Only supported on Renesas RCar */
 241         if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
 242                 return -EINVAL;
 243
 244         /* clock tuning is not needed for upto 52MHz */
 245         if (!((mmc->selected_mode == MMC_HS_200) ||
 246               (mmc->selected_mode == UHS_SDR104) ||
 247               (mmc->selected_mode == UHS_SDR50)))
 248                 return 0;
 249
 250         tap_num = renesas_sdhi_init_tuning(priv);
 251         if (!tap_num)
 252                 /* Tuning is not supported */
 253                 goto out;
 254
 255         if (tap_num * 2 >= sizeof(taps) * 8) {
 256                 dev_err(dev,
 257                         "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
 258                 goto out;
 259         }
 260
 261         /* Issue CMD19 twice for each tap */
 262         for (i = 0; i < 2 * tap_num; i++) {
 263                 renesas_sdhi_prepare_tuning(priv, i % tap_num);
 264
 265                 /* Force PIO for the tuning */
 266                 caps = priv->caps;
 267                 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
 268
 269                 ret = mmc_send_tuning(mmc, opcode, NULL);
 270
 271                 priv->caps = caps;
 272
 273                 if (ret == 0)
 274                         taps |= BIT(i);
 275
 276                 ret = renesas_sdhi_compare_scc_data(priv);
 277                 if (ret == 0)
 278                         smpcmp |= BIT(i);
 279
 280                 mdelay(1);
 281         }
 282
 283         ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
 284
 285 out:
 286         if (ret < 0) {
 287                 dev_warn(dev, "Tuning procedure failed\n");
 288                 renesas_sdhi_reset_tuning(priv);
 289         }
 290
 291         return ret;
 292 }
 293 #endif
 294
 295 static int renesas_sdhi_set_ios(struct udevice *dev)
 296 {
 297         int ret = tmio_sd_set_ios(dev);
 298
 299         mdelay(10);
 300
 301 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 302         struct tmio_sd_priv *priv = dev_get_priv(dev);
 303
 304         if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
 305                 renesas_sdhi_reset_tuning(priv);
 306 #endif
 307
 308         return ret;
 309 }
 310
 311 static const struct dm_mmc_ops renesas_sdhi_ops = {
 312         .send_cmd = tmio_sd_send_cmd,
 313         .set_ios = renesas_sdhi_set_ios,
 314         .get_cd = tmio_sd_get_cd,
 315 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 316         .execute_tuning = renesas_sdhi_execute_tuning,
 317 #endif
 318 };
 319
 320 #define RENESAS_GEN2_QUIRKS     TMIO_SD_CAP_RCAR_GEN2
 321 #define RENESAS_GEN3_QUIRKS                             \
 322         TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
 323
 324 static const struct udevice_id renesas_sdhi_match[] = {
 325         { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
 326         { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
 327         { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
 328         { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
 329         { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
 330         { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
 331         { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
 332         { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
 333         { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
 334         { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
 335         { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
 336         { /* sentinel */ }
 337 };
 338
 339 static int renesas_sdhi_probe(struct udevice *dev)
 340 {
 341         struct tmio_sd_priv *priv = dev_get_priv(dev);
 342         u32 quirks = dev_get_driver_data(dev);
 343         struct fdt_resource reg_res;
 344         struct clk clk;
 345         DECLARE_GLOBAL_DATA_PTR;
 346         int ret;
 347
 348         if (quirks == RENESAS_GEN2_QUIRKS) {
 349                 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
 350                                        "reg", 0, &reg_res);
 351                 if (ret < 0) {
 352                         dev_err(dev, "\"reg\" resource not found, ret=%i\n",
 353                                 ret);
 354                         return ret;
 355                 }
 356
 357                 if (fdt_resource_size(&reg_res) == 0x100)
 358                         quirks |= TMIO_SD_CAP_16BIT;
 359         }
 360
 361         ret = clk_get_by_index(dev, 0, &clk);
 362         if (ret < 0) {
 363                 dev_err(dev, "failed to get host clock\n");
 364                 return ret;
 365         }
 366
 367         /* set to max rate */
 368         priv->mclk = clk_set_rate(&clk, ULONG_MAX);
 369         if (IS_ERR_VALUE(priv->mclk)) {
 370                 dev_err(dev, "failed to set rate for host clock\n");
 371                 clk_free(&clk);
 372                 return priv->mclk;
 373         }
 374
 375         ret = clk_enable(&clk);
 376         clk_free(&clk);
 377         if (ret) {
 378                 dev_err(dev, "failed to enable host clock\n");
 379                 return ret;
 380         }
 381
 382         ret = tmio_sd_probe(dev, quirks);
 383 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 384         if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
 385                 renesas_sdhi_reset_tuning(priv);
 386 #endif
 387         return ret;
 388 }
 389
 390 U_BOOT_DRIVER(renesas_sdhi) = {
 391         .name = "renesas-sdhi",
 392         .id = UCLASS_MMC,
 393         .of_match = renesas_sdhi_match,
 394         .bind = tmio_sd_bind,
 395         .probe = renesas_sdhi_probe,
 396         .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
 397         .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
 398         .ops = &renesas_sdhi_ops,
 399 };