drivers/mmc/renesas-sdhi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <fdtdec.h>
   9 #include <malloc.h>
  10 #include <mmc.h>
  11 #include <dm.h>
  12 #include <dm/device_compat.h>
  13 #include <linux/compat.h>
  14 #include <linux/dma-direction.h>
  15 #include <linux/io.h>
  16 #include <linux/sizes.h>
  17 #include <power/regulator.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "tmio-common.h"
  21
  22 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  23     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  24     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  25
  26 /* SCC registers */
  27 #define RENESAS_SDHI_SCC_DTCNTL                 0x800
  28 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN           BIT(0)
  29 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT    16
  30 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK     0xff
  31 #define RENESAS_SDHI_SCC_TAPSET                 0x804
  32 #define RENESAS_SDHI_SCC_DT2FF                  0x808
  33 #define RENESAS_SDHI_SCC_CKSEL                  0x80c
  34 #define RENESAS_SDHI_SCC_CKSEL_DTSEL            BIT(0)
  35 #define RENESAS_SDHI_SCC_RVSCNTL                0x810
  36 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN          BIT(0)
  37 #define RENESAS_SDHI_SCC_RVSREQ                 0x814
  38 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR          BIT(2)
  39 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP        BIT(1)
  40 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN      BIT(0)
  41 #define RENESAS_SDHI_SCC_SMPCMP                 0x818
  42 #define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR         (BIT(24) | BIT(8))
  43 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP       BIT(24)
  44 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN     BIT(8)
  45 #define RENESAS_SDHI_SCC_TMPPORT2               0x81c
  46 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN       BIT(31)
  47 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL     BIT(4)
  48 #define RENESAS_SDHI_SCC_TMPPORT3               0x828
  49 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0      3
  50 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1      2
  51 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2      1
  52 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3      0
  53 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK   0x3
  54 #define RENESAS_SDHI_SCC_TMPPORT4               0x82c
  55 #define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
  56 #define RENESAS_SDHI_SCC_TMPPORT5               0x830
  57 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R  BIT(8)
  58 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W  (0 << 8)
  59 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK  0x3F
  60 #define RENESAS_SDHI_SCC_TMPPORT6               0x834
  61 #define RENESAS_SDHI_SCC_TMPPORT7               0x838
  62 #define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE        0xa5000000
  63 #define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK        0x1f
  64 #define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE            BIT(7)
  65
  66 #define RENESAS_SDHI_MAX_TAP 3
  67
  68 #define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
  69
  70 static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
  71         { 0,  0,  0,  0,  0,  1,  1,  2,  3,  4,  5,  5,  6,  6,  7, 11,
  72          15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 },
  73         { 3,  3,  4,  4,  5,  6,  6,  7,  8,  8,  9,  9, 10, 11, 12, 15,
  74          16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
  75 };
  76
  77 static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = {
  78         { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  1,  1,  2,  3,  4,  9,
  79          15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 },
  80         { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  1,
  81           2,  9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24}
  82 };
  83
  84 static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = {
  85         { 0,  0,  0,  0,  2,  3,  4,  4,  5,  6,  7,  7,  8,  9,  9, 10,
  86          11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
  87         { 1,  2,  2,  3,  4,  4,  5,  6,  6,  7,  8,  9,  9, 10, 11, 12,
  88          13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 }
  89 };
  90
  91 static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
  92         { 0,  1,  2,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 15,
  93          16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 },
  94         { 0,  1,  2,  2,  2,  3,  4,  5,  6,  7,  9, 10, 11, 12, 13, 15,
  95          16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 }
  96 };
  97
  98 static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
  99         { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
 100           0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },
 101         { 0,  0,  1,  2,  3,  4,  4,  4,  4,  5,  5,  6,  7,  8, 10, 11,
 102          12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
 103 };
 104
 105 static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
 106 {
 107         /* On R-Car Gen3, MMC0 is at 0xee140000 */
 108         return (uintptr_t)(priv->regbase) == 0xee140000;
 109 }
 110
 111 static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
 112 {
 113         /* read mode */
 114         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
 115                        (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
 116                        RENESAS_SDHI_SCC_TMPPORT5);
 117
 118         /* access start and stop */
 119         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
 120                        RENESAS_SDHI_SCC_TMPPORT4);
 121         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
 122
 123         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
 124 }
 125
 126 static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
 127 {
 128         /* write mode */
 129         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
 130                        (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
 131                        RENESAS_SDHI_SCC_TMPPORT5);
 132         tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
 133
 134         /* access start and stop */
 135         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
 136                        RENESAS_SDHI_SCC_TMPPORT4);
 137         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
 138 }
 139
 140 static bool renesas_sdhi_check_scc_error(struct udevice *dev)
 141 {
 142         struct tmio_sd_priv *priv = dev_get_priv(dev);
 143         struct mmc *mmc = mmc_get_mmc_dev(dev);
 144         unsigned long new_tap = priv->tap_set;
 145         unsigned long error_tap = priv->tap_set;
 146         u32 reg, smpcmp;
 147
 148         if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 149             (mmc->selected_mode != UHS_SDR104) &&
 150             (mmc->selected_mode != MMC_HS_200) &&
 151             (mmc->selected_mode != MMC_HS_400) &&
 152             (priv->nrtaps != 4))
 153                 return false;
 154
 155         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 156         /* Handle automatic tuning correction */
 157         if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
 158                 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
 159                 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
 160                         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 161                         return true;
 162                 }
 163
 164                 return false;
 165         }
 166
 167         /* Handle manual tuning correction */
 168         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
 169         if (!reg)       /* No error */
 170                 return false;
 171
 172         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 173
 174         if (mmc->selected_mode == MMC_HS_400) {
 175                 /*
 176                  * Correction Error Status contains CMD and DAT signal status.
 177                  * In HS400, DAT signal based on DS signal, not CLK.
 178                  * Therefore, use only CMD status.
 179                  */
 180                 smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
 181                          RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
 182
 183                 switch (smpcmp) {
 184                 case 0:
 185                         return false;   /* No error in CMD signal */
 186                 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
 187                         new_tap = (priv->tap_set +
 188                                    priv->tap_num + 1) % priv->tap_num;
 189                         error_tap = (priv->tap_set +
 190                                      priv->tap_num - 1) % priv->tap_num;
 191                         break;
 192                 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
 193                         new_tap = (priv->tap_set +
 194                                    priv->tap_num - 1) % priv->tap_num;
 195                         error_tap = (priv->tap_set +
 196                                      priv->tap_num + 1) % priv->tap_num;
 197                         break;
 198                 default:
 199                         return true;    /* Need re-tune */
 200                 }
 201
 202                 if (priv->hs400_bad_tap & BIT(new_tap)) {
 203                         /*
 204                          * New tap is bad tap (cannot change).
 205                          * Compare with HS200 tuning result.
 206                          * In HS200 tuning, when smpcmp[error_tap]
 207                          * is OK, retune is executed.
 208                          */
 209                         if (priv->smpcmp & BIT(error_tap))
 210                                 return true;    /* Need retune */
 211
 212                         return false;   /* cannot change */
 213                 }
 214
 215                 priv->tap_set = new_tap;
 216         } else {
 217                 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
 218                         return true;    /* Need re-tune */
 219                 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
 220                         priv->tap_set = (priv->tap_set +
 221                                          priv->tap_num + 1) % priv->tap_num;
 222                 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
 223                         priv->tap_set = (priv->tap_set +
 224                                          priv->tap_num - 1) % priv->tap_num;
 225                 else
 226                         return false;
 227         }
 228
 229         /* Set TAP position */
 230         tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
 231                        RENESAS_SDHI_SCC_TAPSET);
 232
 233         return false;
 234 }
 235
 236 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
 237 {
 238         u32 calib_code;
 239
 240         if (!priv->adjust_hs400_enable)
 241                 return;
 242
 243         if (!priv->needs_adjust_hs400)
 244                 return;
 245
 246         if (!priv->adjust_hs400_calib_table)
 247                 return;
 248
 249         /*
 250          * Enabled Manual adjust HS400 mode
 251          *
 252          * 1) Disabled Write Protect
 253          *    W(addr=0x00, WP_DISABLE_CODE)
 254          *
 255          * 2) Read Calibration code
 256          *    read_value = R(addr=0x26)
 257          * 3) Refer to calibration table
 258          *    Calibration code = table[read_value]
 259          * 4) Enabled Manual Calibration
 260          *    W(addr=0x22, manual mode | Calibration code)
 261          * 5) Set Offset value to TMPPORT3 Reg
 262          */
 263         sd_scc_tmpport_write32(priv, 0x00,
 264                                RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 265         calib_code = sd_scc_tmpport_read32(priv, 0x26);
 266         calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
 267         sd_scc_tmpport_write32(priv, 0x22,
 268                                RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
 269                                priv->adjust_hs400_calib_table[calib_code]);
 270         tmio_sd_writel(priv, priv->adjust_hs400_offset,
 271                        RENESAS_SDHI_SCC_TMPPORT3);
 272
 273         /* Clear flag */
 274         priv->needs_adjust_hs400 = false;
 275 }
 276
 277 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
 278 {
 279
 280         /* Disabled Manual adjust HS400 mode
 281          *
 282          * 1) Disabled Write Protect
 283          *    W(addr=0x00, WP_DISABLE_CODE)
 284          * 2) Disabled Manual Calibration
 285          *    W(addr=0x22, 0)
 286          * 3) Clear offset value to TMPPORT3 Reg
 287          */
 288         sd_scc_tmpport_write32(priv, 0x00,
 289                                RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 290         sd_scc_tmpport_write32(priv, 0x22, 0);
 291         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
 292 }
 293
 294 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
 295 {
 296         u32 reg;
 297
 298         /* Initialize SCC */
 299         tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
 300
 301         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 302         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 303         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 304
 305         /* Set sampling clock selection range */
 306         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 307                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 308                              RENESAS_SDHI_SCC_DTCNTL);
 309
 310         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 311         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 312         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 313
 314         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 315         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 316         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 317
 318         tmio_sd_writel(priv, 0x300 /* scc_tappos */,
 319                            RENESAS_SDHI_SCC_DT2FF);
 320
 321         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 322         reg |= TMIO_SD_CLKCTL_SCLKEN;
 323         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 324
 325         /* Read TAPNUM */
 326         return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
 327                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 328                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 329 }
 330
 331 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
 332 {
 333         u32 reg;
 334
 335         /* Reset SCC */
 336         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 337         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 338         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 339
 340         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 341         reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
 342         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 343
 344         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 345         reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 346                  RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 347         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 348
 349         /* Disable HS400 mode adjustment */
 350         renesas_sdhi_adjust_hs400_mode_disable(priv);
 351
 352         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 353         reg |= TMIO_SD_CLKCTL_SCLKEN;
 354         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 355
 356         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 357         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 358         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 359
 360         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 361         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 362         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 363 }
 364
 365 static int renesas_sdhi_hs400(struct udevice *dev)
 366 {
 367         struct tmio_sd_priv *priv = dev_get_priv(dev);
 368         struct mmc *mmc = mmc_get_mmc_dev(dev);
 369         bool hs400 = (mmc->selected_mode == MMC_HS_400);
 370         int ret, taps = hs400 ? priv->nrtaps : 8;
 371         unsigned long new_tap;
 372         u32 reg;
 373
 374         if (taps == 4)  /* HS400 on 4tap SoC needs different clock */
 375                 ret = clk_set_rate(&priv->clk, 400000000);
 376         else
 377                 ret = clk_set_rate(&priv->clk, 200000000);
 378         if (ret < 0)
 379                 return ret;
 380
 381         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 382         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 383         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 384
 385         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 386         if (hs400) {
 387                 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 388                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
 389         } else {
 390                 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 391                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 392         }
 393
 394         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 395
 396         /* Disable HS400 mode adjustment */
 397         if (!hs400)
 398                 renesas_sdhi_adjust_hs400_mode_disable(priv);
 399
 400         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 401                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 402                              RENESAS_SDHI_SCC_DTCNTL);
 403
 404         /* Avoid bad TAP */
 405         if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
 406                 new_tap = (priv->tap_set +
 407                            priv->tap_num + 1) % priv->tap_num;
 408
 409                 if (priv->hs400_bad_tap & BIT(new_tap))
 410                         new_tap = (priv->tap_set +
 411                                    priv->tap_num - 1) % priv->tap_num;
 412
 413                 if (priv->hs400_bad_tap & BIT(new_tap)) {
 414                         new_tap = priv->tap_set;
 415                         debug("Three consecutive bad tap is prohibited\n");
 416                 }
 417
 418                 priv->tap_set = new_tap;
 419                 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 420         }
 421
 422         if (taps == 4) {
 423                 tmio_sd_writel(priv, priv->tap_set >> 1,
 424                                RENESAS_SDHI_SCC_TAPSET);
 425                 tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
 426                                RENESAS_SDHI_SCC_DT2FF);
 427         } else {
 428                 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 429                 tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
 430         }
 431
 432         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 433         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 434         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 435
 436         /* Execute adjust hs400 offset after setting to HS400 mode */
 437         if (hs400)
 438                 priv->needs_adjust_hs400 = true;
 439
 440         return 0;
 441 }
 442
 443 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
 444                                        unsigned long tap)
 445 {
 446         /* Set sampling clock position */
 447         tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
 448 }
 449
 450 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
 451 {
 452         /* Get comparison of sampling data */
 453         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
 454 }
 455
 456 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
 457                                      unsigned int taps)
 458 {
 459         unsigned long tap_cnt;  /* counter of tuning success */
 460         unsigned long tap_start;/* start position of tuning success */
 461         unsigned long tap_end;  /* end position of tuning success */
 462         unsigned long ntap;     /* temporary counter of tuning success */
 463         unsigned long match_cnt;/* counter of matching data */
 464         unsigned long i;
 465         bool select = false;
 466         u32 reg;
 467
 468         priv->needs_adjust_hs400 = false;
 469
 470         /* Clear SCC_RVSREQ */
 471         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 472
 473         /* Merge the results */
 474         for (i = 0; i < priv->tap_num * 2; i++) {
 475                 if (!(taps & BIT(i))) {
 476                         taps &= ~BIT(i % priv->tap_num);
 477                         taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
 478                 }
 479                 if (!(priv->smpcmp & BIT(i))) {
 480                         priv->smpcmp &= ~BIT(i % priv->tap_num);
 481                         priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
 482                 }
 483         }
 484
 485         /*
 486          * Find the longest consecutive run of successful probes.  If that
 487          * is more than RENESAS_SDHI_MAX_TAP probes long then use the
 488          * center index as the tap.
 489          */
 490         tap_cnt = 0;
 491         ntap = 0;
 492         tap_start = 0;
 493         tap_end = 0;
 494         for (i = 0; i < priv->tap_num * 2; i++) {
 495                 if (taps & BIT(i))
 496                         ntap++;
 497                 else {
 498                         if (ntap > tap_cnt) {
 499                                 tap_start = i - ntap;
 500                                 tap_end = i - 1;
 501                                 tap_cnt = ntap;
 502                         }
 503                         ntap = 0;
 504                 }
 505         }
 506
 507         if (ntap > tap_cnt) {
 508                 tap_start = i - ntap;
 509                 tap_end = i - 1;
 510                 tap_cnt = ntap;
 511         }
 512
 513         /*
 514          * If all of the TAP is OK, the sampling clock position is selected by
 515          * identifying the change point of data.
 516          */
 517         if (tap_cnt == priv->tap_num * 2) {
 518                 match_cnt = 0;
 519                 ntap = 0;
 520                 tap_start = 0;
 521                 tap_end = 0;
 522                 for (i = 0; i < priv->tap_num * 2; i++) {
 523                         if (priv->smpcmp & BIT(i))
 524                                 ntap++;
 525                         else {
 526                                 if (ntap > match_cnt) {
 527                                         tap_start = i - ntap;
 528                                         tap_end = i - 1;
 529                                         match_cnt = ntap;
 530                                 }
 531                                 ntap = 0;
 532                         }
 533                 }
 534                 if (ntap > match_cnt) {
 535                         tap_start = i - ntap;
 536                         tap_end = i - 1;
 537                         match_cnt = ntap;
 538                 }
 539                 if (match_cnt)
 540                         select = true;
 541         } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
 542                 select = true;
 543
 544         if (select)
 545                 priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
 546         else
 547                 return -EIO;
 548
 549         /* Set SCC */
 550         tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 551
 552         /* Enable auto re-tuning */
 553         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 554         reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 555         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 556
 557         return 0;
 558 }
 559
 560 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
 561 {
 562         struct tmio_sd_priv *priv = dev_get_priv(dev);
 563         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 564         struct mmc *mmc = upriv->mmc;
 565         unsigned int tap_num;
 566         unsigned int taps = 0;
 567         int i, ret = 0;
 568         u32 caps;
 569
 570         /* Only supported on Renesas RCar */
 571         if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
 572                 return -EINVAL;
 573
 574         /* clock tuning is not needed for upto 52MHz */
 575         if (!((mmc->selected_mode == MMC_HS_200) ||
 576               (mmc->selected_mode == MMC_HS_400) ||
 577               (mmc->selected_mode == UHS_SDR104) ||
 578               (mmc->selected_mode == UHS_SDR50)))
 579                 return 0;
 580
 581         tap_num = renesas_sdhi_init_tuning(priv);
 582         if (!tap_num)
 583                 /* Tuning is not supported */
 584                 goto out;
 585
 586         priv->tap_num = tap_num;
 587
 588         if (priv->tap_num * 2 >= sizeof(taps) * 8) {
 589                 dev_err(dev,
 590                         "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
 591                 goto out;
 592         }
 593
 594         priv->smpcmp = 0;
 595
 596         /* Issue CMD19 twice for each tap */
 597         for (i = 0; i < 2 * priv->tap_num; i++) {
 598                 renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
 599
 600                 /* Force PIO for the tuning */
 601                 caps = priv->caps;
 602                 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
 603
 604                 ret = mmc_send_tuning(mmc, opcode, NULL);
 605
 606                 priv->caps = caps;
 607
 608                 if (ret == 0)
 609                         taps |= BIT(i);
 610
 611                 ret = renesas_sdhi_compare_scc_data(priv);
 612                 if (ret == 0)
 613                         priv->smpcmp |= BIT(i);
 614
 615                 mdelay(1);
 616         }
 617
 618         ret = renesas_sdhi_select_tuning(priv, taps);
 619
 620 out:
 621         if (ret < 0) {
 622                 dev_warn(dev, "Tuning procedure failed\n");
 623                 renesas_sdhi_reset_tuning(priv);
 624         }
 625
 626         return ret;
 627 }
 628 #else
 629 static int renesas_sdhi_hs400(struct udevice *dev)
 630 {
 631         return 0;
 632 }
 633 #endif
 634
 635 static int renesas_sdhi_set_ios(struct udevice *dev)
 636 {
 637         struct tmio_sd_priv *priv = dev_get_priv(dev);
 638         u32 tmp;
 639         int ret;
 640
 641         /* Stop the clock before changing its rate to avoid a glitch signal */
 642         tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 643         tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
 644         tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
 645
 646         ret = renesas_sdhi_hs400(dev);
 647         if (ret)
 648                 return ret;
 649
 650         ret = tmio_sd_set_ios(dev);
 651
 652         mdelay(10);
 653
 654 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 655     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 656     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 657         struct mmc *mmc = mmc_get_mmc_dev(dev);
 658         if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 659             (mmc->selected_mode != UHS_SDR104) &&
 660             (mmc->selected_mode != MMC_HS_200) &&
 661             (mmc->selected_mode != MMC_HS_400)) {
 662                 renesas_sdhi_reset_tuning(priv);
 663         }
 664 #endif
 665
 666         return ret;
 667 }
 668
 669 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 670 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
 671                                   int timeout_us)
 672 {
 673         int ret = -ETIMEDOUT;
 674         bool dat0_high;
 675         bool target_dat0_high = !!state;
 676         struct tmio_sd_priv *priv = dev_get_priv(dev);
 677
 678         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 679         while (timeout_us--) {
 680                 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
 681                 if (dat0_high == target_dat0_high) {
 682                         ret = 0;
 683                         break;
 684                 }
 685                 udelay(10);
 686         }
 687
 688         return ret;
 689 }
 690 #endif
 691
 692 static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 693                                  struct mmc_data *data)
 694 {
 695         int ret;
 696
 697         ret = tmio_sd_send_cmd(dev, cmd, data);
 698         if (ret)
 699                 return ret;
 700
 701 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 702     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 703     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 704         struct tmio_sd_priv *priv = dev_get_priv(dev);
 705
 706         renesas_sdhi_check_scc_error(dev);
 707
 708         if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
 709                 renesas_sdhi_adjust_hs400_mode_enable(priv);
 710 #endif
 711
 712         return 0;
 713 }
 714
 715 static const struct dm_mmc_ops renesas_sdhi_ops = {
 716         .send_cmd = renesas_sdhi_send_cmd,
 717         .set_ios = renesas_sdhi_set_ios,
 718         .get_cd = tmio_sd_get_cd,
 719 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 720     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 721     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 722         .execute_tuning = renesas_sdhi_execute_tuning,
 723 #endif
 724 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 725         .wait_dat0 = renesas_sdhi_wait_dat0,
 726 #endif
 727 };
 728
 729 #define RENESAS_GEN2_QUIRKS     TMIO_SD_CAP_RCAR_GEN2
 730 #define RENESAS_GEN3_QUIRKS                             \
 731         TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
 732
 733 static const struct udevice_id renesas_sdhi_match[] = {
 734         { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
 735         { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
 736         { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
 737         { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
 738         { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
 739         { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
 740         { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
 741         { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
 742         { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
 743         { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
 744         { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
 745         { /* sentinel */ }
 746 };
 747
 748 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
 749 {
 750         return clk_get_rate(&priv->clk);
 751 }
 752
 753 static void renesas_sdhi_filter_caps(struct udevice *dev)
 754 {
 755         struct tmio_sd_priv *priv = dev_get_priv(dev);
 756
 757         if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
 758                 return;
 759
 760 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 761     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 762     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 763         struct tmio_sd_plat *plat = dev_get_platdata(dev);
 764
 765         /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
 766         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 767             (rmobile_get_cpu_rev_integer() <= 1)) ||
 768             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 769             (rmobile_get_cpu_rev_integer() == 1) &&
 770             (rmobile_get_cpu_rev_fraction() < 2)))
 771                 plat->cfg.host_caps &= ~MMC_MODE_HS400;
 772
 773         /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
 774         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 775             (rmobile_get_cpu_rev_integer() >= 2)) ||
 776             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 777             (rmobile_get_cpu_rev_integer() == 1) &&
 778             (rmobile_get_cpu_rev_fraction() == 2)) ||
 779             (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
 780                 priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
 781
 782         /* H3 ES3.0 can use HS400 with manual adjustment */
 783         if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 784             (rmobile_get_cpu_rev_integer() >= 3)) {
 785                 priv->adjust_hs400_enable = true;
 786                 priv->adjust_hs400_offset = 0;
 787                 priv->adjust_hs400_calib_table =
 788                         r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
 789         }
 790
 791         /* M3W ES1.2 can use HS400 with manual adjustment */
 792         if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 793             (rmobile_get_cpu_rev_integer() == 1) &&
 794             (rmobile_get_cpu_rev_fraction() == 2)) {
 795                 priv->adjust_hs400_enable = true;
 796                 priv->adjust_hs400_offset = 3;
 797                 priv->adjust_hs400_calib_table =
 798                         r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)];
 799         }
 800
 801         /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
 802         if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 803             (rmobile_get_cpu_rev_integer() == 1) &&
 804             (rmobile_get_cpu_rev_fraction() > 2)) {
 805                 priv->adjust_hs400_enable = true;
 806                 priv->adjust_hs400_offset = 0;
 807                 priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
 808                 priv->adjust_hs400_calib_table =
 809                         r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)];
 810         }
 811
 812         /* M3N can use HS400 with manual adjustment */
 813         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
 814                 priv->adjust_hs400_enable = true;
 815                 priv->adjust_hs400_offset = 3;
 816                 priv->adjust_hs400_calib_table =
 817                         r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
 818         }
 819
 820         /* E3 can use HS400 with manual adjustment */
 821         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
 822                 priv->adjust_hs400_enable = true;
 823                 priv->adjust_hs400_offset = 3;
 824                 priv->adjust_hs400_calib_table =
 825                         r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
 826         }
 827
 828         /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
 829         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 830             (rmobile_get_cpu_rev_integer() <= 2)) ||
 831             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 832             (rmobile_get_cpu_rev_integer() == 1) &&
 833             (rmobile_get_cpu_rev_fraction() <= 2)))
 834                 priv->nrtaps = 4;
 835         else
 836                 priv->nrtaps = 8;
 837 #endif
 838         /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
 839         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 840             (rmobile_get_cpu_rev_integer() <= 1)) ||
 841             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 842             (rmobile_get_cpu_rev_integer() == 1) &&
 843             (rmobile_get_cpu_rev_fraction() == 0)))
 844                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
 845         else
 846                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
 847 }
 848
 849 static int renesas_sdhi_probe(struct udevice *dev)
 850 {
 851         struct tmio_sd_priv *priv = dev_get_priv(dev);
 852         u32 quirks = dev_get_driver_data(dev);
 853         struct fdt_resource reg_res;
 854         DECLARE_GLOBAL_DATA_PTR;
 855         int ret;
 856
 857         priv->clk_get_rate = renesas_sdhi_clk_get_rate;
 858
 859         if (quirks == RENESAS_GEN2_QUIRKS) {
 860                 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
 861                                        "reg", 0, &reg_res);
 862                 if (ret < 0) {
 863                         dev_err(dev, "\"reg\" resource not found, ret=%i\n",
 864                                 ret);
 865                         return ret;
 866                 }
 867
 868                 if (fdt_resource_size(&reg_res) == 0x100)
 869                         quirks |= TMIO_SD_CAP_16BIT;
 870         }
 871
 872         ret = clk_get_by_index(dev, 0, &priv->clk);
 873         if (ret < 0) {
 874                 dev_err(dev, "failed to get host clock\n");
 875                 return ret;
 876         }
 877
 878         /* set to max rate */
 879         ret = clk_set_rate(&priv->clk, 200000000);
 880         if (ret < 0) {
 881                 dev_err(dev, "failed to set rate for host clock\n");
 882                 clk_free(&priv->clk);
 883                 return ret;
 884         }
 885
 886         ret = clk_enable(&priv->clk);
 887         if (ret) {
 888                 dev_err(dev, "failed to enable host clock\n");
 889                 return ret;
 890         }
 891
 892         ret = tmio_sd_probe(dev, quirks);
 893
 894         renesas_sdhi_filter_caps(dev);
 895
 896 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 897     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 898     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 899         if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
 900                 renesas_sdhi_reset_tuning(priv);
 901 #endif
 902         return ret;
 903 }
 904
 905 U_BOOT_DRIVER(renesas_sdhi) = {
 906         .name = "renesas-sdhi",
 907         .id = UCLASS_MMC,
 908         .of_match = renesas_sdhi_match,
 909         .bind = tmio_sd_bind,
 910         .probe = renesas_sdhi_probe,
 911         .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
 912         .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
 913         .ops = &renesas_sdhi_ops,
 914 };