drivers/mmc/renesas-sdhi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <fdtdec.h>
   9 #include <mmc.h>
  10 #include <dm.h>
  11 #include <linux/compat.h>
  12 #include <linux/dma-direction.h>
  13 #include <linux/io.h>
  14 #include <linux/sizes.h>
  15 #include <power/regulator.h>
  16 #include <asm/unaligned.h>
  17
  18 #include "tmio-common.h"
  19
  20 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  21
  22 /* SCC registers */
  23 #define RENESAS_SDHI_SCC_DTCNTL                 0x800
  24 #define   RENESAS_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
  25 #define   RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
  26 #define   RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK           0xff
  27 #define RENESAS_SDHI_SCC_TAPSET                 0x804
  28 #define RENESAS_SDHI_SCC_DT2FF                  0x808
  29 #define RENESAS_SDHI_SCC_CKSEL                  0x80c
  30 #define   RENESAS_SDHI_SCC_CKSEL_DTSEL          BIT(0)
  31 #define RENESAS_SDHI_SCC_RVSCNTL                        0x810
  32 #define   RENESAS_SDHI_SCC_RVSCNTL_RVSEN                BIT(0)
  33 #define RENESAS_SDHI_SCC_RVSREQ                 0x814
  34 #define   RENESAS_SDHI_SCC_RVSREQ_RVSERR                BIT(2)
  35 #define RENESAS_SDHI_SCC_SMPCMP                 0x818
  36 #define RENESAS_SDHI_SCC_TMPPORT2                       0x81c
  37 #define   RENESAS_SDHI_SCC_TMPPORT2_HS400EN             BIT(31)
  38 #define   RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL           BIT(4)
  39
  40 #define RENESAS_SDHI_MAX_TAP 3
  41
  42 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
  43 {
  44         u32 reg;
  45
  46         /* Initialize SCC */
  47         tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
  48
  49         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  50         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
  51         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  52
  53         /* Set sampling clock selection range */
  54         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
  55                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
  56                              RENESAS_SDHI_SCC_DTCNTL);
  57
  58         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
  59         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
  60         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
  61
  62         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  63         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  64         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  65
  66         tmio_sd_writel(priv, 0x300 /* scc_tappos */,
  67                            RENESAS_SDHI_SCC_DT2FF);
  68
  69         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  70         reg |= TMIO_SD_CLKCTL_SCLKEN;
  71         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  72
  73         /* Read TAPNUM */
  74         return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
  75                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
  76                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
  77 }
  78
  79 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
  80 {
  81         u32 reg;
  82
  83         /* Reset SCC */
  84         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  85         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
  86         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  87
  88         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
  89         reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
  90         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
  91
  92         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
  93         reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
  94                  RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
  95         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
  96
  97         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  98         reg |= TMIO_SD_CLKCTL_SCLKEN;
  99         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 100
 101         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 102         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 103         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 104
 105         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 106         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 107         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 108 }
 109
 110 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
 111                                        unsigned long tap)
 112 {
 113         /* Set sampling clock position */
 114         tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
 115 }
 116
 117 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
 118 {
 119         /* Get comparison of sampling data */
 120         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
 121 }
 122
 123 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
 124                                      unsigned int tap_num, unsigned int taps,
 125                                      unsigned int smpcmp)
 126 {
 127         unsigned long tap_cnt;  /* counter of tuning success */
 128         unsigned long tap_start;/* start position of tuning success */
 129         unsigned long tap_end;  /* end position of tuning success */
 130         unsigned long ntap;     /* temporary counter of tuning success */
 131         unsigned long match_cnt;/* counter of matching data */
 132         unsigned long i;
 133         bool select = false;
 134         u32 reg;
 135
 136         /* Clear SCC_RVSREQ */
 137         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 138
 139         /* Merge the results */
 140         for (i = 0; i < tap_num * 2; i++) {
 141                 if (!(taps & BIT(i))) {
 142                         taps &= ~BIT(i % tap_num);
 143                         taps &= ~BIT((i % tap_num) + tap_num);
 144                 }
 145                 if (!(smpcmp & BIT(i))) {
 146                         smpcmp &= ~BIT(i % tap_num);
 147                         smpcmp &= ~BIT((i % tap_num) + tap_num);
 148                 }
 149         }
 150
 151         /*
 152          * Find the longest consecutive run of successful probes.  If that
 153          * is more than RENESAS_SDHI_MAX_TAP probes long then use the
 154          * center index as the tap.
 155          */
 156         tap_cnt = 0;
 157         ntap = 0;
 158         tap_start = 0;
 159         tap_end = 0;
 160         for (i = 0; i < tap_num * 2; i++) {
 161                 if (taps & BIT(i))
 162                         ntap++;
 163                 else {
 164                         if (ntap > tap_cnt) {
 165                                 tap_start = i - ntap;
 166                                 tap_end = i - 1;
 167                                 tap_cnt = ntap;
 168                         }
 169                         ntap = 0;
 170                 }
 171         }
 172
 173         if (ntap > tap_cnt) {
 174                 tap_start = i - ntap;
 175                 tap_end = i - 1;
 176                 tap_cnt = ntap;
 177         }
 178
 179         /*
 180          * If all of the TAP is OK, the sampling clock position is selected by
 181          * identifying the change point of data.
 182          */
 183         if (tap_cnt == tap_num * 2) {
 184                 match_cnt = 0;
 185                 ntap = 0;
 186                 tap_start = 0;
 187                 tap_end = 0;
 188                 for (i = 0; i < tap_num * 2; i++) {
 189                         if (smpcmp & BIT(i))
 190                                 ntap++;
 191                         else {
 192                                 if (ntap > match_cnt) {
 193                                         tap_start = i - ntap;
 194                                         tap_end = i - 1;
 195                                         match_cnt = ntap;
 196                                 }
 197                                 ntap = 0;
 198                         }
 199                 }
 200                 if (ntap > match_cnt) {
 201                         tap_start = i - ntap;
 202                         tap_end = i - 1;
 203                         match_cnt = ntap;
 204                 }
 205                 if (match_cnt)
 206                         select = true;
 207         } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
 208                 select = true;
 209
 210         if (select)
 211                 priv->tap_set = ((tap_start + tap_end) / 2) % tap_num;
 212         else
 213                 return -EIO;
 214
 215         /* Set SCC */
 216         tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 217
 218         /* Enable auto re-tuning */
 219         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 220         reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 221         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 222
 223         return 0;
 224 }
 225
 226 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
 227 {
 228         struct tmio_sd_priv *priv = dev_get_priv(dev);
 229         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 230         struct mmc *mmc = upriv->mmc;
 231         unsigned int tap_num;
 232         unsigned int taps = 0, smpcmp = 0;
 233         int i, ret = 0;
 234         u32 caps;
 235
 236         /* Only supported on Renesas RCar */
 237         if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
 238                 return -EINVAL;
 239
 240         /* clock tuning is not needed for upto 52MHz */
 241         if (!((mmc->selected_mode == MMC_HS_200) ||
 242               (mmc->selected_mode == UHS_SDR104) ||
 243               (mmc->selected_mode == UHS_SDR50)))
 244                 return 0;
 245
 246         tap_num = renesas_sdhi_init_tuning(priv);
 247         if (!tap_num)
 248                 /* Tuning is not supported */
 249                 goto out;
 250
 251         if (tap_num * 2 >= sizeof(taps) * 8) {
 252                 dev_err(dev,
 253                         "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
 254                 goto out;
 255         }
 256
 257         /* Issue CMD19 twice for each tap */
 258         for (i = 0; i < 2 * tap_num; i++) {
 259                 renesas_sdhi_prepare_tuning(priv, i % tap_num);
 260
 261                 /* Force PIO for the tuning */
 262                 caps = priv->caps;
 263                 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
 264
 265                 ret = mmc_send_tuning(mmc, opcode, NULL);
 266
 267                 priv->caps = caps;
 268
 269                 if (ret == 0)
 270                         taps |= BIT(i);
 271
 272                 ret = renesas_sdhi_compare_scc_data(priv);
 273                 if (ret == 0)
 274                         smpcmp |= BIT(i);
 275
 276                 mdelay(1);
 277         }
 278
 279         ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
 280
 281 out:
 282         if (ret < 0) {
 283                 dev_warn(dev, "Tuning procedure failed\n");
 284                 renesas_sdhi_reset_tuning(priv);
 285         }
 286
 287         return ret;
 288 }
 289 #endif
 290
 291 static int renesas_sdhi_set_ios(struct udevice *dev)
 292 {
 293         int ret = tmio_sd_set_ios(dev);
 294
 295         mdelay(10);
 296
 297 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 298         struct tmio_sd_priv *priv = dev_get_priv(dev);
 299
 300         if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
 301                 renesas_sdhi_reset_tuning(priv);
 302 #endif
 303
 304         return ret;
 305 }
 306
 307 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 308 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout)
 309 {
 310         int ret = -ETIMEDOUT;
 311         bool dat0_high;
 312         bool target_dat0_high = !!state;
 313         struct tmio_sd_priv *priv = dev_get_priv(dev);
 314
 315         timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
 316         while (timeout--) {
 317                 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
 318                 if (dat0_high == target_dat0_high) {
 319                         ret = 0;
 320                         break;
 321                 }
 322                 udelay(10);
 323         }
 324
 325         return ret;
 326 }
 327 #endif
 328
 329 static const struct dm_mmc_ops renesas_sdhi_ops = {
 330         .send_cmd = tmio_sd_send_cmd,
 331         .set_ios = renesas_sdhi_set_ios,
 332         .get_cd = tmio_sd_get_cd,
 333 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 334         .execute_tuning = renesas_sdhi_execute_tuning,
 335 #endif
 336 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 337         .wait_dat0 = renesas_sdhi_wait_dat0,
 338 #endif
 339 };
 340
 341 #define RENESAS_GEN2_QUIRKS     TMIO_SD_CAP_RCAR_GEN2
 342 #define RENESAS_GEN3_QUIRKS                             \
 343         TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
 344
 345 static const struct udevice_id renesas_sdhi_match[] = {
 346         { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
 347         { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
 348         { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
 349         { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
 350         { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
 351         { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
 352         { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
 353         { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
 354         { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
 355         { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
 356         { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
 357         { /* sentinel */ }
 358 };
 359
 360 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
 361 {
 362         return clk_get_rate(&priv->clk);
 363 }
 364
 365 static void renesas_sdhi_filter_caps(struct udevice *dev)
 366 {
 367         struct tmio_sd_plat *plat = dev_get_platdata(dev);
 368         struct tmio_sd_priv *priv = dev_get_priv(dev);
 369
 370         if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
 371                 return;
 372
 373         /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1 */
 374         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 375             (rmobile_get_cpu_rev_integer() <= 1)) ||
 376             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 377             (rmobile_get_cpu_rev_integer() == 1) &&
 378             (rmobile_get_cpu_rev_fraction() <= 1)))
 379                 plat->cfg.host_caps &= ~MMC_MODE_HS400;
 380 }
 381
 382 static int renesas_sdhi_probe(struct udevice *dev)
 383 {
 384         struct tmio_sd_priv *priv = dev_get_priv(dev);
 385         u32 quirks = dev_get_driver_data(dev);
 386         struct fdt_resource reg_res;
 387         DECLARE_GLOBAL_DATA_PTR;
 388         int ret;
 389
 390         priv->clk_get_rate = renesas_sdhi_clk_get_rate;
 391
 392         if (quirks == RENESAS_GEN2_QUIRKS) {
 393                 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
 394                                        "reg", 0, &reg_res);
 395                 if (ret < 0) {
 396                         dev_err(dev, "\"reg\" resource not found, ret=%i\n",
 397                                 ret);
 398                         return ret;
 399                 }
 400
 401                 if (fdt_resource_size(&reg_res) == 0x100)
 402                         quirks |= TMIO_SD_CAP_16BIT;
 403         }
 404
 405         ret = clk_get_by_index(dev, 0, &priv->clk);
 406         if (ret < 0) {
 407                 dev_err(dev, "failed to get host clock\n");
 408                 return ret;
 409         }
 410
 411         /* set to max rate */
 412         ret = clk_set_rate(&priv->clk, 200000000);
 413         if (ret < 0) {
 414                 dev_err(dev, "failed to set rate for host clock\n");
 415                 clk_free(&priv->clk);
 416                 return ret;
 417         }
 418
 419         ret = clk_enable(&priv->clk);
 420         if (ret) {
 421                 dev_err(dev, "failed to enable host clock\n");
 422                 return ret;
 423         }
 424
 425         ret = tmio_sd_probe(dev, quirks);
 426
 427         renesas_sdhi_filter_caps(dev);
 428
 429 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
 430         if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
 431                 renesas_sdhi_reset_tuning(priv);
 432 #endif
 433         return ret;
 434 }
 435
 436 U_BOOT_DRIVER(renesas_sdhi) = {
 437         .name = "renesas-sdhi",
 438         .id = UCLASS_MMC,
 439         .of_match = renesas_sdhi_match,
 440         .bind = tmio_sd_bind,
 441         .probe = renesas_sdhi_probe,
 442         .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
 443         .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
 444         .ops = &renesas_sdhi_ops,
 445 };