drivers/mmc/renesas-sdhi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <fdtdec.h>
   9 #include <mmc.h>
  10 #include <dm.h>
  11 #include <linux/compat.h>
  12 #include <linux/dma-direction.h>
  13 #include <linux/io.h>
  14 #include <linux/sizes.h>
  15 #include <power/regulator.h>
  16 #include <asm/unaligned.h>
  17
  18 #include "tmio-common.h"
  19
  20 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  21     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  22     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  23
  24 /* SCC registers */
  25 #define RENESAS_SDHI_SCC_DTCNTL                 0x800
  26 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN           BIT(0)
  27 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT    16
  28 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK     0xff
  29 #define RENESAS_SDHI_SCC_TAPSET                 0x804
  30 #define RENESAS_SDHI_SCC_DT2FF                  0x808
  31 #define RENESAS_SDHI_SCC_CKSEL                  0x80c
  32 #define RENESAS_SDHI_SCC_CKSEL_DTSEL            BIT(0)
  33 #define RENESAS_SDHI_SCC_RVSCNTL                0x810
  34 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN          BIT(0)
  35 #define RENESAS_SDHI_SCC_RVSREQ                 0x814
  36 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR          BIT(2)
  37 #define RENESAS_SDHI_SCC_SMPCMP                 0x818
  38 #define RENESAS_SDHI_SCC_TMPPORT2               0x81c
  39 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN       BIT(31)
  40 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL     BIT(4)
  41 #define RENESAS_SDHI_SCC_TMPPORT3               0x828
  42 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0      3
  43 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1      2
  44 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2      1
  45 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3      0
  46 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK   0x3
  47 #define RENESAS_SDHI_SCC_TMPPORT4               0x82c
  48 #define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
  49 #define RENESAS_SDHI_SCC_TMPPORT5               0x830
  50 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R  BIT(8)
  51 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W  (0 << 8)
  52 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK  0x3F
  53 #define RENESAS_SDHI_SCC_TMPPORT6               0x834
  54 #define RENESAS_SDHI_SCC_TMPPORT7               0x838
  55 #define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE        0xa5000000
  56 #define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK        0x1f
  57 #define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE            BIT(7)
  58
  59 #define RENESAS_SDHI_MAX_TAP 3
  60
  61 static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
  62 {
  63         /* read mode */
  64         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
  65                        (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
  66                        RENESAS_SDHI_SCC_TMPPORT5);
  67
  68         /* access start and stop */
  69         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
  70                        RENESAS_SDHI_SCC_TMPPORT4);
  71         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
  72
  73         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
  74 }
  75
  76 static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
  77 {
  78         /* write mode */
  79         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
  80                        (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
  81                        RENESAS_SDHI_SCC_TMPPORT5);
  82         tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
  83
  84         /* access start and stop */
  85         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
  86                        RENESAS_SDHI_SCC_TMPPORT4);
  87         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
  88 }
  89
  90 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
  91 {
  92         u32 calib_code;
  93
  94         if (!priv->adjust_hs400_enable)
  95                 return;
  96
  97         if (!priv->needs_adjust_hs400)
  98                 return;
  99
 100         /*
 101          * Enabled Manual adjust HS400 mode
 102          *
 103          * 1) Disabled Write Protect
 104          *    W(addr=0x00, WP_DISABLE_CODE)
 105          * 2) Read Calibration code and adjust
 106          *    R(addr=0x26) - adjust value
 107          * 3) Enabled Manual Calibration
 108          *    W(addr=0x22, manual mode | Calibration code)
 109          * 4) Set Offset value to TMPPORT3 Reg
 110          */
 111         sd_scc_tmpport_write32(priv, 0x00,
 112                                RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 113         calib_code = sd_scc_tmpport_read32(priv, 0x26);
 114         calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
 115         if (calib_code > priv->adjust_hs400_calibrate)
 116                 calib_code -= priv->adjust_hs400_calibrate;
 117         else
 118                 calib_code = 0;
 119         sd_scc_tmpport_write32(priv, 0x22,
 120                                RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
 121                                calib_code);
 122         tmio_sd_writel(priv, priv->adjust_hs400_offset,
 123                        RENESAS_SDHI_SCC_TMPPORT3);
 124
 125         /* Clear flag */
 126         priv->needs_adjust_hs400 = false;
 127 }
 128
 129 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
 130 {
 131
 132         /* Disabled Manual adjust HS400 mode
 133          *
 134          * 1) Disabled Write Protect
 135          *    W(addr=0x00, WP_DISABLE_CODE)
 136          * 2) Disabled Manual Calibration
 137          *    W(addr=0x22, 0)
 138          * 3) Clear offset value to TMPPORT3 Reg
 139          */
 140         sd_scc_tmpport_write32(priv, 0x00,
 141                                RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 142         sd_scc_tmpport_write32(priv, 0x22, 0);
 143         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
 144 }
 145
 146 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
 147 {
 148         u32 reg;
 149
 150         /* Initialize SCC */
 151         tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
 152
 153         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 154         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 155         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 156
 157         /* Set sampling clock selection range */
 158         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 159                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 160                              RENESAS_SDHI_SCC_DTCNTL);
 161
 162         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 163         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 164         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 165
 166         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 167         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 168         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 169
 170         tmio_sd_writel(priv, 0x300 /* scc_tappos */,
 171                            RENESAS_SDHI_SCC_DT2FF);
 172
 173         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 174         reg |= TMIO_SD_CLKCTL_SCLKEN;
 175         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 176
 177         /* Read TAPNUM */
 178         return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
 179                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 180                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 181 }
 182
 183 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
 184 {
 185         u32 reg;
 186
 187         /* Reset SCC */
 188         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 189         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 190         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 191
 192         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 193         reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
 194         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 195
 196         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 197         reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 198                  RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 199         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 200
 201         /* Disable HS400 mode adjustment */
 202         renesas_sdhi_adjust_hs400_mode_disable(priv);
 203
 204         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 205         reg |= TMIO_SD_CLKCTL_SCLKEN;
 206         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 207
 208         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 209         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 210         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 211
 212         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 213         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 214         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 215 }
 216
 217 static int renesas_sdhi_hs400(struct udevice *dev)
 218 {
 219         struct tmio_sd_priv *priv = dev_get_priv(dev);
 220         struct mmc *mmc = mmc_get_mmc_dev(dev);
 221         bool hs400 = (mmc->selected_mode == MMC_HS_400);
 222         int ret, taps = hs400 ? priv->nrtaps : 8;
 223         u32 reg;
 224
 225         if (taps == 4)  /* HS400 on 4tap SoC needs different clock */
 226                 ret = clk_set_rate(&priv->clk, 400000000);
 227         else
 228                 ret = clk_set_rate(&priv->clk, 200000000);
 229         if (ret < 0)
 230                 return ret;
 231
 232         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 233         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 234         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 235
 236         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 237         if (hs400) {
 238                 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 239                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
 240         } else {
 241                 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 242                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 243         }
 244
 245         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 246
 247         /* Disable HS400 mode adjustment */
 248         if (!hs400)
 249                 renesas_sdhi_adjust_hs400_mode_disable(priv);
 250
 251         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 252                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 253                              RENESAS_SDHI_SCC_DTCNTL);
 254
 255         if (taps == 4) {
 256                 tmio_sd_writel(priv, priv->tap_set >> 1,
 257                                RENESAS_SDHI_SCC_TAPSET);
 258                 tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
 259                                RENESAS_SDHI_SCC_DT2FF);
 260         } else {
 261                 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 262                 tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
 263         }
 264
 265         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 266         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 267         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 268
 269         /* Execute adjust hs400 offset after setting to HS400 mode */
 270         if (hs400)
 271                 priv->needs_adjust_hs400 = true;
 272
 273         return 0;
 274 }
 275
 276 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
 277                                        unsigned long tap)
 278 {
 279         /* Set sampling clock position */
 280         tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
 281 }
 282
 283 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
 284 {
 285         /* Get comparison of sampling data */
 286         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
 287 }
 288
 289 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
 290                                      unsigned int taps)
 291 {
 292         unsigned long tap_cnt;  /* counter of tuning success */
 293         unsigned long tap_start;/* start position of tuning success */
 294         unsigned long tap_end;  /* end position of tuning success */
 295         unsigned long ntap;     /* temporary counter of tuning success */
 296         unsigned long match_cnt;/* counter of matching data */
 297         unsigned long i;
 298         bool select = false;
 299         u32 reg;
 300
 301         priv->needs_adjust_hs400 = false;
 302
 303         /* Clear SCC_RVSREQ */
 304         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 305
 306         /* Merge the results */
 307         for (i = 0; i < priv->tap_num * 2; i++) {
 308                 if (!(taps & BIT(i))) {
 309                         taps &= ~BIT(i % priv->tap_num);
 310                         taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
 311                 }
 312                 if (!(priv->smpcmp & BIT(i))) {
 313                         priv->smpcmp &= ~BIT(i % priv->tap_num);
 314                         priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
 315                 }
 316         }
 317
 318         /*
 319          * Find the longest consecutive run of successful probes.  If that
 320          * is more than RENESAS_SDHI_MAX_TAP probes long then use the
 321          * center index as the tap.
 322          */
 323         tap_cnt = 0;
 324         ntap = 0;
 325         tap_start = 0;
 326         tap_end = 0;
 327         for (i = 0; i < priv->tap_num * 2; i++) {
 328                 if (taps & BIT(i))
 329                         ntap++;
 330                 else {
 331                         if (ntap > tap_cnt) {
 332                                 tap_start = i - ntap;
 333                                 tap_end = i - 1;
 334                                 tap_cnt = ntap;
 335                         }
 336                         ntap = 0;
 337                 }
 338         }
 339
 340         if (ntap > tap_cnt) {
 341                 tap_start = i - ntap;
 342                 tap_end = i - 1;
 343                 tap_cnt = ntap;
 344         }
 345
 346         /*
 347          * If all of the TAP is OK, the sampling clock position is selected by
 348          * identifying the change point of data.
 349          */
 350         if (tap_cnt == priv->tap_num * 2) {
 351                 match_cnt = 0;
 352                 ntap = 0;
 353                 tap_start = 0;
 354                 tap_end = 0;
 355                 for (i = 0; i < priv->tap_num * 2; i++) {
 356                         if (priv->smpcmp & BIT(i))
 357                                 ntap++;
 358                         else {
 359                                 if (ntap > match_cnt) {
 360                                         tap_start = i - ntap;
 361                                         tap_end = i - 1;
 362                                         match_cnt = ntap;
 363                                 }
 364                                 ntap = 0;
 365                         }
 366                 }
 367                 if (ntap > match_cnt) {
 368                         tap_start = i - ntap;
 369                         tap_end = i - 1;
 370                         match_cnt = ntap;
 371                 }
 372                 if (match_cnt)
 373                         select = true;
 374         } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
 375                 select = true;
 376
 377         if (select)
 378                 priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
 379         else
 380                 return -EIO;
 381
 382         /* Set SCC */
 383         tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 384
 385         /* Enable auto re-tuning */
 386         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 387         reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 388         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 389
 390         return 0;
 391 }
 392
 393 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
 394 {
 395         struct tmio_sd_priv *priv = dev_get_priv(dev);
 396         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 397         struct mmc *mmc = upriv->mmc;
 398         unsigned int tap_num;
 399         unsigned int taps = 0;
 400         int i, ret = 0;
 401         u32 caps;
 402
 403         /* Only supported on Renesas RCar */
 404         if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
 405                 return -EINVAL;
 406
 407         /* clock tuning is not needed for upto 52MHz */
 408         if (!((mmc->selected_mode == MMC_HS_200) ||
 409               (mmc->selected_mode == MMC_HS_400) ||
 410               (mmc->selected_mode == UHS_SDR104) ||
 411               (mmc->selected_mode == UHS_SDR50)))
 412                 return 0;
 413
 414         tap_num = renesas_sdhi_init_tuning(priv);
 415         if (!tap_num)
 416                 /* Tuning is not supported */
 417                 goto out;
 418
 419         priv->tap_num = tap_num;
 420
 421         if (priv->tap_num * 2 >= sizeof(taps) * 8) {
 422                 dev_err(dev,
 423                         "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
 424                 goto out;
 425         }
 426
 427         priv->smpcmp = 0;
 428
 429         /* Issue CMD19 twice for each tap */
 430         for (i = 0; i < 2 * priv->tap_num; i++) {
 431                 renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
 432
 433                 /* Force PIO for the tuning */
 434                 caps = priv->caps;
 435                 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
 436
 437                 ret = mmc_send_tuning(mmc, opcode, NULL);
 438
 439                 priv->caps = caps;
 440
 441                 if (ret == 0)
 442                         taps |= BIT(i);
 443
 444                 ret = renesas_sdhi_compare_scc_data(priv);
 445                 if (ret == 0)
 446                         priv->smpcmp |= BIT(i);
 447
 448                 mdelay(1);
 449         }
 450
 451         ret = renesas_sdhi_select_tuning(priv, taps);
 452
 453 out:
 454         if (ret < 0) {
 455                 dev_warn(dev, "Tuning procedure failed\n");
 456                 renesas_sdhi_reset_tuning(priv);
 457         }
 458
 459         return ret;
 460 }
 461 #else
 462 static int renesas_sdhi_hs400(struct udevice *dev)
 463 {
 464         return 0;
 465 }
 466 #endif
 467
 468 static int renesas_sdhi_set_ios(struct udevice *dev)
 469 {
 470         struct tmio_sd_priv *priv = dev_get_priv(dev);
 471         u32 tmp;
 472         int ret;
 473
 474         /* Stop the clock before changing its rate to avoid a glitch signal */
 475         tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 476         tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
 477         tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
 478
 479         ret = renesas_sdhi_hs400(dev);
 480         if (ret)
 481                 return ret;
 482
 483         ret = tmio_sd_set_ios(dev);
 484
 485         mdelay(10);
 486
 487 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 488     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 489     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 490         struct mmc *mmc = mmc_get_mmc_dev(dev);
 491         if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 492             (mmc->selected_mode != UHS_SDR104) &&
 493             (mmc->selected_mode != MMC_HS_200) &&
 494             (mmc->selected_mode != MMC_HS_400)) {
 495                 renesas_sdhi_reset_tuning(priv);
 496         }
 497 #endif
 498
 499         return ret;
 500 }
 501
 502 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 503 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
 504                                   int timeout_us)
 505 {
 506         int ret = -ETIMEDOUT;
 507         bool dat0_high;
 508         bool target_dat0_high = !!state;
 509         struct tmio_sd_priv *priv = dev_get_priv(dev);
 510
 511         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 512         while (timeout_us--) {
 513                 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
 514                 if (dat0_high == target_dat0_high) {
 515                         ret = 0;
 516                         break;
 517                 }
 518                 udelay(10);
 519         }
 520
 521         return ret;
 522 }
 523 #endif
 524
 525 static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 526                                  struct mmc_data *data)
 527 {
 528         int ret;
 529
 530         ret = tmio_sd_send_cmd(dev, cmd, data);
 531         if (ret)
 532                 return ret;
 533
 534 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 535     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 536     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 537         struct tmio_sd_priv *priv = dev_get_priv(dev);
 538
 539         if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
 540                 renesas_sdhi_adjust_hs400_mode_enable(priv);
 541 #endif
 542
 543         return 0;
 544 }
 545
 546 static const struct dm_mmc_ops renesas_sdhi_ops = {
 547         .send_cmd = renesas_sdhi_send_cmd,
 548         .set_ios = renesas_sdhi_set_ios,
 549         .get_cd = tmio_sd_get_cd,
 550 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 551     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 552     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 553         .execute_tuning = renesas_sdhi_execute_tuning,
 554 #endif
 555 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 556         .wait_dat0 = renesas_sdhi_wait_dat0,
 557 #endif
 558 };
 559
 560 #define RENESAS_GEN2_QUIRKS     TMIO_SD_CAP_RCAR_GEN2
 561 #define RENESAS_GEN3_QUIRKS                             \
 562         TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
 563
 564 static const struct udevice_id renesas_sdhi_match[] = {
 565         { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
 566         { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
 567         { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
 568         { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
 569         { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
 570         { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
 571         { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
 572         { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
 573         { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
 574         { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
 575         { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
 576         { /* sentinel */ }
 577 };
 578
 579 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
 580 {
 581         return clk_get_rate(&priv->clk);
 582 }
 583
 584 static void renesas_sdhi_filter_caps(struct udevice *dev)
 585 {
 586         struct tmio_sd_plat *plat = dev_get_platdata(dev);
 587         struct tmio_sd_priv *priv = dev_get_priv(dev);
 588
 589         if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
 590                 return;
 591
 592         /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1,ES1.2 */
 593         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 594             (rmobile_get_cpu_rev_integer() <= 1)) ||
 595             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 596             (rmobile_get_cpu_rev_integer() == 1) &&
 597             (rmobile_get_cpu_rev_fraction() <= 2)))
 598                 plat->cfg.host_caps &= ~MMC_MODE_HS400;
 599
 600         /* M3W ES1.x for x>2 can use HS400 with manual adjustment */
 601         if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 602             (rmobile_get_cpu_rev_integer() == 1) &&
 603             (rmobile_get_cpu_rev_fraction() > 2)) {
 604                 priv->adjust_hs400_enable = true;
 605                 priv->adjust_hs400_offset = 3;
 606                 priv->adjust_hs400_calibrate = 0x9;
 607         }
 608
 609         /* M3N can use HS400 with manual adjustment */
 610         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
 611                 priv->adjust_hs400_enable = true;
 612                 priv->adjust_hs400_offset = 3;
 613                 priv->adjust_hs400_calibrate = 0x0;
 614         }
 615
 616         /* E3 can use HS400 with manual adjustment */
 617         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
 618                 priv->adjust_hs400_enable = true;
 619                 priv->adjust_hs400_offset = 3;
 620                 priv->adjust_hs400_calibrate = 0x4;
 621         }
 622
 623         /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
 624         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 625             (rmobile_get_cpu_rev_integer() <= 2)) ||
 626             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 627             (rmobile_get_cpu_rev_integer() == 1) &&
 628             (rmobile_get_cpu_rev_fraction() <= 2)))
 629                 priv->nrtaps = 4;
 630         else
 631                 priv->nrtaps = 8;
 632
 633         /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
 634         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 635             (rmobile_get_cpu_rev_integer() <= 1)) ||
 636             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 637             (rmobile_get_cpu_rev_integer() == 1) &&
 638             (rmobile_get_cpu_rev_fraction() == 0)))
 639                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
 640         else
 641                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
 642 }
 643
 644 static int renesas_sdhi_probe(struct udevice *dev)
 645 {
 646         struct tmio_sd_priv *priv = dev_get_priv(dev);
 647         u32 quirks = dev_get_driver_data(dev);
 648         struct fdt_resource reg_res;
 649         DECLARE_GLOBAL_DATA_PTR;
 650         int ret;
 651
 652         priv->clk_get_rate = renesas_sdhi_clk_get_rate;
 653
 654         if (quirks == RENESAS_GEN2_QUIRKS) {
 655                 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
 656                                        "reg", 0, &reg_res);
 657                 if (ret < 0) {
 658                         dev_err(dev, "\"reg\" resource not found, ret=%i\n",
 659                                 ret);
 660                         return ret;
 661                 }
 662
 663                 if (fdt_resource_size(&reg_res) == 0x100)
 664                         quirks |= TMIO_SD_CAP_16BIT;
 665         }
 666
 667         ret = clk_get_by_index(dev, 0, &priv->clk);
 668         if (ret < 0) {
 669                 dev_err(dev, "failed to get host clock\n");
 670                 return ret;
 671         }
 672
 673         /* set to max rate */
 674         ret = clk_set_rate(&priv->clk, 200000000);
 675         if (ret < 0) {
 676                 dev_err(dev, "failed to set rate for host clock\n");
 677                 clk_free(&priv->clk);
 678                 return ret;
 679         }
 680
 681         ret = clk_enable(&priv->clk);
 682         if (ret) {
 683                 dev_err(dev, "failed to enable host clock\n");
 684                 return ret;
 685         }
 686
 687         ret = tmio_sd_probe(dev, quirks);
 688
 689         renesas_sdhi_filter_caps(dev);
 690
 691 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 692     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 693     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 694         if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
 695                 renesas_sdhi_reset_tuning(priv);
 696 #endif
 697         return ret;
 698 }
 699
 700 U_BOOT_DRIVER(renesas_sdhi) = {
 701         .name = "renesas-sdhi",
 702         .id = UCLASS_MMC,
 703         .of_match = renesas_sdhi_match,
 704         .bind = tmio_sd_bind,
 705         .probe = renesas_sdhi_probe,
 706         .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
 707         .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
 708         .ops = &renesas_sdhi_ops,
 709 };