drivers/mmc/renesas-sdhi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <fdtdec.h>
   9 #include <mmc.h>
  10 #include <dm.h>
  11 #include <linux/compat.h>
  12 #include <linux/dma-direction.h>
  13 #include <linux/io.h>
  14 #include <linux/sizes.h>
  15 #include <power/regulator.h>
  16 #include <asm/unaligned.h>
  17
  18 #include "tmio-common.h"
  19
  20 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  21     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  22     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  23
  24 /* SCC registers */
  25 #define RENESAS_SDHI_SCC_DTCNTL                 0x800
  26 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN           BIT(0)
  27 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT    16
  28 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK     0xff
  29 #define RENESAS_SDHI_SCC_TAPSET                 0x804
  30 #define RENESAS_SDHI_SCC_DT2FF                  0x808
  31 #define RENESAS_SDHI_SCC_CKSEL                  0x80c
  32 #define RENESAS_SDHI_SCC_CKSEL_DTSEL            BIT(0)
  33 #define RENESAS_SDHI_SCC_RVSCNTL                0x810
  34 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN          BIT(0)
  35 #define RENESAS_SDHI_SCC_RVSREQ                 0x814
  36 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR          BIT(2)
  37 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP        BIT(1)
  38 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN      BIT(0)
  39 #define RENESAS_SDHI_SCC_SMPCMP                 0x818
  40 #define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR         (BIT(24) | BIT(8))
  41 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP       BIT(24)
  42 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN     BIT(8)
  43 #define RENESAS_SDHI_SCC_TMPPORT2               0x81c
  44 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN       BIT(31)
  45 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL     BIT(4)
  46 #define RENESAS_SDHI_SCC_TMPPORT3               0x828
  47 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0      3
  48 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1      2
  49 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2      1
  50 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3      0
  51 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK   0x3
  52 #define RENESAS_SDHI_SCC_TMPPORT4               0x82c
  53 #define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
  54 #define RENESAS_SDHI_SCC_TMPPORT5               0x830
  55 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R  BIT(8)
  56 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W  (0 << 8)
  57 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK  0x3F
  58 #define RENESAS_SDHI_SCC_TMPPORT6               0x834
  59 #define RENESAS_SDHI_SCC_TMPPORT7               0x838
  60 #define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE        0xa5000000
  61 #define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK        0x1f
  62 #define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE            BIT(7)
  63
  64 #define RENESAS_SDHI_MAX_TAP 3
  65
  66 static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
  67 {
  68         /* read mode */
  69         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
  70                        (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
  71                        RENESAS_SDHI_SCC_TMPPORT5);
  72
  73         /* access start and stop */
  74         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
  75                        RENESAS_SDHI_SCC_TMPPORT4);
  76         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
  77
  78         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
  79 }
  80
  81 static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
  82 {
  83         /* write mode */
  84         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
  85                        (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
  86                        RENESAS_SDHI_SCC_TMPPORT5);
  87         tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
  88
  89         /* access start and stop */
  90         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
  91                        RENESAS_SDHI_SCC_TMPPORT4);
  92         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
  93 }
  94
  95 static bool renesas_sdhi_check_scc_error(struct udevice *dev)
  96 {
  97         struct tmio_sd_priv *priv = dev_get_priv(dev);
  98         struct mmc *mmc = mmc_get_mmc_dev(dev);
  99         unsigned long new_tap = priv->tap_set;
 100         u32 reg, smpcmp;
 101
 102         if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 103             (mmc->selected_mode != UHS_SDR104) &&
 104             (mmc->selected_mode != MMC_HS_200) &&
 105             (mmc->selected_mode != MMC_HS_400) &&
 106             (priv->nrtaps != 4))
 107                 return false;
 108
 109         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 110         /* Handle automatic tuning correction */
 111         if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
 112                 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
 113                 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
 114                         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 115                         return true;
 116                 }
 117
 118                 return false;
 119         }
 120
 121         /* Handle manual tuning correction */
 122         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
 123         if (!reg)       /* No error */
 124                 return false;
 125
 126         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 127
 128         if (mmc->selected_mode == MMC_HS_400) {
 129                 /*
 130                  * Correction Error Status contains CMD and DAT signal status.
 131                  * In HS400, DAT signal based on DS signal, not CLK.
 132                  * Therefore, use only CMD status.
 133                  */
 134                 smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
 135                          RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
 136
 137                 switch (smpcmp) {
 138                 case 0:
 139                         return false;   /* No error in CMD signal */
 140                 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
 141                         new_tap = (priv->tap_set +
 142                                    priv->tap_num + 1) % priv->tap_num;
 143                         break;
 144                 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
 145                         new_tap = (priv->tap_set +
 146                                    priv->tap_num - 1) % priv->tap_num;
 147                         break;
 148                 default:
 149                         return true;    /* Need re-tune */
 150                 }
 151
 152                 priv->tap_set = new_tap;
 153         } else {
 154                 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
 155                         return true;    /* Need re-tune */
 156                 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
 157                         priv->tap_set = (priv->tap_set +
 158                                          priv->tap_num + 1) % priv->tap_num;
 159                 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
 160                         priv->tap_set = (priv->tap_set +
 161                                          priv->tap_num - 1) % priv->tap_num;
 162                 else
 163                         return false;
 164         }
 165
 166         /* Set TAP position */
 167         tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
 168                        RENESAS_SDHI_SCC_TAPSET);
 169
 170         return false;
 171 }
 172
 173 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
 174 {
 175         u32 calib_code;
 176
 177         if (!priv->adjust_hs400_enable)
 178                 return;
 179
 180         if (!priv->needs_adjust_hs400)
 181                 return;
 182
 183         /*
 184          * Enabled Manual adjust HS400 mode
 185          *
 186          * 1) Disabled Write Protect
 187          *    W(addr=0x00, WP_DISABLE_CODE)
 188          * 2) Read Calibration code and adjust
 189          *    R(addr=0x26) - adjust value
 190          * 3) Enabled Manual Calibration
 191          *    W(addr=0x22, manual mode | Calibration code)
 192          * 4) Set Offset value to TMPPORT3 Reg
 193          */
 194         sd_scc_tmpport_write32(priv, 0x00,
 195                                RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 196         calib_code = sd_scc_tmpport_read32(priv, 0x26);
 197         calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
 198         if (calib_code > priv->adjust_hs400_calibrate)
 199                 calib_code -= priv->adjust_hs400_calibrate;
 200         else
 201                 calib_code = 0;
 202         sd_scc_tmpport_write32(priv, 0x22,
 203                                RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
 204                                calib_code);
 205         tmio_sd_writel(priv, priv->adjust_hs400_offset,
 206                        RENESAS_SDHI_SCC_TMPPORT3);
 207
 208         /* Clear flag */
 209         priv->needs_adjust_hs400 = false;
 210 }
 211
 212 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
 213 {
 214
 215         /* Disabled Manual adjust HS400 mode
 216          *
 217          * 1) Disabled Write Protect
 218          *    W(addr=0x00, WP_DISABLE_CODE)
 219          * 2) Disabled Manual Calibration
 220          *    W(addr=0x22, 0)
 221          * 3) Clear offset value to TMPPORT3 Reg
 222          */
 223         sd_scc_tmpport_write32(priv, 0x00,
 224                                RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 225         sd_scc_tmpport_write32(priv, 0x22, 0);
 226         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
 227 }
 228
 229 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
 230 {
 231         u32 reg;
 232
 233         /* Initialize SCC */
 234         tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
 235
 236         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 237         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 238         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 239
 240         /* Set sampling clock selection range */
 241         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 242                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 243                              RENESAS_SDHI_SCC_DTCNTL);
 244
 245         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 246         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 247         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 248
 249         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 250         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 251         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 252
 253         tmio_sd_writel(priv, 0x300 /* scc_tappos */,
 254                            RENESAS_SDHI_SCC_DT2FF);
 255
 256         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 257         reg |= TMIO_SD_CLKCTL_SCLKEN;
 258         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 259
 260         /* Read TAPNUM */
 261         return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
 262                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 263                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 264 }
 265
 266 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
 267 {
 268         u32 reg;
 269
 270         /* Reset SCC */
 271         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 272         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 273         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 274
 275         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 276         reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
 277         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 278
 279         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 280         reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 281                  RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 282         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 283
 284         /* Disable HS400 mode adjustment */
 285         renesas_sdhi_adjust_hs400_mode_disable(priv);
 286
 287         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 288         reg |= TMIO_SD_CLKCTL_SCLKEN;
 289         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 290
 291         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 292         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 293         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 294
 295         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 296         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 297         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 298 }
 299
 300 static int renesas_sdhi_hs400(struct udevice *dev)
 301 {
 302         struct tmio_sd_priv *priv = dev_get_priv(dev);
 303         struct mmc *mmc = mmc_get_mmc_dev(dev);
 304         bool hs400 = (mmc->selected_mode == MMC_HS_400);
 305         int ret, taps = hs400 ? priv->nrtaps : 8;
 306         u32 reg;
 307
 308         if (taps == 4)  /* HS400 on 4tap SoC needs different clock */
 309                 ret = clk_set_rate(&priv->clk, 400000000);
 310         else
 311                 ret = clk_set_rate(&priv->clk, 200000000);
 312         if (ret < 0)
 313                 return ret;
 314
 315         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 316         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 317         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 318
 319         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 320         if (hs400) {
 321                 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 322                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
 323         } else {
 324                 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 325                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 326         }
 327
 328         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 329
 330         /* Disable HS400 mode adjustment */
 331         if (!hs400)
 332                 renesas_sdhi_adjust_hs400_mode_disable(priv);
 333
 334         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 335                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 336                              RENESAS_SDHI_SCC_DTCNTL);
 337
 338         if (taps == 4) {
 339                 tmio_sd_writel(priv, priv->tap_set >> 1,
 340                                RENESAS_SDHI_SCC_TAPSET);
 341                 tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
 342                                RENESAS_SDHI_SCC_DT2FF);
 343         } else {
 344                 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 345                 tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
 346         }
 347
 348         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 349         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 350         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 351
 352         /* Execute adjust hs400 offset after setting to HS400 mode */
 353         if (hs400)
 354                 priv->needs_adjust_hs400 = true;
 355
 356         return 0;
 357 }
 358
 359 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
 360                                        unsigned long tap)
 361 {
 362         /* Set sampling clock position */
 363         tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
 364 }
 365
 366 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
 367 {
 368         /* Get comparison of sampling data */
 369         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
 370 }
 371
 372 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
 373                                      unsigned int taps)
 374 {
 375         unsigned long tap_cnt;  /* counter of tuning success */
 376         unsigned long tap_start;/* start position of tuning success */
 377         unsigned long tap_end;  /* end position of tuning success */
 378         unsigned long ntap;     /* temporary counter of tuning success */
 379         unsigned long match_cnt;/* counter of matching data */
 380         unsigned long i;
 381         bool select = false;
 382         u32 reg;
 383
 384         priv->needs_adjust_hs400 = false;
 385
 386         /* Clear SCC_RVSREQ */
 387         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 388
 389         /* Merge the results */
 390         for (i = 0; i < priv->tap_num * 2; i++) {
 391                 if (!(taps & BIT(i))) {
 392                         taps &= ~BIT(i % priv->tap_num);
 393                         taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
 394                 }
 395                 if (!(priv->smpcmp & BIT(i))) {
 396                         priv->smpcmp &= ~BIT(i % priv->tap_num);
 397                         priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
 398                 }
 399         }
 400
 401         /*
 402          * Find the longest consecutive run of successful probes.  If that
 403          * is more than RENESAS_SDHI_MAX_TAP probes long then use the
 404          * center index as the tap.
 405          */
 406         tap_cnt = 0;
 407         ntap = 0;
 408         tap_start = 0;
 409         tap_end = 0;
 410         for (i = 0; i < priv->tap_num * 2; i++) {
 411                 if (taps & BIT(i))
 412                         ntap++;
 413                 else {
 414                         if (ntap > tap_cnt) {
 415                                 tap_start = i - ntap;
 416                                 tap_end = i - 1;
 417                                 tap_cnt = ntap;
 418                         }
 419                         ntap = 0;
 420                 }
 421         }
 422
 423         if (ntap > tap_cnt) {
 424                 tap_start = i - ntap;
 425                 tap_end = i - 1;
 426                 tap_cnt = ntap;
 427         }
 428
 429         /*
 430          * If all of the TAP is OK, the sampling clock position is selected by
 431          * identifying the change point of data.
 432          */
 433         if (tap_cnt == priv->tap_num * 2) {
 434                 match_cnt = 0;
 435                 ntap = 0;
 436                 tap_start = 0;
 437                 tap_end = 0;
 438                 for (i = 0; i < priv->tap_num * 2; i++) {
 439                         if (priv->smpcmp & BIT(i))
 440                                 ntap++;
 441                         else {
 442                                 if (ntap > match_cnt) {
 443                                         tap_start = i - ntap;
 444                                         tap_end = i - 1;
 445                                         match_cnt = ntap;
 446                                 }
 447                                 ntap = 0;
 448                         }
 449                 }
 450                 if (ntap > match_cnt) {
 451                         tap_start = i - ntap;
 452                         tap_end = i - 1;
 453                         match_cnt = ntap;
 454                 }
 455                 if (match_cnt)
 456                         select = true;
 457         } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
 458                 select = true;
 459
 460         if (select)
 461                 priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
 462         else
 463                 return -EIO;
 464
 465         /* Set SCC */
 466         tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 467
 468         /* Enable auto re-tuning */
 469         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 470         reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 471         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 472
 473         return 0;
 474 }
 475
 476 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
 477 {
 478         struct tmio_sd_priv *priv = dev_get_priv(dev);
 479         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 480         struct mmc *mmc = upriv->mmc;
 481         unsigned int tap_num;
 482         unsigned int taps = 0;
 483         int i, ret = 0;
 484         u32 caps;
 485
 486         /* Only supported on Renesas RCar */
 487         if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
 488                 return -EINVAL;
 489
 490         /* clock tuning is not needed for upto 52MHz */
 491         if (!((mmc->selected_mode == MMC_HS_200) ||
 492               (mmc->selected_mode == MMC_HS_400) ||
 493               (mmc->selected_mode == UHS_SDR104) ||
 494               (mmc->selected_mode == UHS_SDR50)))
 495                 return 0;
 496
 497         tap_num = renesas_sdhi_init_tuning(priv);
 498         if (!tap_num)
 499                 /* Tuning is not supported */
 500                 goto out;
 501
 502         priv->tap_num = tap_num;
 503
 504         if (priv->tap_num * 2 >= sizeof(taps) * 8) {
 505                 dev_err(dev,
 506                         "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
 507                 goto out;
 508         }
 509
 510         priv->smpcmp = 0;
 511
 512         /* Issue CMD19 twice for each tap */
 513         for (i = 0; i < 2 * priv->tap_num; i++) {
 514                 renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
 515
 516                 /* Force PIO for the tuning */
 517                 caps = priv->caps;
 518                 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
 519
 520                 ret = mmc_send_tuning(mmc, opcode, NULL);
 521
 522                 priv->caps = caps;
 523
 524                 if (ret == 0)
 525                         taps |= BIT(i);
 526
 527                 ret = renesas_sdhi_compare_scc_data(priv);
 528                 if (ret == 0)
 529                         priv->smpcmp |= BIT(i);
 530
 531                 mdelay(1);
 532         }
 533
 534         ret = renesas_sdhi_select_tuning(priv, taps);
 535
 536 out:
 537         if (ret < 0) {
 538                 dev_warn(dev, "Tuning procedure failed\n");
 539                 renesas_sdhi_reset_tuning(priv);
 540         }
 541
 542         return ret;
 543 }
 544 #else
 545 static int renesas_sdhi_hs400(struct udevice *dev)
 546 {
 547         return 0;
 548 }
 549 #endif
 550
 551 static int renesas_sdhi_set_ios(struct udevice *dev)
 552 {
 553         struct tmio_sd_priv *priv = dev_get_priv(dev);
 554         u32 tmp;
 555         int ret;
 556
 557         /* Stop the clock before changing its rate to avoid a glitch signal */
 558         tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 559         tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
 560         tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
 561
 562         ret = renesas_sdhi_hs400(dev);
 563         if (ret)
 564                 return ret;
 565
 566         ret = tmio_sd_set_ios(dev);
 567
 568         mdelay(10);
 569
 570 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 571     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 572     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 573         struct mmc *mmc = mmc_get_mmc_dev(dev);
 574         if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 575             (mmc->selected_mode != UHS_SDR104) &&
 576             (mmc->selected_mode != MMC_HS_200) &&
 577             (mmc->selected_mode != MMC_HS_400)) {
 578                 renesas_sdhi_reset_tuning(priv);
 579         }
 580 #endif
 581
 582         return ret;
 583 }
 584
 585 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 586 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
 587                                   int timeout_us)
 588 {
 589         int ret = -ETIMEDOUT;
 590         bool dat0_high;
 591         bool target_dat0_high = !!state;
 592         struct tmio_sd_priv *priv = dev_get_priv(dev);
 593
 594         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 595         while (timeout_us--) {
 596                 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
 597                 if (dat0_high == target_dat0_high) {
 598                         ret = 0;
 599                         break;
 600                 }
 601                 udelay(10);
 602         }
 603
 604         return ret;
 605 }
 606 #endif
 607
 608 static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 609                                  struct mmc_data *data)
 610 {
 611         int ret;
 612
 613         ret = tmio_sd_send_cmd(dev, cmd, data);
 614         if (ret)
 615                 return ret;
 616
 617 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 618     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 619     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 620         struct tmio_sd_priv *priv = dev_get_priv(dev);
 621
 622         renesas_sdhi_check_scc_error(dev);
 623
 624         if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
 625                 renesas_sdhi_adjust_hs400_mode_enable(priv);
 626 #endif
 627
 628         return 0;
 629 }
 630
 631 static const struct dm_mmc_ops renesas_sdhi_ops = {
 632         .send_cmd = renesas_sdhi_send_cmd,
 633         .set_ios = renesas_sdhi_set_ios,
 634         .get_cd = tmio_sd_get_cd,
 635 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 636     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 637     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 638         .execute_tuning = renesas_sdhi_execute_tuning,
 639 #endif
 640 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 641         .wait_dat0 = renesas_sdhi_wait_dat0,
 642 #endif
 643 };
 644
 645 #define RENESAS_GEN2_QUIRKS     TMIO_SD_CAP_RCAR_GEN2
 646 #define RENESAS_GEN3_QUIRKS                             \
 647         TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
 648
 649 static const struct udevice_id renesas_sdhi_match[] = {
 650         { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
 651         { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
 652         { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
 653         { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
 654         { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
 655         { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
 656         { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
 657         { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
 658         { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
 659         { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
 660         { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
 661         { /* sentinel */ }
 662 };
 663
 664 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
 665 {
 666         return clk_get_rate(&priv->clk);
 667 }
 668
 669 static void renesas_sdhi_filter_caps(struct udevice *dev)
 670 {
 671         struct tmio_sd_plat *plat = dev_get_platdata(dev);
 672         struct tmio_sd_priv *priv = dev_get_priv(dev);
 673
 674         if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
 675                 return;
 676
 677         /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1,ES1.2 */
 678         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 679             (rmobile_get_cpu_rev_integer() <= 1)) ||
 680             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 681             (rmobile_get_cpu_rev_integer() == 1) &&
 682             (rmobile_get_cpu_rev_fraction() <= 2)))
 683                 plat->cfg.host_caps &= ~MMC_MODE_HS400;
 684
 685         /* M3W ES1.x for x>2 can use HS400 with manual adjustment */
 686         if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 687             (rmobile_get_cpu_rev_integer() == 1) &&
 688             (rmobile_get_cpu_rev_fraction() > 2)) {
 689                 priv->adjust_hs400_enable = true;
 690                 priv->adjust_hs400_offset = 3;
 691                 priv->adjust_hs400_calibrate = 0x9;
 692         }
 693
 694         /* M3N can use HS400 with manual adjustment */
 695         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
 696                 priv->adjust_hs400_enable = true;
 697                 priv->adjust_hs400_offset = 3;
 698                 priv->adjust_hs400_calibrate = 0x0;
 699         }
 700
 701         /* E3 can use HS400 with manual adjustment */
 702         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
 703                 priv->adjust_hs400_enable = true;
 704                 priv->adjust_hs400_offset = 3;
 705                 priv->adjust_hs400_calibrate = 0x4;
 706         }
 707
 708         /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
 709         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 710             (rmobile_get_cpu_rev_integer() <= 2)) ||
 711             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 712             (rmobile_get_cpu_rev_integer() == 1) &&
 713             (rmobile_get_cpu_rev_fraction() <= 2)))
 714                 priv->nrtaps = 4;
 715         else
 716                 priv->nrtaps = 8;
 717
 718         /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
 719         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 720             (rmobile_get_cpu_rev_integer() <= 1)) ||
 721             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 722             (rmobile_get_cpu_rev_integer() == 1) &&
 723             (rmobile_get_cpu_rev_fraction() == 0)))
 724                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
 725         else
 726                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
 727 }
 728
 729 static int renesas_sdhi_probe(struct udevice *dev)
 730 {
 731         struct tmio_sd_priv *priv = dev_get_priv(dev);
 732         u32 quirks = dev_get_driver_data(dev);
 733         struct fdt_resource reg_res;
 734         DECLARE_GLOBAL_DATA_PTR;
 735         int ret;
 736
 737         priv->clk_get_rate = renesas_sdhi_clk_get_rate;
 738
 739         if (quirks == RENESAS_GEN2_QUIRKS) {
 740                 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
 741                                        "reg", 0, &reg_res);
 742                 if (ret < 0) {
 743                         dev_err(dev, "\"reg\" resource not found, ret=%i\n",
 744                                 ret);
 745                         return ret;
 746                 }
 747
 748                 if (fdt_resource_size(&reg_res) == 0x100)
 749                         quirks |= TMIO_SD_CAP_16BIT;
 750         }
 751
 752         ret = clk_get_by_index(dev, 0, &priv->clk);
 753         if (ret < 0) {
 754                 dev_err(dev, "failed to get host clock\n");
 755                 return ret;
 756         }
 757
 758         /* set to max rate */
 759         ret = clk_set_rate(&priv->clk, 200000000);
 760         if (ret < 0) {
 761                 dev_err(dev, "failed to set rate for host clock\n");
 762                 clk_free(&priv->clk);
 763                 return ret;
 764         }
 765
 766         ret = clk_enable(&priv->clk);
 767         if (ret) {
 768                 dev_err(dev, "failed to enable host clock\n");
 769                 return ret;
 770         }
 771
 772         ret = tmio_sd_probe(dev, quirks);
 773
 774         renesas_sdhi_filter_caps(dev);
 775
 776 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 777     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 778     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 779         if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
 780                 renesas_sdhi_reset_tuning(priv);
 781 #endif
 782         return ret;
 783 }
 784
 785 U_BOOT_DRIVER(renesas_sdhi) = {
 786         .name = "renesas-sdhi",
 787         .id = UCLASS_MMC,
 788         .of_match = renesas_sdhi_match,
 789         .bind = tmio_sd_bind,
 790         .probe = renesas_sdhi_probe,
 791         .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
 792         .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
 793         .ops = &renesas_sdhi_ops,
 794 };