drivers/mmc/renesas-sdhi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <fdtdec.h>
   9 #include <mmc.h>
  10 #include <dm.h>
  11 #include <linux/compat.h>
  12 #include <linux/dma-direction.h>
  13 #include <linux/io.h>
  14 #include <linux/sizes.h>
  15 #include <power/regulator.h>
  16 #include <asm/unaligned.h>
  17
  18 #include "tmio-common.h"
  19
  20 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  21     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  22     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  23
  24 /* SCC registers */
  25 #define RENESAS_SDHI_SCC_DTCNTL                 0x800
  26 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN           BIT(0)
  27 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT    16
  28 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK     0xff
  29 #define RENESAS_SDHI_SCC_TAPSET                 0x804
  30 #define RENESAS_SDHI_SCC_DT2FF                  0x808
  31 #define RENESAS_SDHI_SCC_CKSEL                  0x80c
  32 #define RENESAS_SDHI_SCC_CKSEL_DTSEL            BIT(0)
  33 #define RENESAS_SDHI_SCC_RVSCNTL                0x810
  34 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN          BIT(0)
  35 #define RENESAS_SDHI_SCC_RVSREQ                 0x814
  36 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR          BIT(2)
  37 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP        BIT(1)
  38 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN      BIT(0)
  39 #define RENESAS_SDHI_SCC_SMPCMP                 0x818
  40 #define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR         (BIT(24) | BIT(8))
  41 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP       BIT(24)
  42 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN     BIT(8)
  43 #define RENESAS_SDHI_SCC_TMPPORT2               0x81c
  44 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN       BIT(31)
  45 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL     BIT(4)
  46 #define RENESAS_SDHI_SCC_TMPPORT3               0x828
  47 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0      3
  48 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1      2
  49 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2      1
  50 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3      0
  51 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK   0x3
  52 #define RENESAS_SDHI_SCC_TMPPORT4               0x82c
  53 #define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
  54 #define RENESAS_SDHI_SCC_TMPPORT5               0x830
  55 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R  BIT(8)
  56 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W  (0 << 8)
  57 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK  0x3F
  58 #define RENESAS_SDHI_SCC_TMPPORT6               0x834
  59 #define RENESAS_SDHI_SCC_TMPPORT7               0x838
  60 #define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE        0xa5000000
  61 #define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK        0x1f
  62 #define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE            BIT(7)
  63
  64 #define RENESAS_SDHI_MAX_TAP 3
  65
  66 static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
  67 {
  68         /* read mode */
  69         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
  70                        (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
  71                        RENESAS_SDHI_SCC_TMPPORT5);
  72
  73         /* access start and stop */
  74         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
  75                        RENESAS_SDHI_SCC_TMPPORT4);
  76         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
  77
  78         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
  79 }
  80
  81 static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
  82 {
  83         /* write mode */
  84         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
  85                        (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
  86                        RENESAS_SDHI_SCC_TMPPORT5);
  87         tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
  88
  89         /* access start and stop */
  90         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
  91                        RENESAS_SDHI_SCC_TMPPORT4);
  92         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
  93 }
  94
  95 static bool renesas_sdhi_check_scc_error(struct udevice *dev)
  96 {
  97         struct tmio_sd_priv *priv = dev_get_priv(dev);
  98         struct mmc *mmc = mmc_get_mmc_dev(dev);
  99         unsigned long new_tap = priv->tap_set;
 100         unsigned long error_tap = priv->tap_set;
 101         u32 reg, smpcmp;
 102
 103         if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 104             (mmc->selected_mode != UHS_SDR104) &&
 105             (mmc->selected_mode != MMC_HS_200) &&
 106             (mmc->selected_mode != MMC_HS_400) &&
 107             (priv->nrtaps != 4))
 108                 return false;
 109
 110         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 111         /* Handle automatic tuning correction */
 112         if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
 113                 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
 114                 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
 115                         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 116                         return true;
 117                 }
 118
 119                 return false;
 120         }
 121
 122         /* Handle manual tuning correction */
 123         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
 124         if (!reg)       /* No error */
 125                 return false;
 126
 127         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 128
 129         if (mmc->selected_mode == MMC_HS_400) {
 130                 /*
 131                  * Correction Error Status contains CMD and DAT signal status.
 132                  * In HS400, DAT signal based on DS signal, not CLK.
 133                  * Therefore, use only CMD status.
 134                  */
 135                 smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
 136                          RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
 137
 138                 switch (smpcmp) {
 139                 case 0:
 140                         return false;   /* No error in CMD signal */
 141                 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
 142                         new_tap = (priv->tap_set +
 143                                    priv->tap_num + 1) % priv->tap_num;
 144                         error_tap = (priv->tap_set +
 145                                      priv->tap_num - 1) % priv->tap_num;
 146                         break;
 147                 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
 148                         new_tap = (priv->tap_set +
 149                                    priv->tap_num - 1) % priv->tap_num;
 150                         error_tap = (priv->tap_set +
 151                                      priv->tap_num + 1) % priv->tap_num;
 152                         break;
 153                 default:
 154                         return true;    /* Need re-tune */
 155                 }
 156
 157                 if (priv->hs400_bad_tap & BIT(new_tap)) {
 158                         /*
 159                          * New tap is bad tap (cannot change).
 160                          * Compare with HS200 tuning result.
 161                          * In HS200 tuning, when smpcmp[error_tap]
 162                          * is OK, retune is executed.
 163                          */
 164                         if (priv->smpcmp & BIT(error_tap))
 165                                 return true;    /* Need retune */
 166
 167                         return false;   /* cannot change */
 168                 }
 169
 170                 priv->tap_set = new_tap;
 171         } else {
 172                 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
 173                         return true;    /* Need re-tune */
 174                 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
 175                         priv->tap_set = (priv->tap_set +
 176                                          priv->tap_num + 1) % priv->tap_num;
 177                 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
 178                         priv->tap_set = (priv->tap_set +
 179                                          priv->tap_num - 1) % priv->tap_num;
 180                 else
 181                         return false;
 182         }
 183
 184         /* Set TAP position */
 185         tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
 186                        RENESAS_SDHI_SCC_TAPSET);
 187
 188         return false;
 189 }
 190
 191 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
 192 {
 193         u32 calib_code;
 194
 195         if (!priv->adjust_hs400_enable)
 196                 return;
 197
 198         if (!priv->needs_adjust_hs400)
 199                 return;
 200
 201         /*
 202          * Enabled Manual adjust HS400 mode
 203          *
 204          * 1) Disabled Write Protect
 205          *    W(addr=0x00, WP_DISABLE_CODE)
 206          * 2) Read Calibration code and adjust
 207          *    R(addr=0x26) - adjust value
 208          * 3) Enabled Manual Calibration
 209          *    W(addr=0x22, manual mode | Calibration code)
 210          * 4) Set Offset value to TMPPORT3 Reg
 211          */
 212         sd_scc_tmpport_write32(priv, 0x00,
 213                                RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 214         calib_code = sd_scc_tmpport_read32(priv, 0x26);
 215         calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
 216         if (calib_code > priv->adjust_hs400_calibrate)
 217                 calib_code -= priv->adjust_hs400_calibrate;
 218         else
 219                 calib_code = 0;
 220         sd_scc_tmpport_write32(priv, 0x22,
 221                                RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
 222                                calib_code);
 223         tmio_sd_writel(priv, priv->adjust_hs400_offset,
 224                        RENESAS_SDHI_SCC_TMPPORT3);
 225
 226         /* Clear flag */
 227         priv->needs_adjust_hs400 = false;
 228 }
 229
 230 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
 231 {
 232
 233         /* Disabled Manual adjust HS400 mode
 234          *
 235          * 1) Disabled Write Protect
 236          *    W(addr=0x00, WP_DISABLE_CODE)
 237          * 2) Disabled Manual Calibration
 238          *    W(addr=0x22, 0)
 239          * 3) Clear offset value to TMPPORT3 Reg
 240          */
 241         sd_scc_tmpport_write32(priv, 0x00,
 242                                RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 243         sd_scc_tmpport_write32(priv, 0x22, 0);
 244         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
 245 }
 246
 247 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
 248 {
 249         u32 reg;
 250
 251         /* Initialize SCC */
 252         tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
 253
 254         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 255         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 256         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 257
 258         /* Set sampling clock selection range */
 259         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 260                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 261                              RENESAS_SDHI_SCC_DTCNTL);
 262
 263         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 264         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 265         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 266
 267         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 268         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 269         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 270
 271         tmio_sd_writel(priv, 0x300 /* scc_tappos */,
 272                            RENESAS_SDHI_SCC_DT2FF);
 273
 274         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 275         reg |= TMIO_SD_CLKCTL_SCLKEN;
 276         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 277
 278         /* Read TAPNUM */
 279         return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
 280                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 281                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 282 }
 283
 284 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
 285 {
 286         u32 reg;
 287
 288         /* Reset SCC */
 289         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 290         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 291         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 292
 293         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 294         reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
 295         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 296
 297         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 298         reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 299                  RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 300         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 301
 302         /* Disable HS400 mode adjustment */
 303         renesas_sdhi_adjust_hs400_mode_disable(priv);
 304
 305         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 306         reg |= TMIO_SD_CLKCTL_SCLKEN;
 307         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 308
 309         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 310         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 311         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 312
 313         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 314         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 315         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 316 }
 317
 318 static int renesas_sdhi_hs400(struct udevice *dev)
 319 {
 320         struct tmio_sd_priv *priv = dev_get_priv(dev);
 321         struct mmc *mmc = mmc_get_mmc_dev(dev);
 322         bool hs400 = (mmc->selected_mode == MMC_HS_400);
 323         int ret, taps = hs400 ? priv->nrtaps : 8;
 324         unsigned long new_tap;
 325         u32 reg;
 326
 327         if (taps == 4)  /* HS400 on 4tap SoC needs different clock */
 328                 ret = clk_set_rate(&priv->clk, 400000000);
 329         else
 330                 ret = clk_set_rate(&priv->clk, 200000000);
 331         if (ret < 0)
 332                 return ret;
 333
 334         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 335         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 336         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 337
 338         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 339         if (hs400) {
 340                 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 341                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
 342         } else {
 343                 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 344                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 345         }
 346
 347         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 348
 349         /* Disable HS400 mode adjustment */
 350         if (!hs400)
 351                 renesas_sdhi_adjust_hs400_mode_disable(priv);
 352
 353         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 354                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 355                              RENESAS_SDHI_SCC_DTCNTL);
 356
 357         /* Avoid bad TAP */
 358         if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
 359                 new_tap = (priv->tap_set +
 360                            priv->tap_num + 1) % priv->tap_num;
 361
 362                 if (priv->hs400_bad_tap & BIT(new_tap))
 363                         new_tap = (priv->tap_set +
 364                                    priv->tap_num - 1) % priv->tap_num;
 365
 366                 if (priv->hs400_bad_tap & BIT(new_tap)) {
 367                         new_tap = priv->tap_set;
 368                         debug("Three consecutive bad tap is prohibited\n");
 369                 }
 370
 371                 priv->tap_set = new_tap;
 372                 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 373         }
 374
 375         if (taps == 4) {
 376                 tmio_sd_writel(priv, priv->tap_set >> 1,
 377                                RENESAS_SDHI_SCC_TAPSET);
 378                 tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
 379                                RENESAS_SDHI_SCC_DT2FF);
 380         } else {
 381                 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 382                 tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
 383         }
 384
 385         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 386         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 387         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 388
 389         /* Execute adjust hs400 offset after setting to HS400 mode */
 390         if (hs400)
 391                 priv->needs_adjust_hs400 = true;
 392
 393         return 0;
 394 }
 395
 396 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
 397                                        unsigned long tap)
 398 {
 399         /* Set sampling clock position */
 400         tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
 401 }
 402
 403 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
 404 {
 405         /* Get comparison of sampling data */
 406         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
 407 }
 408
 409 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
 410                                      unsigned int taps)
 411 {
 412         unsigned long tap_cnt;  /* counter of tuning success */
 413         unsigned long tap_start;/* start position of tuning success */
 414         unsigned long tap_end;  /* end position of tuning success */
 415         unsigned long ntap;     /* temporary counter of tuning success */
 416         unsigned long match_cnt;/* counter of matching data */
 417         unsigned long i;
 418         bool select = false;
 419         u32 reg;
 420
 421         priv->needs_adjust_hs400 = false;
 422
 423         /* Clear SCC_RVSREQ */
 424         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 425
 426         /* Merge the results */
 427         for (i = 0; i < priv->tap_num * 2; i++) {
 428                 if (!(taps & BIT(i))) {
 429                         taps &= ~BIT(i % priv->tap_num);
 430                         taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
 431                 }
 432                 if (!(priv->smpcmp & BIT(i))) {
 433                         priv->smpcmp &= ~BIT(i % priv->tap_num);
 434                         priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
 435                 }
 436         }
 437
 438         /*
 439          * Find the longest consecutive run of successful probes.  If that
 440          * is more than RENESAS_SDHI_MAX_TAP probes long then use the
 441          * center index as the tap.
 442          */
 443         tap_cnt = 0;
 444         ntap = 0;
 445         tap_start = 0;
 446         tap_end = 0;
 447         for (i = 0; i < priv->tap_num * 2; i++) {
 448                 if (taps & BIT(i))
 449                         ntap++;
 450                 else {
 451                         if (ntap > tap_cnt) {
 452                                 tap_start = i - ntap;
 453                                 tap_end = i - 1;
 454                                 tap_cnt = ntap;
 455                         }
 456                         ntap = 0;
 457                 }
 458         }
 459
 460         if (ntap > tap_cnt) {
 461                 tap_start = i - ntap;
 462                 tap_end = i - 1;
 463                 tap_cnt = ntap;
 464         }
 465
 466         /*
 467          * If all of the TAP is OK, the sampling clock position is selected by
 468          * identifying the change point of data.
 469          */
 470         if (tap_cnt == priv->tap_num * 2) {
 471                 match_cnt = 0;
 472                 ntap = 0;
 473                 tap_start = 0;
 474                 tap_end = 0;
 475                 for (i = 0; i < priv->tap_num * 2; i++) {
 476                         if (priv->smpcmp & BIT(i))
 477                                 ntap++;
 478                         else {
 479                                 if (ntap > match_cnt) {
 480                                         tap_start = i - ntap;
 481                                         tap_end = i - 1;
 482                                         match_cnt = ntap;
 483                                 }
 484                                 ntap = 0;
 485                         }
 486                 }
 487                 if (ntap > match_cnt) {
 488                         tap_start = i - ntap;
 489                         tap_end = i - 1;
 490                         match_cnt = ntap;
 491                 }
 492                 if (match_cnt)
 493                         select = true;
 494         } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
 495                 select = true;
 496
 497         if (select)
 498                 priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
 499         else
 500                 return -EIO;
 501
 502         /* Set SCC */
 503         tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 504
 505         /* Enable auto re-tuning */
 506         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 507         reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 508         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 509
 510         return 0;
 511 }
 512
 513 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
 514 {
 515         struct tmio_sd_priv *priv = dev_get_priv(dev);
 516         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 517         struct mmc *mmc = upriv->mmc;
 518         unsigned int tap_num;
 519         unsigned int taps = 0;
 520         int i, ret = 0;
 521         u32 caps;
 522
 523         /* Only supported on Renesas RCar */
 524         if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
 525                 return -EINVAL;
 526
 527         /* clock tuning is not needed for upto 52MHz */
 528         if (!((mmc->selected_mode == MMC_HS_200) ||
 529               (mmc->selected_mode == MMC_HS_400) ||
 530               (mmc->selected_mode == UHS_SDR104) ||
 531               (mmc->selected_mode == UHS_SDR50)))
 532                 return 0;
 533
 534         tap_num = renesas_sdhi_init_tuning(priv);
 535         if (!tap_num)
 536                 /* Tuning is not supported */
 537                 goto out;
 538
 539         priv->tap_num = tap_num;
 540
 541         if (priv->tap_num * 2 >= sizeof(taps) * 8) {
 542                 dev_err(dev,
 543                         "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
 544                 goto out;
 545         }
 546
 547         priv->smpcmp = 0;
 548
 549         /* Issue CMD19 twice for each tap */
 550         for (i = 0; i < 2 * priv->tap_num; i++) {
 551                 renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
 552
 553                 /* Force PIO for the tuning */
 554                 caps = priv->caps;
 555                 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
 556
 557                 ret = mmc_send_tuning(mmc, opcode, NULL);
 558
 559                 priv->caps = caps;
 560
 561                 if (ret == 0)
 562                         taps |= BIT(i);
 563
 564                 ret = renesas_sdhi_compare_scc_data(priv);
 565                 if (ret == 0)
 566                         priv->smpcmp |= BIT(i);
 567
 568                 mdelay(1);
 569         }
 570
 571         ret = renesas_sdhi_select_tuning(priv, taps);
 572
 573 out:
 574         if (ret < 0) {
 575                 dev_warn(dev, "Tuning procedure failed\n");
 576                 renesas_sdhi_reset_tuning(priv);
 577         }
 578
 579         return ret;
 580 }
 581 #else
 582 static int renesas_sdhi_hs400(struct udevice *dev)
 583 {
 584         return 0;
 585 }
 586 #endif
 587
 588 static int renesas_sdhi_set_ios(struct udevice *dev)
 589 {
 590         struct tmio_sd_priv *priv = dev_get_priv(dev);
 591         u32 tmp;
 592         int ret;
 593
 594         /* Stop the clock before changing its rate to avoid a glitch signal */
 595         tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 596         tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
 597         tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
 598
 599         ret = renesas_sdhi_hs400(dev);
 600         if (ret)
 601                 return ret;
 602
 603         ret = tmio_sd_set_ios(dev);
 604
 605         mdelay(10);
 606
 607 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 608     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 609     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 610         struct mmc *mmc = mmc_get_mmc_dev(dev);
 611         if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 612             (mmc->selected_mode != UHS_SDR104) &&
 613             (mmc->selected_mode != MMC_HS_200) &&
 614             (mmc->selected_mode != MMC_HS_400)) {
 615                 renesas_sdhi_reset_tuning(priv);
 616         }
 617 #endif
 618
 619         return ret;
 620 }
 621
 622 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 623 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
 624                                   int timeout_us)
 625 {
 626         int ret = -ETIMEDOUT;
 627         bool dat0_high;
 628         bool target_dat0_high = !!state;
 629         struct tmio_sd_priv *priv = dev_get_priv(dev);
 630
 631         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 632         while (timeout_us--) {
 633                 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
 634                 if (dat0_high == target_dat0_high) {
 635                         ret = 0;
 636                         break;
 637                 }
 638                 udelay(10);
 639         }
 640
 641         return ret;
 642 }
 643 #endif
 644
 645 static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 646                                  struct mmc_data *data)
 647 {
 648         int ret;
 649
 650         ret = tmio_sd_send_cmd(dev, cmd, data);
 651         if (ret)
 652                 return ret;
 653
 654 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 655     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 656     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 657         struct tmio_sd_priv *priv = dev_get_priv(dev);
 658
 659         renesas_sdhi_check_scc_error(dev);
 660
 661         if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
 662                 renesas_sdhi_adjust_hs400_mode_enable(priv);
 663 #endif
 664
 665         return 0;
 666 }
 667
 668 static const struct dm_mmc_ops renesas_sdhi_ops = {
 669         .send_cmd = renesas_sdhi_send_cmd,
 670         .set_ios = renesas_sdhi_set_ios,
 671         .get_cd = tmio_sd_get_cd,
 672 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 673     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 674     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 675         .execute_tuning = renesas_sdhi_execute_tuning,
 676 #endif
 677 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 678         .wait_dat0 = renesas_sdhi_wait_dat0,
 679 #endif
 680 };
 681
 682 #define RENESAS_GEN2_QUIRKS     TMIO_SD_CAP_RCAR_GEN2
 683 #define RENESAS_GEN3_QUIRKS                             \
 684         TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
 685
 686 static const struct udevice_id renesas_sdhi_match[] = {
 687         { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
 688         { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
 689         { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
 690         { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
 691         { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
 692         { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
 693         { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
 694         { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
 695         { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
 696         { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
 697         { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
 698         { /* sentinel */ }
 699 };
 700
 701 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
 702 {
 703         return clk_get_rate(&priv->clk);
 704 }
 705
 706 static void renesas_sdhi_filter_caps(struct udevice *dev)
 707 {
 708         struct tmio_sd_plat *plat = dev_get_platdata(dev);
 709         struct tmio_sd_priv *priv = dev_get_priv(dev);
 710
 711         if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
 712                 return;
 713
 714         /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1,ES1.2 */
 715         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 716             (rmobile_get_cpu_rev_integer() <= 1)) ||
 717             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 718             (rmobile_get_cpu_rev_integer() == 1) &&
 719             (rmobile_get_cpu_rev_fraction() <= 2)))
 720                 plat->cfg.host_caps &= ~MMC_MODE_HS400;
 721
 722         /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
 723         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 724             (rmobile_get_cpu_rev_integer() >= 2)) ||
 725             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 726             (rmobile_get_cpu_rev_integer() == 1) &&
 727             (rmobile_get_cpu_rev_fraction() == 2)) ||
 728             (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
 729                 priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
 730
 731         /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
 732         if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 733             (rmobile_get_cpu_rev_integer() == 1) &&
 734             (rmobile_get_cpu_rev_fraction() > 2)) {
 735                 priv->adjust_hs400_enable = true;
 736                 priv->adjust_hs400_offset = 3;
 737                 priv->adjust_hs400_calibrate = 0x9;
 738                 priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
 739         }
 740
 741         /* M3N can use HS400 with manual adjustment */
 742         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
 743                 priv->adjust_hs400_enable = true;
 744                 priv->adjust_hs400_offset = 3;
 745                 priv->adjust_hs400_calibrate = 0x0;
 746         }
 747
 748         /* E3 can use HS400 with manual adjustment */
 749         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
 750                 priv->adjust_hs400_enable = true;
 751                 priv->adjust_hs400_offset = 3;
 752                 priv->adjust_hs400_calibrate = 0x4;
 753         }
 754
 755         /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
 756         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 757             (rmobile_get_cpu_rev_integer() <= 2)) ||
 758             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 759             (rmobile_get_cpu_rev_integer() == 1) &&
 760             (rmobile_get_cpu_rev_fraction() <= 2)))
 761                 priv->nrtaps = 4;
 762         else
 763                 priv->nrtaps = 8;
 764
 765         /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
 766         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 767             (rmobile_get_cpu_rev_integer() <= 1)) ||
 768             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 769             (rmobile_get_cpu_rev_integer() == 1) &&
 770             (rmobile_get_cpu_rev_fraction() == 0)))
 771                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
 772         else
 773                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
 774 }
 775
 776 static int renesas_sdhi_probe(struct udevice *dev)
 777 {
 778         struct tmio_sd_priv *priv = dev_get_priv(dev);
 779         u32 quirks = dev_get_driver_data(dev);
 780         struct fdt_resource reg_res;
 781         DECLARE_GLOBAL_DATA_PTR;
 782         int ret;
 783
 784         priv->clk_get_rate = renesas_sdhi_clk_get_rate;
 785
 786         if (quirks == RENESAS_GEN2_QUIRKS) {
 787                 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
 788                                        "reg", 0, &reg_res);
 789                 if (ret < 0) {
 790                         dev_err(dev, "\"reg\" resource not found, ret=%i\n",
 791                                 ret);
 792                         return ret;
 793                 }
 794
 795                 if (fdt_resource_size(&reg_res) == 0x100)
 796                         quirks |= TMIO_SD_CAP_16BIT;
 797         }
 798
 799         ret = clk_get_by_index(dev, 0, &priv->clk);
 800         if (ret < 0) {
 801                 dev_err(dev, "failed to get host clock\n");
 802                 return ret;
 803         }
 804
 805         /* set to max rate */
 806         ret = clk_set_rate(&priv->clk, 200000000);
 807         if (ret < 0) {
 808                 dev_err(dev, "failed to set rate for host clock\n");
 809                 clk_free(&priv->clk);
 810                 return ret;
 811         }
 812
 813         ret = clk_enable(&priv->clk);
 814         if (ret) {
 815                 dev_err(dev, "failed to enable host clock\n");
 816                 return ret;
 817         }
 818
 819         ret = tmio_sd_probe(dev, quirks);
 820
 821         renesas_sdhi_filter_caps(dev);
 822
 823 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 824     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 825     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 826         if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
 827                 renesas_sdhi_reset_tuning(priv);
 828 #endif
 829         return ret;
 830 }
 831
 832 U_BOOT_DRIVER(renesas_sdhi) = {
 833         .name = "renesas-sdhi",
 834         .id = UCLASS_MMC,
 835         .of_match = renesas_sdhi_match,
 836         .bind = tmio_sd_bind,
 837         .probe = renesas_sdhi_probe,
 838         .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
 839         .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
 840         .ops = &renesas_sdhi_ops,
 841 };