1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
13 #include <dm/device_compat.h>
14 #include <linux/compat.h>
15 #include <linux/dma-direction.h>
17 #include <linux/sizes.h>
18 #include <power/regulator.h>
19 #include <asm/unaligned.h>
21 #include "tmio-common.h"
23 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
24 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
25 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
28 #define RENESAS_SDHI_SCC_DTCNTL 0x800
29 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
30 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
31 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
32 #define RENESAS_SDHI_SCC_TAPSET 0x804
33 #define RENESAS_SDHI_SCC_DT2FF 0x808
34 #define RENESAS_SDHI_SCC_CKSEL 0x80c
35 #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
36 #define RENESAS_SDHI_SCC_RVSCNTL 0x810
37 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
38 #define RENESAS_SDHI_SCC_RVSREQ 0x814
39 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
40 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
41 #define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
42 #define RENESAS_SDHI_SCC_SMPCMP 0x818
43 #define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR (BIT(24) | BIT(8))
44 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
45 #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
46 #define RENESAS_SDHI_SCC_TMPPORT2 0x81c
47 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
48 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
49 #define RENESAS_SDHI_SCC_TMPPORT3 0x828
50 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0 3
51 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1 2
52 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2 1
53 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3 0
54 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK 0x3
55 #define RENESAS_SDHI_SCC_TMPPORT4 0x82c
56 #define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
57 #define RENESAS_SDHI_SCC_TMPPORT5 0x830
58 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
59 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
60 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
61 #define RENESAS_SDHI_SCC_TMPPORT6 0x834
62 #define RENESAS_SDHI_SCC_TMPPORT7 0x838
63 #define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
64 #define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
65 #define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
67 #define RENESAS_SDHI_MAX_TAP 3
69 #define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
71 static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
72 { 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11,
73 15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 },
74 { 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15,
75 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
78 static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = {
79 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9,
80 15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 },
81 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
82 2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24}
85 static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = {
86 { 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10,
87 11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
88 { 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
89 13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 }
92 static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
93 { 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15,
94 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 },
95 { 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15,
96 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 }
99 static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
100 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
101 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
102 { 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11,
103 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
106 static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
108 /* On R-Car Gen3, MMC0 is at 0xee140000 */
109 return (uintptr_t)(priv->regbase) == 0xee140000;
112 static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
115 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
116 (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
117 RENESAS_SDHI_SCC_TMPPORT5);
119 /* access start and stop */
120 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
121 RENESAS_SDHI_SCC_TMPPORT4);
122 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
124 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
127 static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
130 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
131 (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
132 RENESAS_SDHI_SCC_TMPPORT5);
133 tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
135 /* access start and stop */
136 tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
137 RENESAS_SDHI_SCC_TMPPORT4);
138 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
141 static bool renesas_sdhi_check_scc_error(struct udevice *dev)
143 struct tmio_sd_priv *priv = dev_get_priv(dev);
144 struct mmc *mmc = mmc_get_mmc_dev(dev);
145 unsigned long new_tap = priv->tap_set;
146 unsigned long error_tap = priv->tap_set;
149 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
150 (mmc->selected_mode != UHS_SDR104) &&
151 (mmc->selected_mode != MMC_HS_200) &&
152 (mmc->selected_mode != MMC_HS_400) &&
156 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
157 /* Handle automatic tuning correction */
158 if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
159 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
160 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
161 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
168 /* Handle manual tuning correction */
169 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
170 if (!reg) /* No error */
173 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
175 if (mmc->selected_mode == MMC_HS_400) {
177 * Correction Error Status contains CMD and DAT signal status.
178 * In HS400, DAT signal based on DS signal, not CLK.
179 * Therefore, use only CMD status.
181 smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
182 RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
186 return false; /* No error in CMD signal */
187 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
188 new_tap = (priv->tap_set +
189 priv->tap_num + 1) % priv->tap_num;
190 error_tap = (priv->tap_set +
191 priv->tap_num - 1) % priv->tap_num;
193 case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
194 new_tap = (priv->tap_set +
195 priv->tap_num - 1) % priv->tap_num;
196 error_tap = (priv->tap_set +
197 priv->tap_num + 1) % priv->tap_num;
200 return true; /* Need re-tune */
203 if (priv->hs400_bad_tap & BIT(new_tap)) {
205 * New tap is bad tap (cannot change).
206 * Compare with HS200 tuning result.
207 * In HS200 tuning, when smpcmp[error_tap]
208 * is OK, retune is executed.
210 if (priv->smpcmp & BIT(error_tap))
211 return true; /* Need retune */
213 return false; /* cannot change */
216 priv->tap_set = new_tap;
218 if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
219 return true; /* Need re-tune */
220 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
221 priv->tap_set = (priv->tap_set +
222 priv->tap_num + 1) % priv->tap_num;
223 else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
224 priv->tap_set = (priv->tap_set +
225 priv->tap_num - 1) % priv->tap_num;
230 /* Set TAP position */
231 tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
232 RENESAS_SDHI_SCC_TAPSET);
237 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
241 if (!priv->adjust_hs400_enable)
244 if (!priv->needs_adjust_hs400)
247 if (!priv->adjust_hs400_calib_table)
251 * Enabled Manual adjust HS400 mode
253 * 1) Disabled Write Protect
254 * W(addr=0x00, WP_DISABLE_CODE)
256 * 2) Read Calibration code
257 * read_value = R(addr=0x26)
258 * 3) Refer to calibration table
259 * Calibration code = table[read_value]
260 * 4) Enabled Manual Calibration
261 * W(addr=0x22, manual mode | Calibration code)
262 * 5) Set Offset value to TMPPORT3 Reg
264 sd_scc_tmpport_write32(priv, 0x00,
265 RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
266 calib_code = sd_scc_tmpport_read32(priv, 0x26);
267 calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
268 sd_scc_tmpport_write32(priv, 0x22,
269 RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
270 priv->adjust_hs400_calib_table[calib_code]);
271 tmio_sd_writel(priv, priv->adjust_hs400_offset,
272 RENESAS_SDHI_SCC_TMPPORT3);
275 priv->needs_adjust_hs400 = false;
278 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
281 /* Disabled Manual adjust HS400 mode
283 * 1) Disabled Write Protect
284 * W(addr=0x00, WP_DISABLE_CODE)
285 * 2) Disabled Manual Calibration
287 * 3) Clear offset value to TMPPORT3 Reg
289 sd_scc_tmpport_write32(priv, 0x00,
290 RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
291 sd_scc_tmpport_write32(priv, 0x22, 0);
292 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
295 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
300 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
302 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
303 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
304 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
306 /* Set sampling clock selection range */
307 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
308 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
309 RENESAS_SDHI_SCC_DTCNTL);
311 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
312 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
313 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
315 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
316 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
317 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
319 tmio_sd_writel(priv, 0x300 /* scc_tappos */,
320 RENESAS_SDHI_SCC_DT2FF);
322 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
323 reg |= TMIO_SD_CLKCTL_SCLKEN;
324 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
327 return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
328 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
329 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
332 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
337 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
338 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
339 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
341 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
342 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
343 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
345 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
346 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
347 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
348 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
350 /* Disable HS400 mode adjustment */
351 renesas_sdhi_adjust_hs400_mode_disable(priv);
353 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
354 reg |= TMIO_SD_CLKCTL_SCLKEN;
355 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
357 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
358 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
359 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
361 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
362 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
363 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
366 static int renesas_sdhi_hs400(struct udevice *dev)
368 struct tmio_sd_priv *priv = dev_get_priv(dev);
369 struct mmc *mmc = mmc_get_mmc_dev(dev);
370 bool hs400 = (mmc->selected_mode == MMC_HS_400);
371 int ret, taps = hs400 ? priv->nrtaps : 8;
372 unsigned long new_tap;
375 if (taps == 4) /* HS400 on 4tap SoC needs different clock */
376 ret = clk_set_rate(&priv->clk, 400000000);
378 ret = clk_set_rate(&priv->clk, 200000000);
382 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
383 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
384 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
386 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
388 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
389 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
391 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
392 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
395 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
397 /* Disable HS400 mode adjustment */
399 renesas_sdhi_adjust_hs400_mode_disable(priv);
401 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
402 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
403 RENESAS_SDHI_SCC_DTCNTL);
406 if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
407 new_tap = (priv->tap_set +
408 priv->tap_num + 1) % priv->tap_num;
410 if (priv->hs400_bad_tap & BIT(new_tap))
411 new_tap = (priv->tap_set +
412 priv->tap_num - 1) % priv->tap_num;
414 if (priv->hs400_bad_tap & BIT(new_tap)) {
415 new_tap = priv->tap_set;
416 debug("Three consecutive bad tap is prohibited\n");
419 priv->tap_set = new_tap;
420 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
424 tmio_sd_writel(priv, priv->tap_set >> 1,
425 RENESAS_SDHI_SCC_TAPSET);
426 tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
427 RENESAS_SDHI_SCC_DT2FF);
429 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
430 tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
433 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
434 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
435 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
437 /* Execute adjust hs400 offset after setting to HS400 mode */
439 priv->needs_adjust_hs400 = true;
444 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
447 /* Set sampling clock position */
448 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
451 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
453 /* Get comparison of sampling data */
454 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
457 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
460 unsigned long tap_cnt; /* counter of tuning success */
461 unsigned long tap_start;/* start position of tuning success */
462 unsigned long tap_end; /* end position of tuning success */
463 unsigned long ntap; /* temporary counter of tuning success */
464 unsigned long match_cnt;/* counter of matching data */
469 priv->needs_adjust_hs400 = false;
471 /* Clear SCC_RVSREQ */
472 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
474 /* Merge the results */
475 for (i = 0; i < priv->tap_num * 2; i++) {
476 if (!(taps & BIT(i))) {
477 taps &= ~BIT(i % priv->tap_num);
478 taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
480 if (!(priv->smpcmp & BIT(i))) {
481 priv->smpcmp &= ~BIT(i % priv->tap_num);
482 priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
487 * Find the longest consecutive run of successful probes. If that
488 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
489 * center index as the tap.
495 for (i = 0; i < priv->tap_num * 2; i++) {
499 if (ntap > tap_cnt) {
500 tap_start = i - ntap;
508 if (ntap > tap_cnt) {
509 tap_start = i - ntap;
515 * If all of the TAP is OK, the sampling clock position is selected by
516 * identifying the change point of data.
518 if (tap_cnt == priv->tap_num * 2) {
523 for (i = 0; i < priv->tap_num * 2; i++) {
524 if (priv->smpcmp & BIT(i))
527 if (ntap > match_cnt) {
528 tap_start = i - ntap;
535 if (ntap > match_cnt) {
536 tap_start = i - ntap;
542 } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
546 priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
551 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
553 /* Enable auto re-tuning */
554 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
555 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
556 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
561 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
563 struct tmio_sd_priv *priv = dev_get_priv(dev);
564 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
565 struct mmc *mmc = upriv->mmc;
566 unsigned int tap_num;
567 unsigned int taps = 0;
571 /* Only supported on Renesas RCar */
572 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
575 /* clock tuning is not needed for upto 52MHz */
576 if (!((mmc->selected_mode == MMC_HS_200) ||
577 (mmc->selected_mode == MMC_HS_400) ||
578 (mmc->selected_mode == UHS_SDR104) ||
579 (mmc->selected_mode == UHS_SDR50)))
582 tap_num = renesas_sdhi_init_tuning(priv);
584 /* Tuning is not supported */
587 priv->tap_num = tap_num;
589 if (priv->tap_num * 2 >= sizeof(taps) * 8) {
591 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
597 /* Issue CMD19 twice for each tap */
598 for (i = 0; i < 2 * priv->tap_num; i++) {
599 renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
601 /* Force PIO for the tuning */
603 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
605 ret = mmc_send_tuning(mmc, opcode, NULL);
612 ret = renesas_sdhi_compare_scc_data(priv);
614 priv->smpcmp |= BIT(i);
619 ret = renesas_sdhi_select_tuning(priv, taps);
623 dev_warn(dev, "Tuning procedure failed\n");
624 renesas_sdhi_reset_tuning(priv);
630 static int renesas_sdhi_hs400(struct udevice *dev)
636 static int renesas_sdhi_set_ios(struct udevice *dev)
638 struct tmio_sd_priv *priv = dev_get_priv(dev);
642 /* Stop the clock before changing its rate to avoid a glitch signal */
643 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
644 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
645 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
647 ret = renesas_sdhi_hs400(dev);
651 ret = tmio_sd_set_ios(dev);
655 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
656 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
657 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
658 struct mmc *mmc = mmc_get_mmc_dev(dev);
659 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
660 (mmc->selected_mode != UHS_SDR104) &&
661 (mmc->selected_mode != MMC_HS_200) &&
662 (mmc->selected_mode != MMC_HS_400)) {
663 renesas_sdhi_reset_tuning(priv);
670 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
671 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
674 int ret = -ETIMEDOUT;
676 bool target_dat0_high = !!state;
677 struct tmio_sd_priv *priv = dev_get_priv(dev);
679 timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
680 while (timeout_us--) {
681 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
682 if (dat0_high == target_dat0_high) {
693 #define RENESAS_SDHI_DMA_ALIGNMENT 128
695 static int renesas_sdhi_addr_aligned_gen(uintptr_t ubuf,
696 size_t len, size_t len_aligned)
698 /* Check if start is aligned */
699 if (!IS_ALIGNED(ubuf, RENESAS_SDHI_DMA_ALIGNMENT)) {
700 debug("Unaligned buffer address %lx\n", ubuf);
704 /* Check if length is aligned */
705 if (len != len_aligned) {
706 debug("Unaligned buffer length %zu\n", len);
710 #ifdef CONFIG_PHYS_64BIT
711 /* Check if below 32bit boundary */
712 if ((ubuf >> 32) || (ubuf + len_aligned) >> 32) {
713 debug("Buffer above 32bit boundary %lx-%lx\n",
714 ubuf, ubuf + len_aligned);
723 static int renesas_sdhi_addr_aligned(struct bounce_buffer *state)
725 uintptr_t ubuf = (uintptr_t)state->user_buffer;
727 return renesas_sdhi_addr_aligned_gen(ubuf, state->len,
731 static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
732 struct mmc_data *data)
734 struct bounce_buffer bbstate;
735 unsigned int bbflags;
742 if (data->flags & MMC_DATA_READ) {
744 bbflags = GEN_BB_WRITE;
746 buf = (void *)data->src;
747 bbflags = GEN_BB_READ;
749 len = data->blocks * data->blocksize;
751 ret = bounce_buffer_start_extalign(&bbstate, buf, len, bbflags,
752 RENESAS_SDHI_DMA_ALIGNMENT,
753 renesas_sdhi_addr_aligned);
755 * If the amount of data to transfer is too large, we can get
756 * -ENOMEM when starting the bounce buffer. If that happens,
757 * fall back to PIO as it was before, otherwise use the BB.
761 if (data->flags & MMC_DATA_READ)
762 data->dest = bbstate.bounce_buffer;
764 data->src = bbstate.bounce_buffer;
768 ret = tmio_sd_send_cmd(dev, cmd, data);
771 buf = bbstate.user_buffer;
773 bounce_buffer_stop(&bbstate);
775 if (data->flags & MMC_DATA_READ)
784 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
785 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
786 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
787 struct tmio_sd_priv *priv = dev_get_priv(dev);
789 renesas_sdhi_check_scc_error(dev);
791 if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
792 renesas_sdhi_adjust_hs400_mode_enable(priv);
798 int renesas_sdhi_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt)
800 struct tmio_sd_priv *priv = dev_get_priv(dev);
801 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
802 struct mmc *mmc = upriv->mmc;
803 size_t len = blkcnt * mmc->read_bl_len;
804 size_t len_align = roundup(len, RENESAS_SDHI_DMA_ALIGNMENT);
806 if (renesas_sdhi_addr_aligned_gen((uintptr_t)dst, len, len_align)) {
807 if (priv->quirks & TMIO_SD_CAP_16BIT)
812 return (CONFIG_SYS_MALLOC_LEN / 4) / mmc->read_bl_len;
816 static const struct dm_mmc_ops renesas_sdhi_ops = {
817 .send_cmd = renesas_sdhi_send_cmd,
818 .set_ios = renesas_sdhi_set_ios,
819 .get_cd = tmio_sd_get_cd,
820 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
821 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
822 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
823 .execute_tuning = renesas_sdhi_execute_tuning,
825 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
826 .wait_dat0 = renesas_sdhi_wait_dat0,
828 .get_b_max = renesas_sdhi_get_b_max,
831 #define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
832 #define RENESAS_GEN3_QUIRKS \
833 TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
835 static const struct udevice_id renesas_sdhi_match[] = {
836 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
837 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
838 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
839 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
840 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
841 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
842 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
843 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
844 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
845 { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
846 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
850 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
852 return clk_get_rate(&priv->clk);
855 static void renesas_sdhi_filter_caps(struct udevice *dev)
857 struct tmio_sd_priv *priv = dev_get_priv(dev);
859 if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
862 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
863 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
864 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
865 struct tmio_sd_plat *plat = dev_get_platdata(dev);
867 /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
868 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
869 (rmobile_get_cpu_rev_integer() <= 1)) ||
870 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
871 (rmobile_get_cpu_rev_integer() == 1) &&
872 (rmobile_get_cpu_rev_fraction() < 2)))
873 plat->cfg.host_caps &= ~MMC_MODE_HS400;
875 /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
876 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
877 (rmobile_get_cpu_rev_integer() >= 2)) ||
878 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
879 (rmobile_get_cpu_rev_integer() == 1) &&
880 (rmobile_get_cpu_rev_fraction() == 2)) ||
881 (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
882 priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
884 /* H3 ES3.0 can use HS400 with manual adjustment */
885 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
886 (rmobile_get_cpu_rev_integer() >= 3)) {
887 priv->adjust_hs400_enable = true;
888 priv->adjust_hs400_offset = 0;
889 priv->adjust_hs400_calib_table =
890 r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
893 /* M3W ES1.2 can use HS400 with manual adjustment */
894 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
895 (rmobile_get_cpu_rev_integer() == 1) &&
896 (rmobile_get_cpu_rev_fraction() == 2)) {
897 priv->adjust_hs400_enable = true;
898 priv->adjust_hs400_offset = 3;
899 priv->adjust_hs400_calib_table =
900 r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)];
903 /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
904 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
905 (rmobile_get_cpu_rev_integer() == 1) &&
906 (rmobile_get_cpu_rev_fraction() > 2)) {
907 priv->adjust_hs400_enable = true;
908 priv->adjust_hs400_offset = 0;
909 priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
910 priv->adjust_hs400_calib_table =
911 r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)];
914 /* M3N can use HS400 with manual adjustment */
915 if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
916 priv->adjust_hs400_enable = true;
917 priv->adjust_hs400_offset = 3;
918 priv->adjust_hs400_calib_table =
919 r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
922 /* E3 can use HS400 with manual adjustment */
923 if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
924 priv->adjust_hs400_enable = true;
925 priv->adjust_hs400_offset = 3;
926 priv->adjust_hs400_calib_table =
927 r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
930 /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
931 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
932 (rmobile_get_cpu_rev_integer() <= 2)) ||
933 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
934 (rmobile_get_cpu_rev_integer() == 1) &&
935 (rmobile_get_cpu_rev_fraction() <= 2)))
940 /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
941 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
942 (rmobile_get_cpu_rev_integer() <= 1)) ||
943 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
944 (rmobile_get_cpu_rev_integer() == 1) &&
945 (rmobile_get_cpu_rev_fraction() == 0)))
946 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
948 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
951 static int renesas_sdhi_probe(struct udevice *dev)
953 struct tmio_sd_priv *priv = dev_get_priv(dev);
954 u32 quirks = dev_get_driver_data(dev);
955 struct fdt_resource reg_res;
956 DECLARE_GLOBAL_DATA_PTR;
959 priv->clk_get_rate = renesas_sdhi_clk_get_rate;
961 if (quirks == RENESAS_GEN2_QUIRKS) {
962 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
965 dev_err(dev, "\"reg\" resource not found, ret=%i\n",
970 if (fdt_resource_size(®_res) == 0x100)
971 quirks |= TMIO_SD_CAP_16BIT;
974 ret = clk_get_by_index(dev, 0, &priv->clk);
976 dev_err(dev, "failed to get host clock\n");
980 /* set to max rate */
981 ret = clk_set_rate(&priv->clk, 200000000);
983 dev_err(dev, "failed to set rate for host clock\n");
984 clk_free(&priv->clk);
988 ret = clk_enable(&priv->clk);
990 dev_err(dev, "failed to enable host clock\n");
994 priv->quirks = quirks;
995 ret = tmio_sd_probe(dev, quirks);
997 renesas_sdhi_filter_caps(dev);
999 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
1000 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
1001 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1002 if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
1003 renesas_sdhi_reset_tuning(priv);
1008 U_BOOT_DRIVER(renesas_sdhi) = {
1009 .name = "renesas-sdhi",
1011 .of_match = renesas_sdhi_match,
1012 .bind = tmio_sd_bind,
1013 .probe = renesas_sdhi_probe,
1014 .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
1015 .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
1016 .ops = &renesas_sdhi_ops,