1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
11 #include <linux/compat.h>
12 #include <linux/dma-direction.h>
14 #include <linux/sizes.h>
15 #include <power/regulator.h>
16 #include <asm/unaligned.h>
18 #include "tmio-common.h"
20 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
21 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
22 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
25 #define RENESAS_SDHI_SCC_DTCNTL 0x800
26 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
27 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
28 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
29 #define RENESAS_SDHI_SCC_TAPSET 0x804
30 #define RENESAS_SDHI_SCC_DT2FF 0x808
31 #define RENESAS_SDHI_SCC_CKSEL 0x80c
32 #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
33 #define RENESAS_SDHI_SCC_RVSCNTL 0x810
34 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
35 #define RENESAS_SDHI_SCC_RVSREQ 0x814
36 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
37 #define RENESAS_SDHI_SCC_SMPCMP 0x818
38 #define RENESAS_SDHI_SCC_TMPPORT2 0x81c
39 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
40 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
42 #define RENESAS_SDHI_MAX_TAP 3
44 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
49 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
51 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
52 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
53 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
55 /* Set sampling clock selection range */
56 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
57 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
58 RENESAS_SDHI_SCC_DTCNTL);
60 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
61 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
62 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
64 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
65 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
66 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
68 tmio_sd_writel(priv, 0x300 /* scc_tappos */,
69 RENESAS_SDHI_SCC_DT2FF);
71 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
72 reg |= TMIO_SD_CLKCTL_SCLKEN;
73 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
76 return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
77 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
78 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
81 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
86 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
87 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
88 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
90 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
91 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
92 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
94 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
95 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
96 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
97 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
99 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
100 reg |= TMIO_SD_CLKCTL_SCLKEN;
101 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
103 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
104 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
105 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
107 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
108 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
109 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
112 static int renesas_sdhi_hs400(struct udevice *dev)
114 struct tmio_sd_priv *priv = dev_get_priv(dev);
115 struct mmc *mmc = mmc_get_mmc_dev(dev);
116 bool hs400 = (mmc->selected_mode == MMC_HS_400);
117 int ret, taps = hs400 ? priv->nrtaps : 8;
120 if (taps == 4) /* HS400 on 4tap SoC needs different clock */
121 ret = clk_set_rate(&priv->clk, 400000000);
123 ret = clk_set_rate(&priv->clk, 200000000);
127 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
129 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
131 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
132 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
134 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
135 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
138 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
140 tmio_sd_writel(priv, (taps << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
141 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
142 RENESAS_SDHI_SCC_DTCNTL);
145 tmio_sd_writel(priv, priv->tap_set >> 1,
146 RENESAS_SDHI_SCC_TAPSET);
148 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
151 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
152 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
153 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
155 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
156 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
157 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
162 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
165 /* Set sampling clock position */
166 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
169 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
171 /* Get comparison of sampling data */
172 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
175 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
176 unsigned int tap_num, unsigned int taps,
179 unsigned long tap_cnt; /* counter of tuning success */
180 unsigned long tap_start;/* start position of tuning success */
181 unsigned long tap_end; /* end position of tuning success */
182 unsigned long ntap; /* temporary counter of tuning success */
183 unsigned long match_cnt;/* counter of matching data */
188 /* Clear SCC_RVSREQ */
189 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
191 /* Merge the results */
192 for (i = 0; i < tap_num * 2; i++) {
193 if (!(taps & BIT(i))) {
194 taps &= ~BIT(i % tap_num);
195 taps &= ~BIT((i % tap_num) + tap_num);
197 if (!(smpcmp & BIT(i))) {
198 smpcmp &= ~BIT(i % tap_num);
199 smpcmp &= ~BIT((i % tap_num) + tap_num);
204 * Find the longest consecutive run of successful probes. If that
205 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
206 * center index as the tap.
212 for (i = 0; i < tap_num * 2; i++) {
216 if (ntap > tap_cnt) {
217 tap_start = i - ntap;
225 if (ntap > tap_cnt) {
226 tap_start = i - ntap;
232 * If all of the TAP is OK, the sampling clock position is selected by
233 * identifying the change point of data.
235 if (tap_cnt == tap_num * 2) {
240 for (i = 0; i < tap_num * 2; i++) {
244 if (ntap > match_cnt) {
245 tap_start = i - ntap;
252 if (ntap > match_cnt) {
253 tap_start = i - ntap;
259 } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
263 priv->tap_set = ((tap_start + tap_end) / 2) % tap_num;
268 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
270 /* Enable auto re-tuning */
271 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
272 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
273 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
278 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
280 struct tmio_sd_priv *priv = dev_get_priv(dev);
281 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
282 struct mmc *mmc = upriv->mmc;
283 unsigned int tap_num;
284 unsigned int taps = 0, smpcmp = 0;
288 /* Only supported on Renesas RCar */
289 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
292 /* clock tuning is not needed for upto 52MHz */
293 if (!((mmc->selected_mode == MMC_HS_200) ||
294 (mmc->selected_mode == MMC_HS_400) ||
295 (mmc->selected_mode == UHS_SDR104) ||
296 (mmc->selected_mode == UHS_SDR50)))
299 tap_num = renesas_sdhi_init_tuning(priv);
301 /* Tuning is not supported */
304 if (tap_num * 2 >= sizeof(taps) * 8) {
306 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
310 /* Issue CMD19 twice for each tap */
311 for (i = 0; i < 2 * tap_num; i++) {
312 renesas_sdhi_prepare_tuning(priv, i % tap_num);
314 /* Force PIO for the tuning */
316 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
318 ret = mmc_send_tuning(mmc, opcode, NULL);
325 ret = renesas_sdhi_compare_scc_data(priv);
332 ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
336 dev_warn(dev, "Tuning procedure failed\n");
337 renesas_sdhi_reset_tuning(priv);
343 static int renesas_sdhi_hs400(struct udevice *dev)
349 static int renesas_sdhi_set_ios(struct udevice *dev)
351 struct tmio_sd_priv *priv = dev_get_priv(dev);
355 /* Stop the clock before changing its rate to avoid a glitch signal */
356 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
357 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
358 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
360 ret = renesas_sdhi_hs400(dev);
364 ret = tmio_sd_set_ios(dev);
368 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
369 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
370 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
371 struct mmc *mmc = mmc_get_mmc_dev(dev);
372 if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
373 (mmc->selected_mode != UHS_SDR104) &&
374 (mmc->selected_mode != MMC_HS_200) &&
375 (mmc->selected_mode != MMC_HS_400)) {
376 renesas_sdhi_reset_tuning(priv);
383 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
384 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout)
386 int ret = -ETIMEDOUT;
388 bool target_dat0_high = !!state;
389 struct tmio_sd_priv *priv = dev_get_priv(dev);
391 timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
393 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
394 if (dat0_high == target_dat0_high) {
405 static const struct dm_mmc_ops renesas_sdhi_ops = {
406 .send_cmd = tmio_sd_send_cmd,
407 .set_ios = renesas_sdhi_set_ios,
408 .get_cd = tmio_sd_get_cd,
409 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
410 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
411 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
412 .execute_tuning = renesas_sdhi_execute_tuning,
414 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
415 .wait_dat0 = renesas_sdhi_wait_dat0,
419 #define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
420 #define RENESAS_GEN3_QUIRKS \
421 TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
423 static const struct udevice_id renesas_sdhi_match[] = {
424 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
425 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
426 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
427 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
428 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
429 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
430 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
431 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
432 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
433 { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
434 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
438 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
440 return clk_get_rate(&priv->clk);
443 static void renesas_sdhi_filter_caps(struct udevice *dev)
445 struct tmio_sd_plat *plat = dev_get_platdata(dev);
446 struct tmio_sd_priv *priv = dev_get_priv(dev);
448 if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
451 /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1 */
452 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
453 (rmobile_get_cpu_rev_integer() <= 1)) ||
454 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
455 (rmobile_get_cpu_rev_integer() == 1) &&
456 (rmobile_get_cpu_rev_fraction() <= 1)))
457 plat->cfg.host_caps &= ~MMC_MODE_HS400;
459 /* H3 ES2.0 uses 4 tuning taps */
460 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
461 (rmobile_get_cpu_rev_integer() == 2))
467 static int renesas_sdhi_probe(struct udevice *dev)
469 struct tmio_sd_priv *priv = dev_get_priv(dev);
470 u32 quirks = dev_get_driver_data(dev);
471 struct fdt_resource reg_res;
472 DECLARE_GLOBAL_DATA_PTR;
475 priv->clk_get_rate = renesas_sdhi_clk_get_rate;
477 if (quirks == RENESAS_GEN2_QUIRKS) {
478 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
481 dev_err(dev, "\"reg\" resource not found, ret=%i\n",
486 if (fdt_resource_size(®_res) == 0x100)
487 quirks |= TMIO_SD_CAP_16BIT;
490 ret = clk_get_by_index(dev, 0, &priv->clk);
492 dev_err(dev, "failed to get host clock\n");
496 /* set to max rate */
497 ret = clk_set_rate(&priv->clk, 200000000);
499 dev_err(dev, "failed to set rate for host clock\n");
500 clk_free(&priv->clk);
504 ret = clk_enable(&priv->clk);
506 dev_err(dev, "failed to enable host clock\n");
510 ret = tmio_sd_probe(dev, quirks);
512 renesas_sdhi_filter_caps(dev);
514 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
515 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
516 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
517 if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
518 renesas_sdhi_reset_tuning(priv);
523 U_BOOT_DRIVER(renesas_sdhi) = {
524 .name = "renesas-sdhi",
526 .of_match = renesas_sdhi_match,
527 .bind = tmio_sd_bind,
528 .probe = renesas_sdhi_probe,
529 .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
530 .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
531 .ops = &renesas_sdhi_ops,