1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
11 #include <linux/compat.h>
12 #include <linux/dma-direction.h>
14 #include <linux/sizes.h>
15 #include <power/regulator.h>
16 #include <asm/unaligned.h>
18 #include "tmio-common.h"
20 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
23 #define RENESAS_SDHI_SCC_DTCNTL 0x800
24 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
25 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
26 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
27 #define RENESAS_SDHI_SCC_TAPSET 0x804
28 #define RENESAS_SDHI_SCC_DT2FF 0x808
29 #define RENESAS_SDHI_SCC_CKSEL 0x80c
30 #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
31 #define RENESAS_SDHI_SCC_RVSCNTL 0x810
32 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
33 #define RENESAS_SDHI_SCC_RVSREQ 0x814
34 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
35 #define RENESAS_SDHI_SCC_SMPCMP 0x818
36 #define RENESAS_SDHI_SCC_TMPPORT2 0x81c
37 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
38 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
40 #define RENESAS_SDHI_MAX_TAP 3
42 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
47 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
49 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
50 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
51 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
53 /* Set sampling clock selection range */
54 tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
55 RENESAS_SDHI_SCC_DTCNTL_TAPEN,
56 RENESAS_SDHI_SCC_DTCNTL);
58 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
59 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
60 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
62 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
63 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
64 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
66 tmio_sd_writel(priv, 0x300 /* scc_tappos */,
67 RENESAS_SDHI_SCC_DT2FF);
69 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
70 reg |= TMIO_SD_CLKCTL_SCLKEN;
71 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
74 return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
75 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
76 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
79 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
84 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
85 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
86 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
88 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
89 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
90 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
92 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
93 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
94 RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
95 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
97 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
98 reg |= TMIO_SD_CLKCTL_SCLKEN;
99 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
101 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
102 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
103 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
105 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
106 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
107 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
110 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
113 /* Set sampling clock position */
114 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
117 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
119 /* Get comparison of sampling data */
120 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
123 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
124 unsigned int tap_num, unsigned int taps,
127 unsigned long tap_cnt; /* counter of tuning success */
128 unsigned long tap_set; /* tap position */
129 unsigned long tap_start;/* start position of tuning success */
130 unsigned long tap_end; /* end position of tuning success */
131 unsigned long ntap; /* temporary counter of tuning success */
132 unsigned long match_cnt;/* counter of matching data */
137 /* Clear SCC_RVSREQ */
138 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
140 /* Merge the results */
141 for (i = 0; i < tap_num * 2; i++) {
142 if (!(taps & BIT(i))) {
143 taps &= ~BIT(i % tap_num);
144 taps &= ~BIT((i % tap_num) + tap_num);
146 if (!(smpcmp & BIT(i))) {
147 smpcmp &= ~BIT(i % tap_num);
148 smpcmp &= ~BIT((i % tap_num) + tap_num);
153 * Find the longest consecutive run of successful probes. If that
154 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
155 * center index as the tap.
161 for (i = 0; i < tap_num * 2; i++) {
165 if (ntap > tap_cnt) {
166 tap_start = i - ntap;
174 if (ntap > tap_cnt) {
175 tap_start = i - ntap;
181 * If all of the TAP is OK, the sampling clock position is selected by
182 * identifying the change point of data.
184 if (tap_cnt == tap_num * 2) {
189 for (i = 0; i < tap_num * 2; i++) {
193 if (ntap > match_cnt) {
194 tap_start = i - ntap;
201 if (ntap > match_cnt) {
202 tap_start = i - ntap;
208 } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
212 tap_set = ((tap_start + tap_end) / 2) % tap_num;
217 tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
219 /* Enable auto re-tuning */
220 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
221 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
222 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
227 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
229 struct tmio_sd_priv *priv = dev_get_priv(dev);
230 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
231 struct mmc *mmc = upriv->mmc;
232 unsigned int tap_num;
233 unsigned int taps = 0, smpcmp = 0;
237 /* Only supported on Renesas RCar */
238 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
241 /* clock tuning is not needed for upto 52MHz */
242 if (!((mmc->selected_mode == MMC_HS_200) ||
243 (mmc->selected_mode == UHS_SDR104) ||
244 (mmc->selected_mode == UHS_SDR50)))
247 tap_num = renesas_sdhi_init_tuning(priv);
249 /* Tuning is not supported */
252 if (tap_num * 2 >= sizeof(taps) * 8) {
254 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
258 /* Issue CMD19 twice for each tap */
259 for (i = 0; i < 2 * tap_num; i++) {
260 renesas_sdhi_prepare_tuning(priv, i % tap_num);
262 /* Force PIO for the tuning */
264 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
266 ret = mmc_send_tuning(mmc, opcode, NULL);
273 ret = renesas_sdhi_compare_scc_data(priv);
280 ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
284 dev_warn(dev, "Tuning procedure failed\n");
285 renesas_sdhi_reset_tuning(priv);
292 static int renesas_sdhi_set_ios(struct udevice *dev)
294 int ret = tmio_sd_set_ios(dev);
298 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
299 struct tmio_sd_priv *priv = dev_get_priv(dev);
301 if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
302 renesas_sdhi_reset_tuning(priv);
308 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
309 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout)
311 int ret = -ETIMEDOUT;
313 bool target_dat0_high = !!state;
314 struct tmio_sd_priv *priv = dev_get_priv(dev);
316 timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
318 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
319 if (dat0_high == target_dat0_high) {
330 static const struct dm_mmc_ops renesas_sdhi_ops = {
331 .send_cmd = tmio_sd_send_cmd,
332 .set_ios = renesas_sdhi_set_ios,
333 .get_cd = tmio_sd_get_cd,
334 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
335 .execute_tuning = renesas_sdhi_execute_tuning,
337 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
338 .wait_dat0 = renesas_sdhi_wait_dat0,
342 #define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
343 #define RENESAS_GEN3_QUIRKS \
344 TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
346 static const struct udevice_id renesas_sdhi_match[] = {
347 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
348 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
349 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
350 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
351 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
352 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
353 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
354 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
355 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
356 { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
357 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
361 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
363 return clk_get_rate(&priv->clk);
366 static void renesas_sdhi_filter_caps(struct udevice *dev)
368 struct tmio_sd_plat *plat = dev_get_platdata(dev);
369 struct tmio_sd_priv *priv = dev_get_priv(dev);
371 if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
374 /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1 */
375 if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
376 (rmobile_get_cpu_rev_integer() <= 1)) ||
377 ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
378 (rmobile_get_cpu_rev_integer() == 1) &&
379 (rmobile_get_cpu_rev_fraction() <= 1)))
380 plat->cfg.host_caps &= ~MMC_MODE_HS400;
383 static int renesas_sdhi_probe(struct udevice *dev)
385 struct tmio_sd_priv *priv = dev_get_priv(dev);
386 u32 quirks = dev_get_driver_data(dev);
387 struct fdt_resource reg_res;
388 DECLARE_GLOBAL_DATA_PTR;
391 priv->clk_get_rate = renesas_sdhi_clk_get_rate;
393 if (quirks == RENESAS_GEN2_QUIRKS) {
394 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
397 dev_err(dev, "\"reg\" resource not found, ret=%i\n",
402 if (fdt_resource_size(®_res) == 0x100)
403 quirks |= TMIO_SD_CAP_16BIT;
406 ret = clk_get_by_index(dev, 0, &priv->clk);
408 dev_err(dev, "failed to get host clock\n");
412 /* set to max rate */
413 ret = clk_set_rate(&priv->clk, 200000000);
415 dev_err(dev, "failed to set rate for host clock\n");
416 clk_free(&priv->clk);
420 ret = clk_enable(&priv->clk);
422 dev_err(dev, "failed to enable host clock\n");
426 ret = tmio_sd_probe(dev, quirks);
428 renesas_sdhi_filter_caps(dev);
430 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
431 if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
432 renesas_sdhi_reset_tuning(priv);
437 U_BOOT_DRIVER(renesas_sdhi) = {
438 .name = "renesas-sdhi",
440 .of_match = renesas_sdhi_match,
441 .bind = tmio_sd_bind,
442 .probe = renesas_sdhi_probe,
443 .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
444 .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
445 .ops = &renesas_sdhi_ops,