drivers/mmc/renesas-sdhi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <fdtdec.h>
   9 #include <mmc.h>
  10 #include <dm.h>
  11 #include <linux/compat.h>
  12 #include <linux/dma-direction.h>
  13 #include <linux/io.h>
  14 #include <linux/sizes.h>
  15 #include <power/regulator.h>
  16 #include <asm/unaligned.h>
  17
  18 #include "tmio-common.h"
  19
  20 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  21     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  22     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  23
  24 /* SCC registers */
  25 #define RENESAS_SDHI_SCC_DTCNTL                 0x800
  26 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN           BIT(0)
  27 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT    16
  28 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK     0xff
  29 #define RENESAS_SDHI_SCC_TAPSET                 0x804
  30 #define RENESAS_SDHI_SCC_DT2FF                  0x808
  31 #define RENESAS_SDHI_SCC_CKSEL                  0x80c
  32 #define RENESAS_SDHI_SCC_CKSEL_DTSEL            BIT(0)
  33 #define RENESAS_SDHI_SCC_RVSCNTL                0x810
  34 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN          BIT(0)
  35 #define RENESAS_SDHI_SCC_RVSREQ                 0x814
  36 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR          BIT(2)
  37 #define RENESAS_SDHI_SCC_SMPCMP                 0x818
  38 #define RENESAS_SDHI_SCC_TMPPORT2               0x81c
  39 #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN       BIT(31)
  40 #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL     BIT(4)
  41 #define RENESAS_SDHI_SCC_TMPPORT3               0x828
  42 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0      3
  43 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1      2
  44 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2      1
  45 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3      0
  46 #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK   0x3
  47 #define RENESAS_SDHI_SCC_TMPPORT4               0x82c
  48 #define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
  49 #define RENESAS_SDHI_SCC_TMPPORT5               0x830
  50 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R  BIT(8)
  51 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W  (0 << 8)
  52 #define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK  0x3F
  53 #define RENESAS_SDHI_SCC_TMPPORT6               0x834
  54 #define RENESAS_SDHI_SCC_TMPPORT7               0x838
  55 #define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE        0xa5000000
  56 #define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK        0x1f
  57 #define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE            BIT(7)
  58
  59 #define RENESAS_SDHI_MAX_TAP 3
  60
  61 static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
  62 {
  63         /* read mode */
  64         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
  65                        (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
  66                        RENESAS_SDHI_SCC_TMPPORT5);
  67
  68         /* access start and stop */
  69         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
  70                        RENESAS_SDHI_SCC_TMPPORT4);
  71         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
  72
  73         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
  74 }
  75
  76 static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
  77 {
  78         /* write mode */
  79         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
  80                        (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
  81                        RENESAS_SDHI_SCC_TMPPORT5);
  82         tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
  83
  84         /* access start and stop */
  85         tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
  86                        RENESAS_SDHI_SCC_TMPPORT4);
  87         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
  88 }
  89
  90 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
  91 {
  92         u32 calib_code;
  93
  94         if (!priv->adjust_hs400_enable)
  95                 return;
  96
  97         if (!priv->needs_adjust_hs400)
  98                 return;
  99
 100         /*
 101          * Enabled Manual adjust HS400 mode
 102          *
 103          * 1) Disabled Write Protect
 104          *    W(addr=0x00, WP_DISABLE_CODE)
 105          * 2) Read Calibration code and adjust
 106          *    R(addr=0x26) - adjust value
 107          * 3) Enabled Manual Calibration
 108          *    W(addr=0x22, manual mode | Calibration code)
 109          * 4) Set Offset value to TMPPORT3 Reg
 110          */
 111         sd_scc_tmpport_write32(priv, 0x00,
 112                                RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 113         calib_code = sd_scc_tmpport_read32(priv, 0x26);
 114         calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
 115         if (calib_code > priv->adjust_hs400_calibrate)
 116                 calib_code -= priv->adjust_hs400_calibrate;
 117         else
 118                 calib_code = 0;
 119         sd_scc_tmpport_write32(priv, 0x22,
 120                                RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
 121                                calib_code);
 122         tmio_sd_writel(priv, priv->adjust_hs400_offset,
 123                        RENESAS_SDHI_SCC_TMPPORT3);
 124
 125         /* Clear flag */
 126         priv->needs_adjust_hs400 = false;
 127 }
 128
 129 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
 130 {
 131
 132         /* Disabled Manual adjust HS400 mode
 133          *
 134          * 1) Disabled Write Protect
 135          *    W(addr=0x00, WP_DISABLE_CODE)
 136          * 2) Disabled Manual Calibration
 137          *    W(addr=0x22, 0)
 138          * 3) Clear offset value to TMPPORT3 Reg
 139          */
 140         sd_scc_tmpport_write32(priv, 0x00,
 141                                RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
 142         sd_scc_tmpport_write32(priv, 0x22, 0);
 143         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
 144 }
 145
 146 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
 147 {
 148         u32 reg;
 149
 150         /* Initialize SCC */
 151         tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
 152
 153         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 154         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 155         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 156
 157         /* Set sampling clock selection range */
 158         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 159                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 160                              RENESAS_SDHI_SCC_DTCNTL);
 161
 162         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 163         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 164         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 165
 166         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 167         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 168         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 169
 170         tmio_sd_writel(priv, 0x300 /* scc_tappos */,
 171                            RENESAS_SDHI_SCC_DT2FF);
 172
 173         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 174         reg |= TMIO_SD_CLKCTL_SCLKEN;
 175         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 176
 177         /* Read TAPNUM */
 178         return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
 179                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 180                 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 181 }
 182
 183 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
 184 {
 185         u32 reg;
 186
 187         /* Reset SCC */
 188         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 189         reg &= ~TMIO_SD_CLKCTL_SCLKEN;
 190         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 191
 192         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 193         reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
 194         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 195
 196         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 197         reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 198                  RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 199         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 200
 201         /* Disable HS400 mode adjustment */
 202         renesas_sdhi_adjust_hs400_mode_disable(priv);
 203
 204         reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 205         reg |= TMIO_SD_CLKCTL_SCLKEN;
 206         tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
 207
 208         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 209         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 210         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 211
 212         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 213         reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 214         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 215 }
 216
 217 static int renesas_sdhi_hs400(struct udevice *dev)
 218 {
 219         struct tmio_sd_priv *priv = dev_get_priv(dev);
 220         struct mmc *mmc = mmc_get_mmc_dev(dev);
 221         bool hs400 = (mmc->selected_mode == MMC_HS_400);
 222         int ret, taps = hs400 ? priv->nrtaps : 8;
 223         u32 reg;
 224
 225         if (taps == 4)  /* HS400 on 4tap SoC needs different clock */
 226                 ret = clk_set_rate(&priv->clk, 400000000);
 227         else
 228                 ret = clk_set_rate(&priv->clk, 200000000);
 229         if (ret < 0)
 230                 return ret;
 231
 232         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 233
 234         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
 235         if (hs400) {
 236                 reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 237                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
 238         } else {
 239                 reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
 240                        RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
 241         }
 242
 243         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
 244
 245         /* Disable HS400 mode adjustment */
 246         if (!hs400)
 247                 renesas_sdhi_adjust_hs400_mode_disable(priv);
 248
 249         tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
 250                              RENESAS_SDHI_SCC_DTCNTL_TAPEN,
 251                              RENESAS_SDHI_SCC_DTCNTL);
 252
 253         if (taps == 4) {
 254                 tmio_sd_writel(priv, priv->tap_set >> 1,
 255                                RENESAS_SDHI_SCC_TAPSET);
 256         } else {
 257                 tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 258         }
 259
 260         tmio_sd_writel(priv, hs400 ? 0x704 : 0x300,
 261                        RENESAS_SDHI_SCC_DT2FF);
 262
 263         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
 264         reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
 265         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
 266
 267         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 268         reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 269         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 270
 271         /* Execute adjust hs400 offset after setting to HS400 mode */
 272         if (hs400)
 273                 priv->needs_adjust_hs400 = true;
 274
 275         return 0;
 276 }
 277
 278 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
 279                                        unsigned long tap)
 280 {
 281         /* Set sampling clock position */
 282         tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
 283 }
 284
 285 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
 286 {
 287         /* Get comparison of sampling data */
 288         return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
 289 }
 290
 291 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
 292                                      unsigned int tap_num, unsigned int taps,
 293                                      unsigned int smpcmp)
 294 {
 295         unsigned long tap_cnt;  /* counter of tuning success */
 296         unsigned long tap_start;/* start position of tuning success */
 297         unsigned long tap_end;  /* end position of tuning success */
 298         unsigned long ntap;     /* temporary counter of tuning success */
 299         unsigned long match_cnt;/* counter of matching data */
 300         unsigned long i;
 301         bool select = false;
 302         u32 reg;
 303
 304         priv->needs_adjust_hs400 = false;
 305
 306         /* Clear SCC_RVSREQ */
 307         tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
 308
 309         /* Merge the results */
 310         for (i = 0; i < tap_num * 2; i++) {
 311                 if (!(taps & BIT(i))) {
 312                         taps &= ~BIT(i % tap_num);
 313                         taps &= ~BIT((i % tap_num) + tap_num);
 314                 }
 315                 if (!(smpcmp & BIT(i))) {
 316                         smpcmp &= ~BIT(i % tap_num);
 317                         smpcmp &= ~BIT((i % tap_num) + tap_num);
 318                 }
 319         }
 320
 321         /*
 322          * Find the longest consecutive run of successful probes.  If that
 323          * is more than RENESAS_SDHI_MAX_TAP probes long then use the
 324          * center index as the tap.
 325          */
 326         tap_cnt = 0;
 327         ntap = 0;
 328         tap_start = 0;
 329         tap_end = 0;
 330         for (i = 0; i < tap_num * 2; i++) {
 331                 if (taps & BIT(i))
 332                         ntap++;
 333                 else {
 334                         if (ntap > tap_cnt) {
 335                                 tap_start = i - ntap;
 336                                 tap_end = i - 1;
 337                                 tap_cnt = ntap;
 338                         }
 339                         ntap = 0;
 340                 }
 341         }
 342
 343         if (ntap > tap_cnt) {
 344                 tap_start = i - ntap;
 345                 tap_end = i - 1;
 346                 tap_cnt = ntap;
 347         }
 348
 349         /*
 350          * If all of the TAP is OK, the sampling clock position is selected by
 351          * identifying the change point of data.
 352          */
 353         if (tap_cnt == tap_num * 2) {
 354                 match_cnt = 0;
 355                 ntap = 0;
 356                 tap_start = 0;
 357                 tap_end = 0;
 358                 for (i = 0; i < tap_num * 2; i++) {
 359                         if (smpcmp & BIT(i))
 360                                 ntap++;
 361                         else {
 362                                 if (ntap > match_cnt) {
 363                                         tap_start = i - ntap;
 364                                         tap_end = i - 1;
 365                                         match_cnt = ntap;
 366                                 }
 367                                 ntap = 0;
 368                         }
 369                 }
 370                 if (ntap > match_cnt) {
 371                         tap_start = i - ntap;
 372                         tap_end = i - 1;
 373                         match_cnt = ntap;
 374                 }
 375                 if (match_cnt)
 376                         select = true;
 377         } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
 378                 select = true;
 379
 380         if (select)
 381                 priv->tap_set = ((tap_start + tap_end) / 2) % tap_num;
 382         else
 383                 return -EIO;
 384
 385         /* Set SCC */
 386         tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
 387
 388         /* Enable auto re-tuning */
 389         reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
 390         reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
 391         tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
 392
 393         return 0;
 394 }
 395
 396 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
 397 {
 398         struct tmio_sd_priv *priv = dev_get_priv(dev);
 399         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 400         struct mmc *mmc = upriv->mmc;
 401         unsigned int tap_num;
 402         unsigned int taps = 0, smpcmp = 0;
 403         int i, ret = 0;
 404         u32 caps;
 405
 406         /* Only supported on Renesas RCar */
 407         if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
 408                 return -EINVAL;
 409
 410         /* clock tuning is not needed for upto 52MHz */
 411         if (!((mmc->selected_mode == MMC_HS_200) ||
 412               (mmc->selected_mode == MMC_HS_400) ||
 413               (mmc->selected_mode == UHS_SDR104) ||
 414               (mmc->selected_mode == UHS_SDR50)))
 415                 return 0;
 416
 417         tap_num = renesas_sdhi_init_tuning(priv);
 418         if (!tap_num)
 419                 /* Tuning is not supported */
 420                 goto out;
 421
 422         if (tap_num * 2 >= sizeof(taps) * 8) {
 423                 dev_err(dev,
 424                         "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
 425                 goto out;
 426         }
 427
 428         /* Issue CMD19 twice for each tap */
 429         for (i = 0; i < 2 * tap_num; i++) {
 430                 renesas_sdhi_prepare_tuning(priv, i % tap_num);
 431
 432                 /* Force PIO for the tuning */
 433                 caps = priv->caps;
 434                 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
 435
 436                 ret = mmc_send_tuning(mmc, opcode, NULL);
 437
 438                 priv->caps = caps;
 439
 440                 if (ret == 0)
 441                         taps |= BIT(i);
 442
 443                 ret = renesas_sdhi_compare_scc_data(priv);
 444                 if (ret == 0)
 445                         smpcmp |= BIT(i);
 446
 447                 mdelay(1);
 448         }
 449
 450         ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
 451
 452 out:
 453         if (ret < 0) {
 454                 dev_warn(dev, "Tuning procedure failed\n");
 455                 renesas_sdhi_reset_tuning(priv);
 456         }
 457
 458         return ret;
 459 }
 460 #else
 461 static int renesas_sdhi_hs400(struct udevice *dev)
 462 {
 463         return 0;
 464 }
 465 #endif
 466
 467 static int renesas_sdhi_set_ios(struct udevice *dev)
 468 {
 469         struct tmio_sd_priv *priv = dev_get_priv(dev);
 470         u32 tmp;
 471         int ret;
 472
 473         /* Stop the clock before changing its rate to avoid a glitch signal */
 474         tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
 475         tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
 476         tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
 477
 478         ret = renesas_sdhi_hs400(dev);
 479         if (ret)
 480                 return ret;
 481
 482         ret = tmio_sd_set_ios(dev);
 483
 484         mdelay(10);
 485
 486 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 487     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 488     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 489         struct mmc *mmc = mmc_get_mmc_dev(dev);
 490         if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
 491             (mmc->selected_mode != UHS_SDR104) &&
 492             (mmc->selected_mode != MMC_HS_200) &&
 493             (mmc->selected_mode != MMC_HS_400)) {
 494                 renesas_sdhi_reset_tuning(priv);
 495         }
 496 #endif
 497
 498         return ret;
 499 }
 500
 501 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 502 static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
 503                                   int timeout_us)
 504 {
 505         int ret = -ETIMEDOUT;
 506         bool dat0_high;
 507         bool target_dat0_high = !!state;
 508         struct tmio_sd_priv *priv = dev_get_priv(dev);
 509
 510         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 511         while (timeout_us--) {
 512                 dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
 513                 if (dat0_high == target_dat0_high) {
 514                         ret = 0;
 515                         break;
 516                 }
 517                 udelay(10);
 518         }
 519
 520         return ret;
 521 }
 522 #endif
 523
 524 static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 525                                  struct mmc_data *data)
 526 {
 527         int ret;
 528
 529         ret = tmio_sd_send_cmd(dev, cmd, data);
 530         if (ret)
 531                 return ret;
 532
 533 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 534     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 535     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 536         struct tmio_sd_priv *priv = dev_get_priv(dev);
 537
 538         if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
 539                 renesas_sdhi_adjust_hs400_mode_enable(priv);
 540 #endif
 541
 542         return 0;
 543 }
 544
 545 static const struct dm_mmc_ops renesas_sdhi_ops = {
 546         .send_cmd = renesas_sdhi_send_cmd,
 547         .set_ios = renesas_sdhi_set_ios,
 548         .get_cd = tmio_sd_get_cd,
 549 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 550     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 551     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 552         .execute_tuning = renesas_sdhi_execute_tuning,
 553 #endif
 554 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 555         .wait_dat0 = renesas_sdhi_wait_dat0,
 556 #endif
 557 };
 558
 559 #define RENESAS_GEN2_QUIRKS     TMIO_SD_CAP_RCAR_GEN2
 560 #define RENESAS_GEN3_QUIRKS                             \
 561         TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
 562
 563 static const struct udevice_id renesas_sdhi_match[] = {
 564         { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
 565         { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
 566         { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
 567         { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
 568         { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
 569         { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
 570         { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
 571         { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
 572         { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
 573         { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
 574         { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
 575         { /* sentinel */ }
 576 };
 577
 578 static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
 579 {
 580         return clk_get_rate(&priv->clk);
 581 }
 582
 583 static void renesas_sdhi_filter_caps(struct udevice *dev)
 584 {
 585         struct tmio_sd_plat *plat = dev_get_platdata(dev);
 586         struct tmio_sd_priv *priv = dev_get_priv(dev);
 587
 588         if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
 589                 return;
 590
 591         /* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1,ES1.2 */
 592         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 593             (rmobile_get_cpu_rev_integer() <= 1)) ||
 594             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 595             (rmobile_get_cpu_rev_integer() == 1) &&
 596             (rmobile_get_cpu_rev_fraction() <= 2)))
 597                 plat->cfg.host_caps &= ~MMC_MODE_HS400;
 598
 599         /* M3W ES1.x for x>2 can use HS400 with manual adjustment */
 600         if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 601             (rmobile_get_cpu_rev_integer() == 1) &&
 602             (rmobile_get_cpu_rev_fraction() > 2)) {
 603                 priv->adjust_hs400_enable = true;
 604                 priv->adjust_hs400_offset = 0;
 605                 priv->adjust_hs400_calibrate = 0x9;
 606         }
 607
 608         /* M3N can use HS400 with manual adjustment */
 609         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
 610                 priv->adjust_hs400_enable = true;
 611                 priv->adjust_hs400_offset = 0;
 612                 priv->adjust_hs400_calibrate = 0x0;
 613         }
 614
 615         /* E3 can use HS400 with manual adjustment */
 616         if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
 617                 priv->adjust_hs400_enable = true;
 618                 priv->adjust_hs400_offset = 0;
 619                 priv->adjust_hs400_calibrate = 0x2;
 620         }
 621
 622         /* H3 ES2.0 uses 4 tuning taps */
 623         if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 624             (rmobile_get_cpu_rev_integer() == 2))
 625                 priv->nrtaps = 4;
 626         else
 627                 priv->nrtaps = 8;
 628
 629         /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
 630         if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
 631             (rmobile_get_cpu_rev_integer() <= 1)) ||
 632             ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
 633             (rmobile_get_cpu_rev_integer() == 1) &&
 634             (rmobile_get_cpu_rev_fraction() == 0)))
 635                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
 636         else
 637                 priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
 638 }
 639
 640 static int renesas_sdhi_probe(struct udevice *dev)
 641 {
 642         struct tmio_sd_priv *priv = dev_get_priv(dev);
 643         u32 quirks = dev_get_driver_data(dev);
 644         struct fdt_resource reg_res;
 645         DECLARE_GLOBAL_DATA_PTR;
 646         int ret;
 647
 648         priv->clk_get_rate = renesas_sdhi_clk_get_rate;
 649
 650         if (quirks == RENESAS_GEN2_QUIRKS) {
 651                 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
 652                                        "reg", 0, &reg_res);
 653                 if (ret < 0) {
 654                         dev_err(dev, "\"reg\" resource not found, ret=%i\n",
 655                                 ret);
 656                         return ret;
 657                 }
 658
 659                 if (fdt_resource_size(&reg_res) == 0x100)
 660                         quirks |= TMIO_SD_CAP_16BIT;
 661         }
 662
 663         ret = clk_get_by_index(dev, 0, &priv->clk);
 664         if (ret < 0) {
 665                 dev_err(dev, "failed to get host clock\n");
 666                 return ret;
 667         }
 668
 669         /* set to max rate */
 670         ret = clk_set_rate(&priv->clk, 200000000);
 671         if (ret < 0) {
 672                 dev_err(dev, "failed to set rate for host clock\n");
 673                 clk_free(&priv->clk);
 674                 return ret;
 675         }
 676
 677         ret = clk_enable(&priv->clk);
 678         if (ret) {
 679                 dev_err(dev, "failed to enable host clock\n");
 680                 return ret;
 681         }
 682
 683         ret = tmio_sd_probe(dev, quirks);
 684
 685         renesas_sdhi_filter_caps(dev);
 686
 687 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
 688     CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
 689     CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
 690         if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
 691                 renesas_sdhi_reset_tuning(priv);
 692 #endif
 693         return ret;
 694 }
 695
 696 U_BOOT_DRIVER(renesas_sdhi) = {
 697         .name = "renesas-sdhi",
 698         .id = UCLASS_MMC,
 699         .of_match = renesas_sdhi_match,
 700         .bind = tmio_sd_bind,
 701         .probe = renesas_sdhi_probe,
 702         .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
 703         .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
 704         .ops = &renesas_sdhi_ops,
 705 };