3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
36 #include <asm/arch/mmc_host_def.h>
37 #ifdef CONFIG_OMAP54XX
38 #include <asm/arch/mux_dra7xx.h>
39 #include <asm/arch/dra7xx_iodelay.h>
41 #if !defined(CONFIG_SOC_KEYSTONE)
43 #include <asm/arch/sys_proto.h>
45 #ifdef CONFIG_MMC_OMAP36XX_PINS
46 #include <asm/arch/mux.h>
49 #include <power/regulator.h>
52 DECLARE_GLOBAL_DATA_PTR;
54 /* simplify defines to OMAP_HSMMC_USE_GPIO */
55 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
56 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
57 #define OMAP_HSMMC_USE_GPIO
59 #undef OMAP_HSMMC_USE_GPIO
62 /* common definitions for all OMAPs */
63 #define SYSCTL_SRC (1 << 25)
64 #define SYSCTL_SRD (1 << 26)
66 #ifdef CONFIG_IODELAY_RECALIBRATION
67 struct omap_hsmmc_pinctrl_state {
68 struct pad_conf_entry *padconf;
70 struct iodelay_cfg_entry *iodelay;
75 struct omap_hsmmc_data {
76 struct hsmmc *base_addr;
77 #if !CONFIG_IS_ENABLED(DM_MMC)
78 struct mmc_config cfg;
83 #ifdef OMAP_HSMMC_USE_GPIO
84 #if CONFIG_IS_ENABLED(DM_MMC)
85 struct gpio_desc cd_gpio; /* Change Detect GPIO */
86 struct gpio_desc wp_gpio; /* Write Protect GPIO */
92 #if CONFIG_IS_ENABLED(DM_MMC)
96 #ifdef CONFIG_MMC_OMAP_HS_ADMA
97 struct omap_hsmmc_adma_desc *adma_desc_table;
101 struct udevice *pbias_supply;
103 #ifdef CONFIG_IODELAY_RECALIBRATION
104 struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
105 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
106 struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
107 struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
108 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
109 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
110 struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
111 struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
112 struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
116 struct omap_mmc_of_data {
120 #ifdef CONFIG_MMC_OMAP_HS_ADMA
121 struct omap_hsmmc_adma_desc {
128 #define ADMA_MAX_LEN 63488
130 /* Decriptor table defines */
131 #define ADMA_DESC_ATTR_VALID BIT(0)
132 #define ADMA_DESC_ATTR_END BIT(1)
133 #define ADMA_DESC_ATTR_INT BIT(2)
134 #define ADMA_DESC_ATTR_ACT1 BIT(4)
135 #define ADMA_DESC_ATTR_ACT2 BIT(5)
137 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
138 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
141 /* If we fail after 1 second wait, something is really bad */
142 #define MAX_RETRY_MS 1000
143 #define MMC_TIMEOUT_MS 20
145 /* DMA transfers can take a long time if a lot a data is transferred.
146 * The timeout must take in account the amount of data. Let's assume
147 * that the time will never exceed 333 ms per MB (in other word we assume
148 * that the bandwidth is always above 3MB/s).
150 #define DMA_TIMEOUT_PER_MB 333
151 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
152 #define OMAP_HSMMC_NO_1_8_V BIT(1)
153 #define OMAP_HSMMC_USE_ADMA BIT(2)
154 #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
156 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
157 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
159 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
160 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
161 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
163 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
165 #if CONFIG_IS_ENABLED(DM_MMC)
166 return dev_get_priv(mmc->dev);
168 return (struct omap_hsmmc_data *)mmc->priv;
171 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
173 #if CONFIG_IS_ENABLED(DM_MMC)
174 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
177 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
181 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
182 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
186 #ifndef CONFIG_DM_GPIO
187 if (!gpio_is_valid(gpio))
190 ret = gpio_request(gpio, label);
194 ret = gpio_direction_input(gpio);
202 static unsigned char mmc_board_init(struct mmc *mmc)
204 #if defined(CONFIG_OMAP34XX)
205 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
206 t2_t *t2_base = (t2_t *)T2_BASE;
207 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
209 #ifdef CONFIG_MMC_OMAP36XX_PINS
210 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
213 pbias_lite = readl(&t2_base->pbias_lite);
214 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
215 #ifdef CONFIG_TARGET_OMAP3_CAIRO
216 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
217 pbias_lite &= ~PBIASLITEVMODE0;
219 #ifdef CONFIG_TARGET_OMAP3_LOGIC
220 /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
221 pbias_lite &= ~PBIASLITEVMODE1;
223 #ifdef CONFIG_MMC_OMAP36XX_PINS
224 if (get_cpu_family() == CPU_OMAP36XX) {
225 /* Disable extended drain IO before changing PBIAS */
226 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
227 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
230 writel(pbias_lite, &t2_base->pbias_lite);
232 writel(pbias_lite | PBIASLITEPWRDNZ1 |
233 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
234 &t2_base->pbias_lite);
236 #ifdef CONFIG_MMC_OMAP36XX_PINS
237 if (get_cpu_family() == CPU_OMAP36XX)
238 /* Enable extended drain IO after changing PBIAS */
240 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
241 OMAP34XX_CTRL_WKUP_CTRL);
243 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
246 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
249 /* Change from default of 52MHz to 26MHz if necessary */
250 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
251 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
252 &t2_base->ctl_prog_io1);
254 writel(readl(&prcm_base->fclken1_core) |
255 EN_MMC1 | EN_MMC2 | EN_MMC3,
256 &prcm_base->fclken1_core);
258 writel(readl(&prcm_base->iclken1_core) |
259 EN_MMC1 | EN_MMC2 | EN_MMC3,
260 &prcm_base->iclken1_core);
263 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
264 !CONFIG_IS_ENABLED(DM_REGULATOR)
265 /* PBIAS config needed for MMC1 only */
266 if (mmc_get_blk_desc(mmc)->devnum == 0)
267 vmmc_pbias_config(LDO_VOLT_3V3);
273 void mmc_init_stream(struct hsmmc *mmc_base)
277 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
279 writel(MMC_CMD0, &mmc_base->cmd);
280 start = get_timer(0);
281 while (!(readl(&mmc_base->stat) & CC_MASK)) {
282 if (get_timer(0) - start > MAX_RETRY_MS) {
283 printf("%s: timedout waiting for cc!\n", __func__);
287 writel(CC_MASK, &mmc_base->stat)
289 writel(MMC_CMD0, &mmc_base->cmd)
291 start = get_timer(0);
292 while (!(readl(&mmc_base->stat) & CC_MASK)) {
293 if (get_timer(0) - start > MAX_RETRY_MS) {
294 printf("%s: timedout waiting for cc2!\n", __func__);
298 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
301 #if CONFIG_IS_ENABLED(DM_MMC)
302 #ifdef CONFIG_IODELAY_RECALIBRATION
303 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
305 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
306 struct omap_hsmmc_pinctrl_state *pinctrl_state;
308 switch (priv->mode) {
310 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
313 pinctrl_state = priv->sdr104_pinctrl_state;
316 pinctrl_state = priv->sdr50_pinctrl_state;
319 pinctrl_state = priv->ddr50_pinctrl_state;
322 pinctrl_state = priv->sdr25_pinctrl_state;
325 pinctrl_state = priv->sdr12_pinctrl_state;
330 pinctrl_state = priv->hs_pinctrl_state;
333 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
335 pinctrl_state = priv->default_pinctrl_state;
340 pinctrl_state = priv->default_pinctrl_state;
342 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
343 if (pinctrl_state->iodelay)
344 late_recalibrate_iodelay(pinctrl_state->padconf,
345 pinctrl_state->npads,
346 pinctrl_state->iodelay,
347 pinctrl_state->niodelays);
349 do_set_mux32((*ctrl)->control_padconf_core_base,
350 pinctrl_state->padconf,
351 pinctrl_state->npads);
355 static void omap_hsmmc_set_timing(struct mmc *mmc)
358 struct hsmmc *mmc_base;
359 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
361 mmc_base = priv->base_addr;
363 omap_hsmmc_stop_clock(mmc_base);
364 val = readl(&mmc_base->ac12);
365 val &= ~AC12_UHSMC_MASK;
366 priv->mode = mmc->selected_mode;
368 if (mmc_is_mode_ddr(priv->mode))
369 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
371 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
373 switch (priv->mode) {
376 val |= AC12_UHSMC_SDR104;
379 val |= AC12_UHSMC_SDR50;
383 val |= AC12_UHSMC_DDR50;
388 val |= AC12_UHSMC_SDR25;
394 val |= AC12_UHSMC_SDR12;
397 val |= AC12_UHSMC_RES;
400 writel(val, &mmc_base->ac12);
402 #ifdef CONFIG_IODELAY_RECALIBRATION
403 omap_hsmmc_io_recalibrate(mmc);
405 omap_hsmmc_start_clock(mmc_base);
408 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
410 struct hsmmc *mmc_base;
411 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
414 mmc_base = priv->base_addr;
416 hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
417 ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
419 switch (signal_voltage) {
420 case MMC_SIGNAL_VOLTAGE_330:
423 case MMC_SIGNAL_VOLTAGE_180:
425 ac12 |= AC12_V1V8_SIGEN;
429 writel(hctl, &mmc_base->hctl);
430 writel(ac12, &mmc_base->ac12);
433 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
434 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout)
436 int ret = -ETIMEDOUT;
439 bool target_dat0_high = !!state;
440 struct omap_hsmmc_data *priv = dev_get_priv(dev);
441 struct hsmmc *mmc_base = priv->base_addr;
443 con = readl(&mmc_base->con);
444 writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
446 timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
448 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
449 if (dat0_high == target_dat0_high) {
455 writel(con, &mmc_base->con);
461 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
462 #if CONFIG_IS_ENABLED(DM_REGULATOR)
463 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
468 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
470 if (!mmc->vqmmc_supply)
474 ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
478 /* Turn off IO voltage */
479 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
482 /* Program a new IO voltage value */
483 ret = regulator_set_value(mmc->vqmmc_supply, uV);
486 /* Turn on IO voltage */
487 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
491 /* Program PBIAS voltage*/
492 ret = regulator_set_value(priv->pbias_supply, uV);
493 if (ret && ret != -ENOSYS)
496 ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
504 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
506 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
507 struct hsmmc *mmc_base = priv->base_addr;
508 int mv = mmc_voltage_to_mv(mmc->signal_voltage);
510 __maybe_unused u8 palmas_ldo_volt;
516 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
518 capa_mask = VS33_3V3SUP;
519 palmas_ldo_volt = LDO_VOLT_3V3;
520 } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
521 capa_mask = VS18_1V8SUP;
522 palmas_ldo_volt = LDO_VOLT_1V8;
527 val = readl(&mmc_base->capa);
528 if (!(val & capa_mask))
531 priv->signal_voltage = mmc->signal_voltage;
533 omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
535 #if CONFIG_IS_ENABLED(DM_REGULATOR)
536 return omap_hsmmc_set_io_regulator(mmc, mv);
537 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
538 defined(CONFIG_PALMAS_POWER)
539 if (mmc_get_blk_desc(mmc)->devnum == 0)
540 vmmc_pbias_config(palmas_ldo_volt);
548 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
550 struct hsmmc *mmc_base;
551 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
554 mmc_base = priv->base_addr;
555 val = readl(&mmc_base->capa);
557 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
558 val |= (VS33_3V3SUP | VS18_1V8SUP);
559 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
567 writel(val, &mmc_base->capa);
572 #ifdef MMC_SUPPORTS_TUNING
573 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
575 struct hsmmc *mmc_base;
576 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
579 mmc_base = priv->base_addr;
580 val = readl(&mmc_base->ac12);
581 val &= ~(AC12_SCLK_SEL);
582 writel(val, &mmc_base->ac12);
584 val = readl(&mmc_base->dll);
585 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
586 writel(val, &mmc_base->dll);
589 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
592 struct hsmmc *mmc_base;
593 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
596 mmc_base = priv->base_addr;
597 val = readl(&mmc_base->dll);
598 val |= DLL_FORCE_VALUE;
599 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
600 val |= (count << DLL_FORCE_SR_C_SHIFT);
601 writel(val, &mmc_base->dll);
604 writel(val, &mmc_base->dll);
605 for (i = 0; i < 1000; i++) {
606 if (readl(&mmc_base->dll) & DLL_CALIB)
610 writel(val, &mmc_base->dll);
613 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
615 struct omap_hsmmc_data *priv = dev_get_priv(dev);
616 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
617 struct mmc *mmc = upriv->mmc;
618 struct hsmmc *mmc_base;
620 u8 cur_match, prev_match = 0;
623 u32 start_window = 0, max_window = 0;
624 u32 length = 0, max_len = 0;
625 bool single_point_failure = false;
626 struct udevice *thermal_dev;
630 mmc_base = priv->base_addr;
631 val = readl(&mmc_base->capa2);
633 /* clock tuning is not needed for upto 52MHz */
634 if (!((mmc->selected_mode == MMC_HS_200) ||
635 (mmc->selected_mode == UHS_SDR104) ||
636 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
639 ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
641 printf("Couldn't get thermal device for tuning\n");
644 ret = thermal_get_temp(thermal_dev, &temperature);
646 printf("Couldn't get temperature for tuning\n");
649 val = readl(&mmc_base->dll);
651 writel(val, &mmc_base->dll);
654 * Stage 1: Search for a maximum pass window ignoring any
655 * any single point failures. If the tuning value ends up
656 * near it, move away from it in stage 2 below
658 while (phase_delay <= MAX_PHASE_DELAY) {
659 omap_hsmmc_set_dll(mmc, phase_delay);
661 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
666 } else if (single_point_failure) {
667 /* ignore single point failure */
669 single_point_failure = false;
671 start_window = phase_delay;
675 single_point_failure = prev_match;
678 if (length > max_len) {
679 max_window = start_window;
683 prev_match = cur_match;
692 val = readl(&mmc_base->ac12);
693 if (!(val & AC12_SCLK_SEL)) {
698 * Assign tuning value as a ratio of maximum pass window based
701 if (temperature < -20000)
702 phase_delay = min(max_window + 4 * max_len - 24,
704 DIV_ROUND_UP(13 * max_len, 16) * 4);
705 else if (temperature < 20000)
706 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
707 else if (temperature < 40000)
708 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
709 else if (temperature < 70000)
710 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
711 else if (temperature < 90000)
712 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
713 else if (temperature < 120000)
714 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
716 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
719 * Stage 2: Search for a single point failure near the chosen tuning
720 * value in two steps. First in the +3 to +10 range and then in the
721 * +2 to -10 range. If found, move away from it in the appropriate
722 * direction by the appropriate amount depending on the temperature.
724 for (i = 3; i <= 10; i++) {
725 omap_hsmmc_set_dll(mmc, phase_delay + i);
726 if (mmc_send_tuning(mmc, opcode, NULL)) {
727 if (temperature < 10000)
728 phase_delay += i + 6;
729 else if (temperature < 20000)
730 phase_delay += i - 12;
731 else if (temperature < 70000)
732 phase_delay += i - 8;
733 else if (temperature < 90000)
734 phase_delay += i - 6;
736 phase_delay += i - 6;
738 goto single_failure_found;
742 for (i = 2; i >= -10; i--) {
743 omap_hsmmc_set_dll(mmc, phase_delay + i);
744 if (mmc_send_tuning(mmc, opcode, NULL)) {
745 if (temperature < 10000)
746 phase_delay += i + 12;
747 else if (temperature < 20000)
748 phase_delay += i + 8;
749 else if (temperature < 70000)
750 phase_delay += i + 8;
751 else if (temperature < 90000)
752 phase_delay += i + 10;
754 phase_delay += i + 12;
756 goto single_failure_found;
760 single_failure_found:
762 omap_hsmmc_set_dll(mmc, phase_delay);
764 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
765 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
771 omap_hsmmc_disable_tuning(mmc);
772 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
773 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
779 static void omap_hsmmc_send_init_stream(struct udevice *dev)
781 struct omap_hsmmc_data *priv = dev_get_priv(dev);
782 struct hsmmc *mmc_base = priv->base_addr;
784 mmc_init_stream(mmc_base);
788 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
790 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
791 struct hsmmc *mmc_base = priv->base_addr;
792 u32 irq_mask = INT_EN_MASK;
795 * TODO: Errata i802 indicates only DCRC interrupts can occur during
796 * tuning procedure and DCRC should be disabled. But see occurences
797 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
798 * interrupts occur along with BRR, so the data is actually in the
799 * buffer. It has to be debugged why these interrutps occur
801 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
802 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
804 writel(irq_mask, &mmc_base->ie);
807 static int omap_hsmmc_init_setup(struct mmc *mmc)
809 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
810 struct hsmmc *mmc_base;
811 unsigned int reg_val;
815 mmc_base = priv->base_addr;
818 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
819 &mmc_base->sysconfig);
820 start = get_timer(0);
821 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
822 if (get_timer(0) - start > MAX_RETRY_MS) {
823 printf("%s: timedout waiting for cc2!\n", __func__);
827 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
828 start = get_timer(0);
829 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
830 if (get_timer(0) - start > MAX_RETRY_MS) {
831 printf("%s: timedout waiting for softresetall!\n",
836 #ifdef CONFIG_MMC_OMAP_HS_ADMA
837 reg_val = readl(&mmc_base->hl_hwinfo);
838 if (reg_val & MADMA_EN)
839 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
842 #if CONFIG_IS_ENABLED(DM_MMC)
843 reg_val = omap_hsmmc_set_capabilities(mmc);
844 omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
845 MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
847 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
848 writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
852 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
854 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
855 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
856 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
859 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
860 (ICE_STOP | DTO_15THDTO));
861 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
862 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
863 start = get_timer(0);
864 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
865 if (get_timer(0) - start > MAX_RETRY_MS) {
866 printf("%s: timedout waiting for ics!\n", __func__);
870 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
872 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
874 mmc_enable_irq(mmc, NULL);
876 #if !CONFIG_IS_ENABLED(DM_MMC)
877 mmc_init_stream(mmc_base);
884 * MMC controller internal finite state machine reset
886 * Used to reset command or data internal state machines, using respectively
887 * SRC or SRD bit of SYSCTL register
889 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
893 mmc_reg_out(&mmc_base->sysctl, bit, bit);
896 * CMD(DAT) lines reset procedures are slightly different
897 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
898 * According to OMAP3 TRM:
899 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
901 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
902 * procedure steps must be as follows:
903 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
904 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
905 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
906 * 3. Wait until the SRC (SRD) bit returns to 0x0
907 * (reset procedure is completed).
909 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
910 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
911 if (!(readl(&mmc_base->sysctl) & bit)) {
912 start = get_timer(0);
913 while (!(readl(&mmc_base->sysctl) & bit)) {
914 if (get_timer(0) - start > MMC_TIMEOUT_MS)
919 start = get_timer(0);
920 while ((readl(&mmc_base->sysctl) & bit) != 0) {
921 if (get_timer(0) - start > MAX_RETRY_MS) {
922 printf("%s: timedout waiting for sysctl %x to clear\n",
929 #ifdef CONFIG_MMC_OMAP_HS_ADMA
930 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
932 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
933 struct omap_hsmmc_adma_desc *desc;
936 desc = &priv->adma_desc_table[priv->desc_slot];
938 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
942 attr |= ADMA_DESC_ATTR_END;
945 desc->addr = (u32)buf;
950 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
951 struct mmc_data *data)
953 uint total_len = data->blocksize * data->blocks;
954 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
955 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
960 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
961 memalign(ARCH_DMA_MINALIGN, desc_count *
962 sizeof(struct omap_hsmmc_adma_desc));
964 if (data->flags & MMC_DATA_READ)
967 buf = (char *)data->src;
970 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
972 total_len -= ADMA_MAX_LEN;
975 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
977 flush_dcache_range((long)priv->adma_desc_table,
978 (long)priv->adma_desc_table +
980 sizeof(struct omap_hsmmc_adma_desc),
984 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
986 struct hsmmc *mmc_base;
987 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
991 mmc_base = priv->base_addr;
992 omap_hsmmc_prepare_adma_table(mmc, data);
994 if (data->flags & MMC_DATA_READ)
997 buf = (char *)data->src;
999 val = readl(&mmc_base->hctl);
1001 writel(val, &mmc_base->hctl);
1003 val = readl(&mmc_base->con);
1005 writel(val, &mmc_base->con);
1007 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1009 flush_dcache_range((u32)buf,
1011 ROUND(data->blocksize * data->blocks,
1012 ARCH_DMA_MINALIGN));
1015 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1017 struct hsmmc *mmc_base;
1018 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1021 mmc_base = priv->base_addr;
1023 val = readl(&mmc_base->con);
1025 writel(val, &mmc_base->con);
1027 val = readl(&mmc_base->hctl);
1029 writel(val, &mmc_base->hctl);
1031 kfree(priv->adma_desc_table);
1034 #define omap_hsmmc_adma_desc
1035 #define omap_hsmmc_prepare_adma_table
1036 #define omap_hsmmc_prepare_data
1037 #define omap_hsmmc_dma_cleanup
1040 #if !CONFIG_IS_ENABLED(DM_MMC)
1041 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1042 struct mmc_data *data)
1044 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1046 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1047 struct mmc_data *data)
1049 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1050 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1051 struct mmc *mmc = upriv->mmc;
1053 struct hsmmc *mmc_base;
1054 unsigned int flags, mmc_stat;
1056 priv->last_cmd = cmd->cmdidx;
1058 mmc_base = priv->base_addr;
1060 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1063 start = get_timer(0);
1064 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1065 if (get_timer(0) - start > MAX_RETRY_MS) {
1066 printf("%s: timedout waiting on cmd inhibit to clear\n",
1068 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1069 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1073 writel(0xFFFFFFFF, &mmc_base->stat);
1074 if (readl(&mmc_base->stat)) {
1075 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1076 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1081 * CMDIDX[13:8] : Command index
1082 * DATAPRNT[5] : Data Present Select
1083 * ENCMDIDX[4] : Command Index Check Enable
1084 * ENCMDCRC[3] : Command CRC Check Enable
1089 * 11 = Length 48 Check busy after response
1091 /* Delay added before checking the status of frq change
1092 * retry not supported by mmc.c(core file)
1094 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1095 udelay(50000); /* wait 50 ms */
1097 if (!(cmd->resp_type & MMC_RSP_PRESENT))
1099 else if (cmd->resp_type & MMC_RSP_136)
1100 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1101 else if (cmd->resp_type & MMC_RSP_BUSY)
1102 flags = RSP_TYPE_LGHT48B;
1104 flags = RSP_TYPE_LGHT48;
1106 /* enable default flags */
1107 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1109 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1111 if (cmd->resp_type & MMC_RSP_CRC)
1112 flags |= CCCE_CHECK;
1113 if (cmd->resp_type & MMC_RSP_OPCODE)
1114 flags |= CICE_CHECK;
1117 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1118 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1119 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1120 data->blocksize = 512;
1121 writel(data->blocksize | (data->blocks << 16),
1124 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1126 if (data->flags & MMC_DATA_READ)
1127 flags |= (DP_DATA | DDIR_READ);
1129 flags |= (DP_DATA | DDIR_WRITE);
1131 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1132 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1133 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1134 omap_hsmmc_prepare_data(mmc, data);
1140 mmc_enable_irq(mmc, cmd);
1142 writel(cmd->cmdarg, &mmc_base->arg);
1143 udelay(20); /* To fix "No status update" error on eMMC */
1144 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1146 start = get_timer(0);
1148 mmc_stat = readl(&mmc_base->stat);
1149 if (get_timer(start) > MAX_RETRY_MS) {
1150 printf("%s : timeout: No status update\n", __func__);
1153 } while (!mmc_stat);
1155 if ((mmc_stat & IE_CTO) != 0) {
1156 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1158 } else if ((mmc_stat & ERRI_MASK) != 0)
1161 if (mmc_stat & CC_MASK) {
1162 writel(CC_MASK, &mmc_base->stat);
1163 if (cmd->resp_type & MMC_RSP_PRESENT) {
1164 if (cmd->resp_type & MMC_RSP_136) {
1165 /* response type 2 */
1166 cmd->response[3] = readl(&mmc_base->rsp10);
1167 cmd->response[2] = readl(&mmc_base->rsp32);
1168 cmd->response[1] = readl(&mmc_base->rsp54);
1169 cmd->response[0] = readl(&mmc_base->rsp76);
1171 /* response types 1, 1b, 3, 4, 5, 6 */
1172 cmd->response[0] = readl(&mmc_base->rsp10);
1176 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1177 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1178 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1181 if (mmc_stat & IE_ADMAE) {
1182 omap_hsmmc_dma_cleanup(mmc);
1186 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
1187 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1188 if (timeout < MAX_RETRY_MS)
1189 timeout = MAX_RETRY_MS;
1191 start = get_timer(0);
1193 mmc_stat = readl(&mmc_base->stat);
1194 if (mmc_stat & TC_MASK) {
1195 writel(readl(&mmc_base->stat) | TC_MASK,
1199 if (get_timer(start) > timeout) {
1200 printf("%s : DMA timeout: No status update\n",
1206 omap_hsmmc_dma_cleanup(mmc);
1211 if (data && (data->flags & MMC_DATA_READ)) {
1212 mmc_read_data(mmc_base, data->dest,
1213 data->blocksize * data->blocks);
1214 } else if (data && (data->flags & MMC_DATA_WRITE)) {
1215 mmc_write_data(mmc_base, data->src,
1216 data->blocksize * data->blocks);
1221 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1223 unsigned int *output_buf = (unsigned int *)buf;
1224 unsigned int mmc_stat;
1230 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1234 ulong start = get_timer(0);
1236 mmc_stat = readl(&mmc_base->stat);
1237 if (get_timer(0) - start > MAX_RETRY_MS) {
1238 printf("%s: timedout waiting for status!\n",
1242 } while (mmc_stat == 0);
1244 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1245 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1247 if ((mmc_stat & ERRI_MASK) != 0)
1250 if (mmc_stat & BRR_MASK) {
1253 writel(readl(&mmc_base->stat) | BRR_MASK,
1255 for (k = 0; k < count; k++) {
1256 *output_buf = readl(&mmc_base->data);
1262 if (mmc_stat & BWR_MASK)
1263 writel(readl(&mmc_base->stat) | BWR_MASK,
1266 if (mmc_stat & TC_MASK) {
1267 writel(readl(&mmc_base->stat) | TC_MASK,
1275 #if CONFIG_IS_ENABLED(MMC_WRITE)
1276 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1279 unsigned int *input_buf = (unsigned int *)buf;
1280 unsigned int mmc_stat;
1284 * Start Polled Write
1286 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1290 ulong start = get_timer(0);
1292 mmc_stat = readl(&mmc_base->stat);
1293 if (get_timer(0) - start > MAX_RETRY_MS) {
1294 printf("%s: timedout waiting for status!\n",
1298 } while (mmc_stat == 0);
1300 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1301 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1303 if ((mmc_stat & ERRI_MASK) != 0)
1306 if (mmc_stat & BWR_MASK) {
1309 writel(readl(&mmc_base->stat) | BWR_MASK,
1311 for (k = 0; k < count; k++) {
1312 writel(*input_buf, &mmc_base->data);
1318 if (mmc_stat & BRR_MASK)
1319 writel(readl(&mmc_base->stat) | BRR_MASK,
1322 if (mmc_stat & TC_MASK) {
1323 writel(readl(&mmc_base->stat) | TC_MASK,
1331 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1337 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1339 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1342 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1344 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1347 static void omap_hsmmc_set_clock(struct mmc *mmc)
1349 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1350 struct hsmmc *mmc_base;
1351 unsigned int dsor = 0;
1354 mmc_base = priv->base_addr;
1355 omap_hsmmc_stop_clock(mmc_base);
1357 /* TODO: Is setting DTO required here? */
1358 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1359 (ICE_STOP | DTO_15THDTO));
1361 if (mmc->clock != 0) {
1362 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1363 if (dsor > CLKD_MAX)
1369 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1370 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1372 start = get_timer(0);
1373 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1374 if (get_timer(0) - start > MAX_RETRY_MS) {
1375 printf("%s: timedout waiting for ics!\n", __func__);
1380 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1381 mmc->clock = priv->clock;
1382 omap_hsmmc_start_clock(mmc_base);
1385 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1387 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1388 struct hsmmc *mmc_base;
1390 mmc_base = priv->base_addr;
1391 /* configue bus width */
1392 switch (mmc->bus_width) {
1394 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1399 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1401 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1407 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1409 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1414 priv->bus_width = mmc->bus_width;
1417 #if !CONFIG_IS_ENABLED(DM_MMC)
1418 static int omap_hsmmc_set_ios(struct mmc *mmc)
1420 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1422 static int omap_hsmmc_set_ios(struct udevice *dev)
1424 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1425 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1426 struct mmc *mmc = upriv->mmc;
1428 struct hsmmc *mmc_base = priv->base_addr;
1431 if (priv->bus_width != mmc->bus_width)
1432 omap_hsmmc_set_bus_width(mmc);
1434 if (priv->clock != mmc->clock)
1435 omap_hsmmc_set_clock(mmc);
1437 if (mmc->clk_disable)
1438 omap_hsmmc_stop_clock(mmc_base);
1440 omap_hsmmc_start_clock(mmc_base);
1442 #if CONFIG_IS_ENABLED(DM_MMC)
1443 if (priv->mode != mmc->selected_mode)
1444 omap_hsmmc_set_timing(mmc);
1446 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1447 if (priv->signal_voltage != mmc->signal_voltage)
1448 ret = omap_hsmmc_set_signal_voltage(mmc);
1454 #ifdef OMAP_HSMMC_USE_GPIO
1455 #if CONFIG_IS_ENABLED(DM_MMC)
1456 static int omap_hsmmc_getcd(struct udevice *dev)
1459 #if CONFIG_IS_ENABLED(DM_GPIO)
1460 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1461 value = dm_gpio_get_value(&priv->cd_gpio);
1463 /* if no CD return as 1 */
1470 static int omap_hsmmc_getwp(struct udevice *dev)
1473 #if CONFIG_IS_ENABLED(DM_GPIO)
1474 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1475 value = dm_gpio_get_value(&priv->wp_gpio);
1477 /* if no WP return as 0 */
1483 static int omap_hsmmc_getcd(struct mmc *mmc)
1485 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1488 /* if no CD return as 1 */
1489 cd_gpio = priv->cd_gpio;
1493 /* NOTE: assumes card detect signal is active-low */
1494 return !gpio_get_value(cd_gpio);
1497 static int omap_hsmmc_getwp(struct mmc *mmc)
1499 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1502 /* if no WP return as 0 */
1503 wp_gpio = priv->wp_gpio;
1507 /* NOTE: assumes write protect signal is active-high */
1508 return gpio_get_value(wp_gpio);
1513 #if CONFIG_IS_ENABLED(DM_MMC)
1514 static const struct dm_mmc_ops omap_hsmmc_ops = {
1515 .send_cmd = omap_hsmmc_send_cmd,
1516 .set_ios = omap_hsmmc_set_ios,
1517 #ifdef OMAP_HSMMC_USE_GPIO
1518 .get_cd = omap_hsmmc_getcd,
1519 .get_wp = omap_hsmmc_getwp,
1521 #ifdef MMC_SUPPORTS_TUNING
1522 .execute_tuning = omap_hsmmc_execute_tuning,
1524 .send_init_stream = omap_hsmmc_send_init_stream,
1525 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1526 .wait_dat0 = omap_hsmmc_wait_dat0,
1530 static const struct mmc_ops omap_hsmmc_ops = {
1531 .send_cmd = omap_hsmmc_send_cmd,
1532 .set_ios = omap_hsmmc_set_ios,
1533 .init = omap_hsmmc_init_setup,
1534 #ifdef OMAP_HSMMC_USE_GPIO
1535 .getcd = omap_hsmmc_getcd,
1536 .getwp = omap_hsmmc_getwp,
1541 #if !CONFIG_IS_ENABLED(DM_MMC)
1542 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1546 struct omap_hsmmc_data *priv;
1547 struct mmc_config *cfg;
1550 priv = calloc(1, sizeof(*priv));
1554 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1556 switch (dev_index) {
1558 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1560 #ifdef OMAP_HSMMC2_BASE
1562 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1563 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1564 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1565 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1566 defined(CONFIG_HSMMC2_8BIT)
1567 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1568 host_caps_val |= MMC_MODE_8BIT;
1572 #ifdef OMAP_HSMMC3_BASE
1574 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1575 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1576 /* Enable 8-bit interface for eMMC on DRA7XX */
1577 host_caps_val |= MMC_MODE_8BIT;
1582 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1585 #ifdef OMAP_HSMMC_USE_GPIO
1586 /* on error gpio values are set to -1, which is what we want */
1587 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1588 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1593 cfg->name = "OMAP SD/MMC";
1594 cfg->ops = &omap_hsmmc_ops;
1596 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1597 cfg->host_caps = host_caps_val & ~host_caps_mask;
1599 cfg->f_min = 400000;
1604 if (cfg->host_caps & MMC_MODE_HS) {
1605 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1606 cfg->f_max = 52000000;
1608 cfg->f_max = 26000000;
1610 cfg->f_max = 20000000;
1613 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1615 #if defined(CONFIG_OMAP34XX)
1617 * Silicon revs 2.1 and older do not support multiblock transfers.
1619 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1623 mmc = mmc_create(cfg, priv);
1631 #ifdef CONFIG_IODELAY_RECALIBRATION
1632 static struct pad_conf_entry *
1633 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1636 struct pad_conf_entry *padconf;
1638 padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1640 debug("failed to allocate memory\n");
1644 while (index < count) {
1645 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1646 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1653 static struct iodelay_cfg_entry *
1654 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1657 struct iodelay_cfg_entry *iodelay;
1659 iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1661 debug("failed to allocate memory\n");
1665 while (index < count) {
1666 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1667 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1668 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1675 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
1676 const char *name, int *len)
1678 const void *fdt = gd->fdt_blob;
1680 const fdt32_t *pinctrl;
1682 offset = fdt_node_offset_by_phandle(fdt, phandle);
1684 debug("failed to get pinctrl node %s.\n",
1685 fdt_strerror(offset));
1689 pinctrl = fdt_getprop(fdt, offset, name, len);
1691 debug("failed to get property %s\n", name);
1698 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1701 const void *fdt = gd->fdt_blob;
1702 const __be32 *phandle;
1703 int node = dev_of_offset(mmc->dev);
1705 phandle = fdt_getprop(fdt, node, prop_name, NULL);
1707 debug("failed to get property %s\n", prop_name);
1711 return fdt32_to_cpu(*phandle);
1714 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1717 const void *fdt = gd->fdt_blob;
1718 const __be32 *phandle;
1721 int node = dev_of_offset(mmc->dev);
1723 phandle = fdt_getprop(fdt, node, prop_name, &len);
1725 debug("failed to get property %s\n", prop_name);
1729 /* No manual mode iodelay values if count < 2 */
1730 count = len / sizeof(*phandle);
1734 return fdt32_to_cpu(*(phandle + 1));
1737 static struct pad_conf_entry *
1738 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1742 struct pad_conf_entry *padconf;
1744 const fdt32_t *pinctrl;
1746 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1748 return ERR_PTR(-EINVAL);
1750 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1753 return ERR_PTR(-EINVAL);
1755 count = (len / sizeof(*pinctrl)) / 2;
1756 padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1758 return ERR_PTR(-EINVAL);
1765 static struct iodelay_cfg_entry *
1766 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1770 struct iodelay_cfg_entry *iodelay;
1772 const fdt32_t *pinctrl;
1774 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1775 /* Not all modes have manual mode iodelay values. So its not fatal */
1779 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1782 return ERR_PTR(-EINVAL);
1784 count = (len / sizeof(*pinctrl)) / 3;
1785 iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1787 return ERR_PTR(-EINVAL);
1794 static struct omap_hsmmc_pinctrl_state *
1795 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1800 const void *fdt = gd->fdt_blob;
1801 int node = dev_of_offset(mmc->dev);
1803 struct omap_hsmmc_pinctrl_state *pinctrl_state;
1805 pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1806 malloc(sizeof(*pinctrl_state));
1807 if (!pinctrl_state) {
1808 debug("failed to allocate memory\n");
1812 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1814 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1815 goto err_pinctrl_state;
1818 sprintf(prop_name, "pinctrl-%d", index);
1820 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1822 if (IS_ERR(pinctrl_state->padconf))
1823 goto err_pinctrl_state;
1824 pinctrl_state->npads = npads;
1826 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1828 if (IS_ERR(pinctrl_state->iodelay))
1830 pinctrl_state->niodelays = niodelays;
1832 return pinctrl_state;
1835 kfree(pinctrl_state->padconf);
1838 kfree(pinctrl_state);
1842 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
1844 struct omap_hsmmc_pinctrl_state *s = NULL; \
1846 if (!(cfg->host_caps & capmask)) \
1849 if (priv->hw_rev) { \
1850 sprintf(str, "%s-%s", #mode, priv->hw_rev); \
1851 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
1855 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1857 if (!s && !optional) { \
1858 debug("%s: no pinctrl for %s\n", \
1859 mmc->dev->name, #mode); \
1860 cfg->host_caps &= ~(capmask); \
1862 priv->mode##_pinctrl_state = s; \
1866 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1868 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1869 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1870 struct omap_hsmmc_pinctrl_state *default_pinctrl;
1872 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1875 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1876 if (!default_pinctrl) {
1877 printf("no pinctrl state for default mode\n");
1881 priv->default_pinctrl_state = default_pinctrl;
1883 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1884 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1885 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1886 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1887 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1889 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1890 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1891 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1897 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1898 #ifdef CONFIG_OMAP54XX
1899 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1905 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1907 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1908 struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1910 struct mmc_config *cfg = &plat->cfg;
1911 #ifdef CONFIG_OMAP54XX
1912 const struct mmc_platform_fixups *fixups;
1914 const void *fdt = gd->fdt_blob;
1915 int node = dev_of_offset(dev);
1918 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1919 sizeof(struct hsmmc *),
1922 ret = mmc_of_parse(dev, cfg);
1927 cfg->f_max = 52000000;
1928 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1929 cfg->f_min = 400000;
1930 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1931 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1932 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1933 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1934 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1935 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1937 plat->controller_flags |= of_data->controller_flags;
1939 #ifdef CONFIG_OMAP54XX
1940 fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1942 plat->hw_rev = fixups->hw_rev;
1943 cfg->host_caps &= ~fixups->unsupported_caps;
1944 cfg->f_max = fixups->max_freq;
1954 static int omap_hsmmc_bind(struct udevice *dev)
1956 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1957 plat->mmc = calloc(1, sizeof(struct mmc));
1958 return mmc_bind(dev, plat->mmc, &plat->cfg);
1961 static int omap_hsmmc_probe(struct udevice *dev)
1963 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1964 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1965 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1966 struct mmc_config *cfg = &plat->cfg;
1968 #ifdef CONFIG_IODELAY_RECALIBRATION
1972 cfg->name = "OMAP SD/MMC";
1973 priv->base_addr = plat->base_addr;
1974 priv->controller_flags = plat->controller_flags;
1975 priv->hw_rev = plat->hw_rev;
1980 mmc = mmc_create(cfg, priv);
1984 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1985 device_get_supply_regulator(dev, "pbias-supply",
1986 &priv->pbias_supply);
1988 #if defined(OMAP_HSMMC_USE_GPIO)
1989 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1990 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1991 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1998 #ifdef CONFIG_IODELAY_RECALIBRATION
1999 ret = omap_hsmmc_get_pinctrl_state(mmc);
2001 * disable high speed modes for the platforms that require IO delay
2002 * and for which we don't have this information
2005 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
2006 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
2007 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2012 return omap_hsmmc_init_setup(mmc);
2015 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2017 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2018 .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2021 static const struct udevice_id omap_hsmmc_ids[] = {
2022 { .compatible = "ti,omap3-hsmmc" },
2023 { .compatible = "ti,omap4-hsmmc" },
2024 { .compatible = "ti,am33xx-hsmmc" },
2025 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2030 U_BOOT_DRIVER(omap_hsmmc) = {
2031 .name = "omap_hsmmc",
2033 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2034 .of_match = omap_hsmmc_ids,
2035 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2036 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2039 .bind = omap_hsmmc_bind,
2041 .ops = &omap_hsmmc_ops,
2042 .probe = omap_hsmmc_probe,
2043 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2044 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2045 .flags = DM_FLAG_PRE_RELOC,