drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <memalign.h>
  29 #include <mmc.h>
  30 #include <part.h>
  31 #include <i2c.h>
  32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  33 #include <palmas.h>
  34 #endif
  35 #include <asm/io.h>
  36 #include <asm/arch/mmc_host_def.h>
  37 #ifdef CONFIG_OMAP54XX
  38 #include <asm/arch/mux_dra7xx.h>
  39 #include <asm/arch/dra7xx_iodelay.h>
  40 #endif
  41 #if !defined(CONFIG_SOC_KEYSTONE)
  42 #include <asm/gpio.h>
  43 #include <asm/arch/sys_proto.h>
  44 #endif
  45 #ifdef CONFIG_MMC_OMAP36XX_PINS
  46 #include <asm/arch/mux.h>
  47 #endif
  48 #include <dm.h>
  49 #include <power/regulator.h>
  50 #include <thermal.h>
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  55 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  56         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  57 #define OMAP_HSMMC_USE_GPIO
  58 #else
  59 #undef OMAP_HSMMC_USE_GPIO
  60 #endif
  61
  62 /* common definitions for all OMAPs */
  63 #define SYSCTL_SRC      (1 << 25)
  64 #define SYSCTL_SRD      (1 << 26)
  65
  66 #ifdef CONFIG_IODELAY_RECALIBRATION
  67 struct omap_hsmmc_pinctrl_state {
  68         struct pad_conf_entry *padconf;
  69         int npads;
  70         struct iodelay_cfg_entry *iodelay;
  71         int niodelays;
  72 };
  73 #endif
  74
  75 struct omap_hsmmc_data {
  76         struct hsmmc *base_addr;
  77 #if !CONFIG_IS_ENABLED(DM_MMC)
  78         struct mmc_config cfg;
  79 #endif
  80         uint bus_width;
  81         uint clock;
  82         ushort last_cmd;
  83 #ifdef OMAP_HSMMC_USE_GPIO
  84 #if CONFIG_IS_ENABLED(DM_MMC)
  85         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  86         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  87 #else
  88         int cd_gpio;
  89         int wp_gpio;
  90 #endif
  91 #endif
  92 #if CONFIG_IS_ENABLED(DM_MMC)
  93         enum bus_mode mode;
  94 #endif
  95         u8 controller_flags;
  96 #ifdef CONFIG_MMC_OMAP_HS_ADMA
  97         struct omap_hsmmc_adma_desc *adma_desc_table;
  98         uint desc_slot;
  99 #endif
 100         const char *hw_rev;
 101         struct udevice *pbias_supply;
 102         uint signal_voltage;
 103 #ifdef CONFIG_IODELAY_RECALIBRATION
 104         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 105         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 106         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 107         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 108         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 109         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 110         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 111         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 112         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 113 #endif
 114 };
 115
 116 struct omap_mmc_of_data {
 117         u8 controller_flags;
 118 };
 119
 120 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 121 struct omap_hsmmc_adma_desc {
 122         u8 attr;
 123         u8 reserved;
 124         u16 len;
 125         u32 addr;
 126 };
 127
 128 #define ADMA_MAX_LEN    63488
 129
 130 /* Decriptor table defines */
 131 #define ADMA_DESC_ATTR_VALID            BIT(0)
 132 #define ADMA_DESC_ATTR_END              BIT(1)
 133 #define ADMA_DESC_ATTR_INT              BIT(2)
 134 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 135 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 136
 137 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 138 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 139 #endif
 140
 141 /* If we fail after 1 second wait, something is really bad */
 142 #define MAX_RETRY_MS    1000
 143 #define MMC_TIMEOUT_MS  20
 144
 145 /* DMA transfers can take a long time if a lot a data is transferred.
 146  * The timeout must take in account the amount of data. Let's assume
 147  * that the time will never exceed 333 ms per MB (in other word we assume
 148  * that the bandwidth is always above 3MB/s).
 149  */
 150 #define DMA_TIMEOUT_PER_MB      333
 151 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 152 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 153 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 154 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 155
 156 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 157 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 158                         unsigned int siz);
 159 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 160 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 161 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 162
 163 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 164 {
 165 #if CONFIG_IS_ENABLED(DM_MMC)
 166         return dev_get_priv(mmc->dev);
 167 #else
 168         return (struct omap_hsmmc_data *)mmc->priv;
 169 #endif
 170 }
 171 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 172 {
 173 #if CONFIG_IS_ENABLED(DM_MMC)
 174         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 175         return &plat->cfg;
 176 #else
 177         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 178 #endif
 179 }
 180
 181 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 182 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 183 {
 184         int ret;
 185
 186 #ifndef CONFIG_DM_GPIO
 187         if (!gpio_is_valid(gpio))
 188                 return -1;
 189 #endif
 190         ret = gpio_request(gpio, label);
 191         if (ret)
 192                 return ret;
 193
 194         ret = gpio_direction_input(gpio);
 195         if (ret)
 196                 return ret;
 197
 198         return gpio;
 199 }
 200 #endif
 201
 202 static unsigned char mmc_board_init(struct mmc *mmc)
 203 {
 204 #if defined(CONFIG_OMAP34XX)
 205         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 206         t2_t *t2_base = (t2_t *)T2_BASE;
 207         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 208         u32 pbias_lite;
 209 #ifdef CONFIG_MMC_OMAP36XX_PINS
 210         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 211 #endif
 212
 213         pbias_lite = readl(&t2_base->pbias_lite);
 214         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 215 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 216         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 217         pbias_lite &= ~PBIASLITEVMODE0;
 218 #endif
 219 #ifdef CONFIG_TARGET_OMAP3_LOGIC
 220         /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
 221         pbias_lite &= ~PBIASLITEVMODE1;
 222 #endif
 223 #ifdef CONFIG_MMC_OMAP36XX_PINS
 224         if (get_cpu_family() == CPU_OMAP36XX) {
 225                 /* Disable extended drain IO before changing PBIAS */
 226                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 227                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 228         }
 229 #endif
 230         writel(pbias_lite, &t2_base->pbias_lite);
 231
 232         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 233                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 234                 &t2_base->pbias_lite);
 235
 236 #ifdef CONFIG_MMC_OMAP36XX_PINS
 237         if (get_cpu_family() == CPU_OMAP36XX)
 238                 /* Enable extended drain IO after changing PBIAS */
 239                 writel(wkup_ctrl |
 240                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 241                                 OMAP34XX_CTRL_WKUP_CTRL);
 242 #endif
 243         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 244                 &t2_base->devconf0);
 245
 246         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 247                 &t2_base->devconf1);
 248
 249         /* Change from default of 52MHz to 26MHz if necessary */
 250         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 251                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 252                         &t2_base->ctl_prog_io1);
 253
 254         writel(readl(&prcm_base->fclken1_core) |
 255                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 256                 &prcm_base->fclken1_core);
 257
 258         writel(readl(&prcm_base->iclken1_core) |
 259                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 260                 &prcm_base->iclken1_core);
 261 #endif
 262
 263 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
 264         !CONFIG_IS_ENABLED(DM_REGULATOR)
 265         /* PBIAS config needed for MMC1 only */
 266         if (mmc_get_blk_desc(mmc)->devnum == 0)
 267                 vmmc_pbias_config(LDO_VOLT_3V3);
 268 #endif
 269
 270         return 0;
 271 }
 272
 273 void mmc_init_stream(struct hsmmc *mmc_base)
 274 {
 275         ulong start;
 276
 277         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 278
 279         writel(MMC_CMD0, &mmc_base->cmd);
 280         start = get_timer(0);
 281         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 282                 if (get_timer(0) - start > MAX_RETRY_MS) {
 283                         printf("%s: timedout waiting for cc!\n", __func__);
 284                         return;
 285                 }
 286         }
 287         writel(CC_MASK, &mmc_base->stat)
 288                 ;
 289         writel(MMC_CMD0, &mmc_base->cmd)
 290                 ;
 291         start = get_timer(0);
 292         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 293                 if (get_timer(0) - start > MAX_RETRY_MS) {
 294                         printf("%s: timedout waiting for cc2!\n", __func__);
 295                         return;
 296                 }
 297         }
 298         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 299 }
 300
 301 #if CONFIG_IS_ENABLED(DM_MMC)
 302 #ifdef CONFIG_IODELAY_RECALIBRATION
 303 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 304 {
 305         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 306         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 307
 308         switch (priv->mode) {
 309         case MMC_HS_200:
 310                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 311                 break;
 312         case UHS_SDR104:
 313                 pinctrl_state = priv->sdr104_pinctrl_state;
 314                 break;
 315         case UHS_SDR50:
 316                 pinctrl_state = priv->sdr50_pinctrl_state;
 317                 break;
 318         case UHS_DDR50:
 319                 pinctrl_state = priv->ddr50_pinctrl_state;
 320                 break;
 321         case UHS_SDR25:
 322                 pinctrl_state = priv->sdr25_pinctrl_state;
 323                 break;
 324         case UHS_SDR12:
 325                 pinctrl_state = priv->sdr12_pinctrl_state;
 326                 break;
 327         case SD_HS:
 328         case MMC_HS:
 329         case MMC_HS_52:
 330                 pinctrl_state = priv->hs_pinctrl_state;
 331                 break;
 332         case MMC_DDR_52:
 333                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 334         default:
 335                 pinctrl_state = priv->default_pinctrl_state;
 336                 break;
 337         }
 338
 339         if (!pinctrl_state)
 340                 pinctrl_state = priv->default_pinctrl_state;
 341
 342         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 343                 if (pinctrl_state->iodelay)
 344                         late_recalibrate_iodelay(pinctrl_state->padconf,
 345                                                  pinctrl_state->npads,
 346                                                  pinctrl_state->iodelay,
 347                                                  pinctrl_state->niodelays);
 348                 else
 349                         do_set_mux32((*ctrl)->control_padconf_core_base,
 350                                      pinctrl_state->padconf,
 351                                      pinctrl_state->npads);
 352         }
 353 }
 354 #endif
 355 static void omap_hsmmc_set_timing(struct mmc *mmc)
 356 {
 357         u32 val;
 358         struct hsmmc *mmc_base;
 359         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 360
 361         mmc_base = priv->base_addr;
 362
 363         omap_hsmmc_stop_clock(mmc_base);
 364         val = readl(&mmc_base->ac12);
 365         val &= ~AC12_UHSMC_MASK;
 366         priv->mode = mmc->selected_mode;
 367
 368         if (mmc_is_mode_ddr(priv->mode))
 369                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 370         else
 371                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 372
 373         switch (priv->mode) {
 374         case MMC_HS_200:
 375         case UHS_SDR104:
 376                 val |= AC12_UHSMC_SDR104;
 377                 break;
 378         case UHS_SDR50:
 379                 val |= AC12_UHSMC_SDR50;
 380                 break;
 381         case MMC_DDR_52:
 382         case UHS_DDR50:
 383                 val |= AC12_UHSMC_DDR50;
 384                 break;
 385         case SD_HS:
 386         case MMC_HS_52:
 387         case UHS_SDR25:
 388                 val |= AC12_UHSMC_SDR25;
 389                 break;
 390         case MMC_LEGACY:
 391         case MMC_HS:
 392         case SD_LEGACY:
 393         case UHS_SDR12:
 394                 val |= AC12_UHSMC_SDR12;
 395                 break;
 396         default:
 397                 val |= AC12_UHSMC_RES;
 398                 break;
 399         }
 400         writel(val, &mmc_base->ac12);
 401
 402 #ifdef CONFIG_IODELAY_RECALIBRATION
 403         omap_hsmmc_io_recalibrate(mmc);
 404 #endif
 405         omap_hsmmc_start_clock(mmc_base);
 406 }
 407
 408 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 409 {
 410         struct hsmmc *mmc_base;
 411         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 412         u32 hctl, ac12;
 413
 414         mmc_base = priv->base_addr;
 415
 416         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
 417         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 418
 419         switch (signal_voltage) {
 420         case MMC_SIGNAL_VOLTAGE_330:
 421                 hctl |= SDVS_3V3;
 422                 break;
 423         case MMC_SIGNAL_VOLTAGE_180:
 424                 hctl |= SDVS_1V8;
 425                 ac12 |= AC12_V1V8_SIGEN;
 426                 break;
 427         }
 428
 429         writel(hctl, &mmc_base->hctl);
 430         writel(ac12, &mmc_base->ac12);
 431 }
 432
 433 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
 434 {
 435         int ret = -ETIMEDOUT;
 436         u32 con;
 437         bool dat0_high;
 438         bool target_dat0_high = !!state;
 439         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 440         struct hsmmc *mmc_base = priv->base_addr;
 441
 442         con = readl(&mmc_base->con);
 443         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
 444
 445         timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
 446         while (timeout_us--) {
 447                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
 448                 if (dat0_high == target_dat0_high) {
 449                         ret = 0;
 450                         break;
 451                 }
 452                 udelay(10);
 453         }
 454         writel(con, &mmc_base->con);
 455
 456         return ret;
 457 }
 458
 459 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 460 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 461 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
 462 {
 463         int ret = 0;
 464         int uV = mV * 1000;
 465
 466         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 467
 468         if (!mmc->vqmmc_supply)
 469                 return 0;
 470
 471         /* Disable PBIAS */
 472         ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
 473         if (ret)
 474                 return ret;
 475
 476         /* Turn off IO voltage */
 477         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
 478         if (ret)
 479                 return ret;
 480         /* Program a new IO voltage value */
 481         ret = regulator_set_value(mmc->vqmmc_supply, uV);
 482         if (ret)
 483                 return ret;
 484         /* Turn on IO voltage */
 485         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 486         if (ret)
 487                 return ret;
 488
 489         /* Program PBIAS voltage*/
 490         ret = regulator_set_value(priv->pbias_supply, uV);
 491         if (ret && ret != -ENOSYS)
 492                 return ret;
 493         /* Enable PBIAS */
 494         ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
 495         if (ret)
 496                 return ret;
 497
 498         return 0;
 499 }
 500 #endif
 501
 502 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 503 {
 504         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 505         struct hsmmc *mmc_base = priv->base_addr;
 506         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
 507         u32 capa_mask;
 508         __maybe_unused u8 palmas_ldo_volt;
 509         u32 val;
 510
 511         if (mv < 0)
 512                 return -EINVAL;
 513
 514         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 515                 mv = 3300;
 516                 capa_mask = VS33_3V3SUP;
 517                 palmas_ldo_volt = LDO_VOLT_3V3;
 518         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 519                 capa_mask = VS18_1V8SUP;
 520                 palmas_ldo_volt = LDO_VOLT_1V8;
 521         } else {
 522                 return -EOPNOTSUPP;
 523         }
 524
 525         val = readl(&mmc_base->capa);
 526         if (!(val & capa_mask))
 527                 return -EOPNOTSUPP;
 528
 529         priv->signal_voltage = mmc->signal_voltage;
 530
 531         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
 532
 533 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 534         return omap_hsmmc_set_io_regulator(mmc, mv);
 535 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
 536         defined(CONFIG_PALMAS_POWER)
 537         if (mmc_get_blk_desc(mmc)->devnum == 0)
 538                 vmmc_pbias_config(palmas_ldo_volt);
 539         return 0;
 540 #else
 541         return 0;
 542 #endif
 543 }
 544 #endif
 545
 546 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
 547 {
 548         struct hsmmc *mmc_base;
 549         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 550         u32 val;
 551
 552         mmc_base = priv->base_addr;
 553         val = readl(&mmc_base->capa);
 554
 555         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 556                 val |= (VS33_3V3SUP | VS18_1V8SUP);
 557         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 558                 val |= VS33_3V3SUP;
 559                 val &= ~VS18_1V8SUP;
 560         } else {
 561                 val |= VS18_1V8SUP;
 562                 val &= ~VS33_3V3SUP;
 563         }
 564
 565         writel(val, &mmc_base->capa);
 566
 567         return val;
 568 }
 569
 570 #ifdef MMC_SUPPORTS_TUNING
 571 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 572 {
 573         struct hsmmc *mmc_base;
 574         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 575         u32 val;
 576
 577         mmc_base = priv->base_addr;
 578         val = readl(&mmc_base->ac12);
 579         val &= ~(AC12_SCLK_SEL);
 580         writel(val, &mmc_base->ac12);
 581
 582         val = readl(&mmc_base->dll);
 583         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 584         writel(val, &mmc_base->dll);
 585 }
 586
 587 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 588 {
 589         int i;
 590         struct hsmmc *mmc_base;
 591         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 592         u32 val;
 593
 594         mmc_base = priv->base_addr;
 595         val = readl(&mmc_base->dll);
 596         val |= DLL_FORCE_VALUE;
 597         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 598         val |= (count << DLL_FORCE_SR_C_SHIFT);
 599         writel(val, &mmc_base->dll);
 600
 601         val |= DLL_CALIB;
 602         writel(val, &mmc_base->dll);
 603         for (i = 0; i < 1000; i++) {
 604                 if (readl(&mmc_base->dll) & DLL_CALIB)
 605                         break;
 606         }
 607         val &= ~DLL_CALIB;
 608         writel(val, &mmc_base->dll);
 609 }
 610
 611 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 612 {
 613         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 614         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 615         struct mmc *mmc = upriv->mmc;
 616         struct hsmmc *mmc_base;
 617         u32 val;
 618         u8 cur_match, prev_match = 0;
 619         int ret;
 620         u32 phase_delay = 0;
 621         u32 start_window = 0, max_window = 0;
 622         u32 length = 0, max_len = 0;
 623         bool single_point_failure = false;
 624         struct udevice *thermal_dev;
 625         int temperature;
 626         int i;
 627
 628         mmc_base = priv->base_addr;
 629         val = readl(&mmc_base->capa2);
 630
 631         /* clock tuning is not needed for upto 52MHz */
 632         if (!((mmc->selected_mode == MMC_HS_200) ||
 633               (mmc->selected_mode == UHS_SDR104) ||
 634               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 635                 return 0;
 636
 637         ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
 638         if (ret) {
 639                 printf("Couldn't get thermal device for tuning\n");
 640                 return ret;
 641         }
 642         ret = thermal_get_temp(thermal_dev, &temperature);
 643         if (ret) {
 644                 printf("Couldn't get temperature for tuning\n");
 645                 return ret;
 646         }
 647         val = readl(&mmc_base->dll);
 648         val |= DLL_SWT;
 649         writel(val, &mmc_base->dll);
 650
 651         /*
 652          * Stage 1: Search for a maximum pass window ignoring any
 653          * any single point failures. If the tuning value ends up
 654          * near it, move away from it in stage 2 below
 655          */
 656         while (phase_delay <= MAX_PHASE_DELAY) {
 657                 omap_hsmmc_set_dll(mmc, phase_delay);
 658
 659                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 660
 661                 if (cur_match) {
 662                         if (prev_match) {
 663                                 length++;
 664                         } else if (single_point_failure) {
 665                                 /* ignore single point failure */
 666                                 length++;
 667                                 single_point_failure = false;
 668                         } else {
 669                                 start_window = phase_delay;
 670                                 length = 1;
 671                         }
 672                 } else {
 673                         single_point_failure = prev_match;
 674                 }
 675
 676                 if (length > max_len) {
 677                         max_window = start_window;
 678                         max_len = length;
 679                 }
 680
 681                 prev_match = cur_match;
 682                 phase_delay += 4;
 683         }
 684
 685         if (!max_len) {
 686                 ret = -EIO;
 687                 goto tuning_error;
 688         }
 689
 690         val = readl(&mmc_base->ac12);
 691         if (!(val & AC12_SCLK_SEL)) {
 692                 ret = -EIO;
 693                 goto tuning_error;
 694         }
 695         /*
 696          * Assign tuning value as a ratio of maximum pass window based
 697          * on temperature
 698          */
 699         if (temperature < -20000)
 700                 phase_delay = min(max_window + 4 * max_len - 24,
 701                                   max_window +
 702                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 703         else if (temperature < 20000)
 704                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 705         else if (temperature < 40000)
 706                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 707         else if (temperature < 70000)
 708                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 709         else if (temperature < 90000)
 710                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 711         else if (temperature < 120000)
 712                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 713         else
 714                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 715
 716         /*
 717          * Stage 2: Search for a single point failure near the chosen tuning
 718          * value in two steps. First in the +3 to +10 range and then in the
 719          * +2 to -10 range. If found, move away from it in the appropriate
 720          * direction by the appropriate amount depending on the temperature.
 721          */
 722         for (i = 3; i <= 10; i++) {
 723                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 724                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 725                         if (temperature < 10000)
 726                                 phase_delay += i + 6;
 727                         else if (temperature < 20000)
 728                                 phase_delay += i - 12;
 729                         else if (temperature < 70000)
 730                                 phase_delay += i - 8;
 731                         else if (temperature < 90000)
 732                                 phase_delay += i - 6;
 733                         else
 734                                 phase_delay += i - 6;
 735
 736                         goto single_failure_found;
 737                 }
 738         }
 739
 740         for (i = 2; i >= -10; i--) {
 741                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 742                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 743                         if (temperature < 10000)
 744                                 phase_delay += i + 12;
 745                         else if (temperature < 20000)
 746                                 phase_delay += i + 8;
 747                         else if (temperature < 70000)
 748                                 phase_delay += i + 8;
 749                         else if (temperature < 90000)
 750                                 phase_delay += i + 10;
 751                         else
 752                                 phase_delay += i + 12;
 753
 754                         goto single_failure_found;
 755                 }
 756         }
 757
 758 single_failure_found:
 759
 760         omap_hsmmc_set_dll(mmc, phase_delay);
 761
 762         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 763         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 764
 765         return 0;
 766
 767 tuning_error:
 768
 769         omap_hsmmc_disable_tuning(mmc);
 770         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 771         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 772
 773         return ret;
 774 }
 775 #endif
 776 #endif
 777
 778 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 779 {
 780         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 781         struct hsmmc *mmc_base = priv->base_addr;
 782         u32 irq_mask = INT_EN_MASK;
 783
 784         /*
 785          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 786          * tuning procedure and DCRC should be disabled. But see occurences
 787          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 788          * interrupts occur along with BRR, so the data is actually in the
 789          * buffer. It has to be debugged why these interrutps occur
 790          */
 791         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 792                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 793
 794         writel(irq_mask, &mmc_base->ie);
 795 }
 796
 797 static int omap_hsmmc_init_setup(struct mmc *mmc)
 798 {
 799         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 800         struct hsmmc *mmc_base;
 801         unsigned int reg_val;
 802         unsigned int dsor;
 803         ulong start;
 804
 805         mmc_base = priv->base_addr;
 806         mmc_board_init(mmc);
 807
 808         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 809                 &mmc_base->sysconfig);
 810         start = get_timer(0);
 811         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 812                 if (get_timer(0) - start > MAX_RETRY_MS) {
 813                         printf("%s: timedout waiting for cc2!\n", __func__);
 814                         return -ETIMEDOUT;
 815                 }
 816         }
 817         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 818         start = get_timer(0);
 819         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 820                 if (get_timer(0) - start > MAX_RETRY_MS) {
 821                         printf("%s: timedout waiting for softresetall!\n",
 822                                 __func__);
 823                         return -ETIMEDOUT;
 824                 }
 825         }
 826 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 827         reg_val = readl(&mmc_base->hl_hwinfo);
 828         if (reg_val & MADMA_EN)
 829                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 830 #endif
 831
 832 #if CONFIG_IS_ENABLED(DM_MMC)
 833         reg_val = omap_hsmmc_set_capabilities(mmc);
 834         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
 835                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
 836 #else
 837         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 838         writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
 839                 &mmc_base->capa);
 840 #endif
 841
 842         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 843
 844         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 845                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 846                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 847
 848         dsor = 240;
 849         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 850                 (ICE_STOP | DTO_15THDTO));
 851         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 852                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 853         start = get_timer(0);
 854         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 855                 if (get_timer(0) - start > MAX_RETRY_MS) {
 856                         printf("%s: timedout waiting for ics!\n", __func__);
 857                         return -ETIMEDOUT;
 858                 }
 859         }
 860         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 861
 862         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 863
 864         mmc_enable_irq(mmc, NULL);
 865
 866 #if !CONFIG_IS_ENABLED(DM_MMC)
 867         mmc_init_stream(mmc_base);
 868 #endif
 869
 870         return 0;
 871 }
 872
 873 /*
 874  * MMC controller internal finite state machine reset
 875  *
 876  * Used to reset command or data internal state machines, using respectively
 877  * SRC or SRD bit of SYSCTL register
 878  */
 879 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 880 {
 881         ulong start;
 882
 883         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 884
 885         /*
 886          * CMD(DAT) lines reset procedures are slightly different
 887          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 888          * According to OMAP3 TRM:
 889          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 890          * returns to 0x0.
 891          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 892          * procedure steps must be as follows:
 893          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 894          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 895          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 896          * 3. Wait until the SRC (SRD) bit returns to 0x0
 897          *    (reset procedure is completed).
 898          */
 899 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 900         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 901         if (!(readl(&mmc_base->sysctl) & bit)) {
 902                 start = get_timer(0);
 903                 while (!(readl(&mmc_base->sysctl) & bit)) {
 904                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 905                                 return;
 906                 }
 907         }
 908 #endif
 909         start = get_timer(0);
 910         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 911                 if (get_timer(0) - start > MAX_RETRY_MS) {
 912                         printf("%s: timedout waiting for sysctl %x to clear\n",
 913                                 __func__, bit);
 914                         return;
 915                 }
 916         }
 917 }
 918
 919 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 920 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 921 {
 922         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 923         struct omap_hsmmc_adma_desc *desc;
 924         u8 attr;
 925
 926         desc = &priv->adma_desc_table[priv->desc_slot];
 927
 928         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 929         if (!end)
 930                 priv->desc_slot++;
 931         else
 932                 attr |= ADMA_DESC_ATTR_END;
 933
 934         desc->len = len;
 935         desc->addr = (u32)buf;
 936         desc->reserved = 0;
 937         desc->attr = attr;
 938 }
 939
 940 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 941                                           struct mmc_data *data)
 942 {
 943         uint total_len = data->blocksize * data->blocks;
 944         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 945         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 946         int i = desc_count;
 947         char *buf;
 948
 949         priv->desc_slot = 0;
 950         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 951                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 952                                 sizeof(struct omap_hsmmc_adma_desc));
 953
 954         if (data->flags & MMC_DATA_READ)
 955                 buf = data->dest;
 956         else
 957                 buf = (char *)data->src;
 958
 959         while (--i) {
 960                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 961                 buf += ADMA_MAX_LEN;
 962                 total_len -= ADMA_MAX_LEN;
 963         }
 964
 965         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 966
 967         flush_dcache_range((long)priv->adma_desc_table,
 968                            (long)priv->adma_desc_table +
 969                            ROUND(desc_count *
 970                            sizeof(struct omap_hsmmc_adma_desc),
 971                            ARCH_DMA_MINALIGN));
 972 }
 973
 974 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 975 {
 976         struct hsmmc *mmc_base;
 977         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 978         u32 val;
 979         char *buf;
 980
 981         mmc_base = priv->base_addr;
 982         omap_hsmmc_prepare_adma_table(mmc, data);
 983
 984         if (data->flags & MMC_DATA_READ)
 985                 buf = data->dest;
 986         else
 987                 buf = (char *)data->src;
 988
 989         val = readl(&mmc_base->hctl);
 990         val |= DMA_SELECT;
 991         writel(val, &mmc_base->hctl);
 992
 993         val = readl(&mmc_base->con);
 994         val |= DMA_MASTER;
 995         writel(val, &mmc_base->con);
 996
 997         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
 998
 999         flush_dcache_range((u32)buf,
1000                            (u32)buf +
1001                            ROUND(data->blocksize * data->blocks,
1002                                  ARCH_DMA_MINALIGN));
1003 }
1004
1005 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1006 {
1007         struct hsmmc *mmc_base;
1008         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1009         u32 val;
1010
1011         mmc_base = priv->base_addr;
1012
1013         val = readl(&mmc_base->con);
1014         val &= ~DMA_MASTER;
1015         writel(val, &mmc_base->con);
1016
1017         val = readl(&mmc_base->hctl);
1018         val &= ~DMA_SELECT;
1019         writel(val, &mmc_base->hctl);
1020
1021         kfree(priv->adma_desc_table);
1022 }
1023 #else
1024 #define omap_hsmmc_adma_desc
1025 #define omap_hsmmc_prepare_adma_table
1026 #define omap_hsmmc_prepare_data
1027 #define omap_hsmmc_dma_cleanup
1028 #endif
1029
1030 #if !CONFIG_IS_ENABLED(DM_MMC)
1031 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1032                         struct mmc_data *data)
1033 {
1034         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1035 #else
1036 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1037                         struct mmc_data *data)
1038 {
1039         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1040         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1041         struct mmc *mmc = upriv->mmc;
1042 #endif
1043         struct hsmmc *mmc_base;
1044         unsigned int flags, mmc_stat;
1045         ulong start;
1046         priv->last_cmd = cmd->cmdidx;
1047
1048         mmc_base = priv->base_addr;
1049
1050         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1051                 return 0;
1052
1053         start = get_timer(0);
1054         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1055                 if (get_timer(0) - start > MAX_RETRY_MS) {
1056                         printf("%s: timedout waiting on cmd inhibit to clear\n",
1057                                         __func__);
1058                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1059                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1060                         return -ETIMEDOUT;
1061                 }
1062         }
1063         writel(0xFFFFFFFF, &mmc_base->stat);
1064         if (readl(&mmc_base->stat)) {
1065                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1066                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1067         }
1068
1069         /*
1070          * CMDREG
1071          * CMDIDX[13:8] : Command index
1072          * DATAPRNT[5]  : Data Present Select
1073          * ENCMDIDX[4]  : Command Index Check Enable
1074          * ENCMDCRC[3]  : Command CRC Check Enable
1075          * RSPTYP[1:0]
1076          *      00 = No Response
1077          *      01 = Length 136
1078          *      10 = Length 48
1079          *      11 = Length 48 Check busy after response
1080          */
1081         /* Delay added before checking the status of frq change
1082          * retry not supported by mmc.c(core file)
1083          */
1084         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1085                 udelay(50000); /* wait 50 ms */
1086
1087         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1088                 flags = 0;
1089         else if (cmd->resp_type & MMC_RSP_136)
1090                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1091         else if (cmd->resp_type & MMC_RSP_BUSY)
1092                 flags = RSP_TYPE_LGHT48B;
1093         else
1094                 flags = RSP_TYPE_LGHT48;
1095
1096         /* enable default flags */
1097         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1098                         MSBS_SGLEBLK);
1099         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1100
1101         if (cmd->resp_type & MMC_RSP_CRC)
1102                 flags |= CCCE_CHECK;
1103         if (cmd->resp_type & MMC_RSP_OPCODE)
1104                 flags |= CICE_CHECK;
1105
1106         if (data) {
1107                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1108                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1109                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1110                         data->blocksize = 512;
1111                         writel(data->blocksize | (data->blocks << 16),
1112                                                         &mmc_base->blk);
1113                 } else
1114                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1115
1116                 if (data->flags & MMC_DATA_READ)
1117                         flags |= (DP_DATA | DDIR_READ);
1118                 else
1119                         flags |= (DP_DATA | DDIR_WRITE);
1120
1121 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1122                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1123                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1124                         omap_hsmmc_prepare_data(mmc, data);
1125                         flags |= DE_ENABLE;
1126                 }
1127 #endif
1128         }
1129
1130         mmc_enable_irq(mmc, cmd);
1131
1132         writel(cmd->cmdarg, &mmc_base->arg);
1133         udelay(20);             /* To fix "No status update" error on eMMC */
1134         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1135
1136         start = get_timer(0);
1137         do {
1138                 mmc_stat = readl(&mmc_base->stat);
1139                 if (get_timer(start) > MAX_RETRY_MS) {
1140                         printf("%s : timeout: No status update\n", __func__);
1141                         return -ETIMEDOUT;
1142                 }
1143         } while (!mmc_stat);
1144
1145         if ((mmc_stat & IE_CTO) != 0) {
1146                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1147                 return -ETIMEDOUT;
1148         } else if ((mmc_stat & ERRI_MASK) != 0)
1149                 return -1;
1150
1151         if (mmc_stat & CC_MASK) {
1152                 writel(CC_MASK, &mmc_base->stat);
1153                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1154                         if (cmd->resp_type & MMC_RSP_136) {
1155                                 /* response type 2 */
1156                                 cmd->response[3] = readl(&mmc_base->rsp10);
1157                                 cmd->response[2] = readl(&mmc_base->rsp32);
1158                                 cmd->response[1] = readl(&mmc_base->rsp54);
1159                                 cmd->response[0] = readl(&mmc_base->rsp76);
1160                         } else
1161                                 /* response types 1, 1b, 3, 4, 5, 6 */
1162                                 cmd->response[0] = readl(&mmc_base->rsp10);
1163                 }
1164         }
1165
1166 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1167         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1168             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1169                 u32 sz_mb, timeout;
1170
1171                 if (mmc_stat & IE_ADMAE) {
1172                         omap_hsmmc_dma_cleanup(mmc);
1173                         return -EIO;
1174                 }
1175
1176                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1177                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1178                 if (timeout < MAX_RETRY_MS)
1179                         timeout = MAX_RETRY_MS;
1180
1181                 start = get_timer(0);
1182                 do {
1183                         mmc_stat = readl(&mmc_base->stat);
1184                         if (mmc_stat & TC_MASK) {
1185                                 writel(readl(&mmc_base->stat) | TC_MASK,
1186                                        &mmc_base->stat);
1187                                 break;
1188                         }
1189                         if (get_timer(start) > timeout) {
1190                                 printf("%s : DMA timeout: No status update\n",
1191                                        __func__);
1192                                 return -ETIMEDOUT;
1193                         }
1194                 } while (1);
1195
1196                 omap_hsmmc_dma_cleanup(mmc);
1197                 return 0;
1198         }
1199 #endif
1200
1201         if (data && (data->flags & MMC_DATA_READ)) {
1202                 mmc_read_data(mmc_base, data->dest,
1203                                 data->blocksize * data->blocks);
1204         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1205                 mmc_write_data(mmc_base, data->src,
1206                                 data->blocksize * data->blocks);
1207         }
1208         return 0;
1209 }
1210
1211 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1212 {
1213         unsigned int *output_buf = (unsigned int *)buf;
1214         unsigned int mmc_stat;
1215         unsigned int count;
1216
1217         /*
1218          * Start Polled Read
1219          */
1220         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1221         count /= 4;
1222
1223         while (size) {
1224                 ulong start = get_timer(0);
1225                 do {
1226                         mmc_stat = readl(&mmc_base->stat);
1227                         if (get_timer(0) - start > MAX_RETRY_MS) {
1228                                 printf("%s: timedout waiting for status!\n",
1229                                                 __func__);
1230                                 return -ETIMEDOUT;
1231                         }
1232                 } while (mmc_stat == 0);
1233
1234                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1235                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1236
1237                 if ((mmc_stat & ERRI_MASK) != 0)
1238                         return 1;
1239
1240                 if (mmc_stat & BRR_MASK) {
1241                         unsigned int k;
1242
1243                         writel(readl(&mmc_base->stat) | BRR_MASK,
1244                                 &mmc_base->stat);
1245                         for (k = 0; k < count; k++) {
1246                                 *output_buf = readl(&mmc_base->data);
1247                                 output_buf++;
1248                         }
1249                         size -= (count*4);
1250                 }
1251
1252                 if (mmc_stat & BWR_MASK)
1253                         writel(readl(&mmc_base->stat) | BWR_MASK,
1254                                 &mmc_base->stat);
1255
1256                 if (mmc_stat & TC_MASK) {
1257                         writel(readl(&mmc_base->stat) | TC_MASK,
1258                                 &mmc_base->stat);
1259                         break;
1260                 }
1261         }
1262         return 0;
1263 }
1264
1265 #if CONFIG_IS_ENABLED(MMC_WRITE)
1266 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1267                           unsigned int size)
1268 {
1269         unsigned int *input_buf = (unsigned int *)buf;
1270         unsigned int mmc_stat;
1271         unsigned int count;
1272
1273         /*
1274          * Start Polled Write
1275          */
1276         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1277         count /= 4;
1278
1279         while (size) {
1280                 ulong start = get_timer(0);
1281                 do {
1282                         mmc_stat = readl(&mmc_base->stat);
1283                         if (get_timer(0) - start > MAX_RETRY_MS) {
1284                                 printf("%s: timedout waiting for status!\n",
1285                                                 __func__);
1286                                 return -ETIMEDOUT;
1287                         }
1288                 } while (mmc_stat == 0);
1289
1290                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1291                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1292
1293                 if ((mmc_stat & ERRI_MASK) != 0)
1294                         return 1;
1295
1296                 if (mmc_stat & BWR_MASK) {
1297                         unsigned int k;
1298
1299                         writel(readl(&mmc_base->stat) | BWR_MASK,
1300                                         &mmc_base->stat);
1301                         for (k = 0; k < count; k++) {
1302                                 writel(*input_buf, &mmc_base->data);
1303                                 input_buf++;
1304                         }
1305                         size -= (count*4);
1306                 }
1307
1308                 if (mmc_stat & BRR_MASK)
1309                         writel(readl(&mmc_base->stat) | BRR_MASK,
1310                                 &mmc_base->stat);
1311
1312                 if (mmc_stat & TC_MASK) {
1313                         writel(readl(&mmc_base->stat) | TC_MASK,
1314                                 &mmc_base->stat);
1315                         break;
1316                 }
1317         }
1318         return 0;
1319 }
1320 #else
1321 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1322                           unsigned int size)
1323 {
1324         return -ENOTSUPP;
1325 }
1326 #endif
1327 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1328 {
1329         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1330 }
1331
1332 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1333 {
1334         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1335 }
1336
1337 static void omap_hsmmc_set_clock(struct mmc *mmc)
1338 {
1339         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1340         struct hsmmc *mmc_base;
1341         unsigned int dsor = 0;
1342         ulong start;
1343
1344         mmc_base = priv->base_addr;
1345         omap_hsmmc_stop_clock(mmc_base);
1346
1347         /* TODO: Is setting DTO required here? */
1348         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1349                     (ICE_STOP | DTO_15THDTO));
1350
1351         if (mmc->clock != 0) {
1352                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1353                 if (dsor > CLKD_MAX)
1354                         dsor = CLKD_MAX;
1355         } else {
1356                 dsor = CLKD_MAX;
1357         }
1358
1359         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1360                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1361
1362         start = get_timer(0);
1363         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1364                 if (get_timer(0) - start > MAX_RETRY_MS) {
1365                         printf("%s: timedout waiting for ics!\n", __func__);
1366                         return;
1367                 }
1368         }
1369
1370         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1371         mmc->clock = priv->clock;
1372         omap_hsmmc_start_clock(mmc_base);
1373 }
1374
1375 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1376 {
1377         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1378         struct hsmmc *mmc_base;
1379
1380         mmc_base = priv->base_addr;
1381         /* configue bus width */
1382         switch (mmc->bus_width) {
1383         case 8:
1384                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1385                         &mmc_base->con);
1386                 break;
1387
1388         case 4:
1389                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1390                         &mmc_base->con);
1391                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1392                         &mmc_base->hctl);
1393                 break;
1394
1395         case 1:
1396         default:
1397                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1398                         &mmc_base->con);
1399                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1400                         &mmc_base->hctl);
1401                 break;
1402         }
1403
1404         priv->bus_width = mmc->bus_width;
1405 }
1406
1407 #if !CONFIG_IS_ENABLED(DM_MMC)
1408 static int omap_hsmmc_set_ios(struct mmc *mmc)
1409 {
1410         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1411 #else
1412 static int omap_hsmmc_set_ios(struct udevice *dev)
1413 {
1414         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1415         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1416         struct mmc *mmc = upriv->mmc;
1417 #endif
1418         struct hsmmc *mmc_base = priv->base_addr;
1419         int ret = 0;
1420
1421         if (priv->bus_width != mmc->bus_width)
1422                 omap_hsmmc_set_bus_width(mmc);
1423
1424         if (priv->clock != mmc->clock)
1425                 omap_hsmmc_set_clock(mmc);
1426
1427         if (mmc->clk_disable)
1428                 omap_hsmmc_stop_clock(mmc_base);
1429         else
1430                 omap_hsmmc_start_clock(mmc_base);
1431
1432 #if CONFIG_IS_ENABLED(DM_MMC)
1433         if (priv->mode != mmc->selected_mode)
1434                 omap_hsmmc_set_timing(mmc);
1435
1436 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1437         if (priv->signal_voltage != mmc->signal_voltage)
1438                 ret = omap_hsmmc_set_signal_voltage(mmc);
1439 #endif
1440 #endif
1441         return ret;
1442 }
1443
1444 #ifdef OMAP_HSMMC_USE_GPIO
1445 #if CONFIG_IS_ENABLED(DM_MMC)
1446 static int omap_hsmmc_getcd(struct udevice *dev)
1447 {
1448         int value = -1;
1449 #if CONFIG_IS_ENABLED(DM_GPIO)
1450         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1451         value = dm_gpio_get_value(&priv->cd_gpio);
1452 #endif
1453         /* if no CD return as 1 */
1454         if (value < 0)
1455                 return 1;
1456
1457         return value;
1458 }
1459
1460 static int omap_hsmmc_getwp(struct udevice *dev)
1461 {
1462         int value = 0;
1463 #if CONFIG_IS_ENABLED(DM_GPIO)
1464         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1465         value = dm_gpio_get_value(&priv->wp_gpio);
1466 #endif
1467         /* if no WP return as 0 */
1468         if (value < 0)
1469                 return 0;
1470         return value;
1471 }
1472 #else
1473 static int omap_hsmmc_getcd(struct mmc *mmc)
1474 {
1475         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1476         int cd_gpio;
1477
1478         /* if no CD return as 1 */
1479         cd_gpio = priv->cd_gpio;
1480         if (cd_gpio < 0)
1481                 return 1;
1482
1483         /* NOTE: assumes card detect signal is active-low */
1484         return !gpio_get_value(cd_gpio);
1485 }
1486
1487 static int omap_hsmmc_getwp(struct mmc *mmc)
1488 {
1489         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1490         int wp_gpio;
1491
1492         /* if no WP return as 0 */
1493         wp_gpio = priv->wp_gpio;
1494         if (wp_gpio < 0)
1495                 return 0;
1496
1497         /* NOTE: assumes write protect signal is active-high */
1498         return gpio_get_value(wp_gpio);
1499 }
1500 #endif
1501 #endif
1502
1503 #if CONFIG_IS_ENABLED(DM_MMC)
1504 static const struct dm_mmc_ops omap_hsmmc_ops = {
1505         .send_cmd       = omap_hsmmc_send_cmd,
1506         .set_ios        = omap_hsmmc_set_ios,
1507 #ifdef OMAP_HSMMC_USE_GPIO
1508         .get_cd         = omap_hsmmc_getcd,
1509         .get_wp         = omap_hsmmc_getwp,
1510 #endif
1511 #ifdef MMC_SUPPORTS_TUNING
1512         .execute_tuning = omap_hsmmc_execute_tuning,
1513 #endif
1514         .wait_dat0      = omap_hsmmc_wait_dat0,
1515 };
1516 #else
1517 static const struct mmc_ops omap_hsmmc_ops = {
1518         .send_cmd       = omap_hsmmc_send_cmd,
1519         .set_ios        = omap_hsmmc_set_ios,
1520         .init           = omap_hsmmc_init_setup,
1521 #ifdef OMAP_HSMMC_USE_GPIO
1522         .getcd          = omap_hsmmc_getcd,
1523         .getwp          = omap_hsmmc_getwp,
1524 #endif
1525 };
1526 #endif
1527
1528 #if !CONFIG_IS_ENABLED(DM_MMC)
1529 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1530                 int wp_gpio)
1531 {
1532         struct mmc *mmc;
1533         struct omap_hsmmc_data *priv;
1534         struct mmc_config *cfg;
1535         uint host_caps_val;
1536
1537         priv = calloc(1, sizeof(*priv));
1538         if (priv == NULL)
1539                 return -1;
1540
1541         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1542
1543         switch (dev_index) {
1544         case 0:
1545                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1546                 break;
1547 #ifdef OMAP_HSMMC2_BASE
1548         case 1:
1549                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1550 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1551         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1552         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1553                 defined(CONFIG_HSMMC2_8BIT)
1554                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1555                 host_caps_val |= MMC_MODE_8BIT;
1556 #endif
1557                 break;
1558 #endif
1559 #ifdef OMAP_HSMMC3_BASE
1560         case 2:
1561                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1562 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1563                 /* Enable 8-bit interface for eMMC on DRA7XX */
1564                 host_caps_val |= MMC_MODE_8BIT;
1565 #endif
1566                 break;
1567 #endif
1568         default:
1569                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1570                 return 1;
1571         }
1572 #ifdef OMAP_HSMMC_USE_GPIO
1573         /* on error gpio values are set to -1, which is what we want */
1574         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1575         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1576 #endif
1577
1578         cfg = &priv->cfg;
1579
1580         cfg->name = "OMAP SD/MMC";
1581         cfg->ops = &omap_hsmmc_ops;
1582
1583         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1584         cfg->host_caps = host_caps_val & ~host_caps_mask;
1585
1586         cfg->f_min = 400000;
1587
1588         if (f_max != 0)
1589                 cfg->f_max = f_max;
1590         else {
1591                 if (cfg->host_caps & MMC_MODE_HS) {
1592                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1593                                 cfg->f_max = 52000000;
1594                         else
1595                                 cfg->f_max = 26000000;
1596                 } else
1597                         cfg->f_max = 20000000;
1598         }
1599
1600         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1601
1602 #if defined(CONFIG_OMAP34XX)
1603         /*
1604          * Silicon revs 2.1 and older do not support multiblock transfers.
1605          */
1606         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1607                 cfg->b_max = 1;
1608 #endif
1609
1610         mmc = mmc_create(cfg, priv);
1611         if (mmc == NULL)
1612                 return -1;
1613
1614         return 0;
1615 }
1616 #else
1617
1618 #ifdef CONFIG_IODELAY_RECALIBRATION
1619 static struct pad_conf_entry *
1620 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1621 {
1622         int index = 0;
1623         struct pad_conf_entry *padconf;
1624
1625         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1626         if (!padconf) {
1627                 debug("failed to allocate memory\n");
1628                 return 0;
1629         }
1630
1631         while (index < count) {
1632                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1633                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1634                 index++;
1635         }
1636
1637         return padconf;
1638 }
1639
1640 static struct iodelay_cfg_entry *
1641 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1642 {
1643         int index = 0;
1644         struct iodelay_cfg_entry *iodelay;
1645
1646         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1647         if (!iodelay) {
1648                 debug("failed to allocate memory\n");
1649                 return 0;
1650         }
1651
1652         while (index < count) {
1653                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1654                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1655                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1656                 index++;
1657         }
1658
1659         return iodelay;
1660 }
1661
1662 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1663                                                    const char *name, int *len)
1664 {
1665         const void *fdt = gd->fdt_blob;
1666         int offset;
1667         const fdt32_t *pinctrl;
1668
1669         offset = fdt_node_offset_by_phandle(fdt, phandle);
1670         if (offset < 0) {
1671                 debug("failed to get pinctrl node %s.\n",
1672                       fdt_strerror(offset));
1673                 return 0;
1674         }
1675
1676         pinctrl = fdt_getprop(fdt, offset, name, len);
1677         if (!pinctrl) {
1678                 debug("failed to get property %s\n", name);
1679                 return 0;
1680         }
1681
1682         return pinctrl;
1683 }
1684
1685 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1686                                                 char *prop_name)
1687 {
1688         const void *fdt = gd->fdt_blob;
1689         const __be32 *phandle;
1690         int node = dev_of_offset(mmc->dev);
1691
1692         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1693         if (!phandle) {
1694                 debug("failed to get property %s\n", prop_name);
1695                 return 0;
1696         }
1697
1698         return fdt32_to_cpu(*phandle);
1699 }
1700
1701 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1702                                                char *prop_name)
1703 {
1704         const void *fdt = gd->fdt_blob;
1705         const __be32 *phandle;
1706         int len;
1707         int count;
1708         int node = dev_of_offset(mmc->dev);
1709
1710         phandle = fdt_getprop(fdt, node, prop_name, &len);
1711         if (!phandle) {
1712                 debug("failed to get property %s\n", prop_name);
1713                 return 0;
1714         }
1715
1716         /* No manual mode iodelay values if count < 2 */
1717         count = len / sizeof(*phandle);
1718         if (count < 2)
1719                 return 0;
1720
1721         return fdt32_to_cpu(*(phandle + 1));
1722 }
1723
1724 static struct pad_conf_entry *
1725 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1726 {
1727         int len;
1728         int count;
1729         struct pad_conf_entry *padconf;
1730         u32 phandle;
1731         const fdt32_t *pinctrl;
1732
1733         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1734         if (!phandle)
1735                 return ERR_PTR(-EINVAL);
1736
1737         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1738                                                &len);
1739         if (!pinctrl)
1740                 return ERR_PTR(-EINVAL);
1741
1742         count = (len / sizeof(*pinctrl)) / 2;
1743         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1744         if (!padconf)
1745                 return ERR_PTR(-EINVAL);
1746
1747         *npads = count;
1748
1749         return padconf;
1750 }
1751
1752 static struct iodelay_cfg_entry *
1753 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1754 {
1755         int len;
1756         int count;
1757         struct iodelay_cfg_entry *iodelay;
1758         u32 phandle;
1759         const fdt32_t *pinctrl;
1760
1761         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1762         /* Not all modes have manual mode iodelay values. So its not fatal */
1763         if (!phandle)
1764                 return 0;
1765
1766         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1767                                                &len);
1768         if (!pinctrl)
1769                 return ERR_PTR(-EINVAL);
1770
1771         count = (len / sizeof(*pinctrl)) / 3;
1772         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1773         if (!iodelay)
1774                 return ERR_PTR(-EINVAL);
1775
1776         *niodelay = count;
1777
1778         return iodelay;
1779 }
1780
1781 static struct omap_hsmmc_pinctrl_state *
1782 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1783 {
1784         int index;
1785         int npads = 0;
1786         int niodelays = 0;
1787         const void *fdt = gd->fdt_blob;
1788         int node = dev_of_offset(mmc->dev);
1789         char prop_name[11];
1790         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1791
1792         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1793                          malloc(sizeof(*pinctrl_state));
1794         if (!pinctrl_state) {
1795                 debug("failed to allocate memory\n");
1796                 return 0;
1797         }
1798
1799         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1800         if (index < 0) {
1801                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1802                 goto err_pinctrl_state;
1803         }
1804
1805         sprintf(prop_name, "pinctrl-%d", index);
1806
1807         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1808                                                          &npads);
1809         if (IS_ERR(pinctrl_state->padconf))
1810                 goto err_pinctrl_state;
1811         pinctrl_state->npads = npads;
1812
1813         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1814                                                         &niodelays);
1815         if (IS_ERR(pinctrl_state->iodelay))
1816                 goto err_padconf;
1817         pinctrl_state->niodelays = niodelays;
1818
1819         return pinctrl_state;
1820
1821 err_padconf:
1822         kfree(pinctrl_state->padconf);
1823
1824 err_pinctrl_state:
1825         kfree(pinctrl_state);
1826         return 0;
1827 }
1828
1829 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1830         do {                                                            \
1831                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1832                 char str[20];                                           \
1833                 if (!(cfg->host_caps & capmask))                        \
1834                         break;                                          \
1835                                                                         \
1836                 if (priv->hw_rev) {                                     \
1837                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1838                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1839                 }                                                       \
1840                                                                         \
1841                 if (!s)                                                 \
1842                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1843                                                                         \
1844                 if (!s && !optional) {                                  \
1845                         debug("%s: no pinctrl for %s\n",                \
1846                               mmc->dev->name, #mode);                   \
1847                         cfg->host_caps &= ~(capmask);                   \
1848                 } else {                                                \
1849                         priv->mode##_pinctrl_state = s;                 \
1850                 }                                                       \
1851         } while (0)
1852
1853 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1854 {
1855         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1856         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1857         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1858
1859         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1860                 return 0;
1861
1862         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1863         if (!default_pinctrl) {
1864                 printf("no pinctrl state for default mode\n");
1865                 return -EINVAL;
1866         }
1867
1868         priv->default_pinctrl_state = default_pinctrl;
1869
1870         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1871         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1872         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1873         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1874         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1875
1876         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1877         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1878         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1879
1880         return 0;
1881 }
1882 #endif
1883
1884 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1885 #ifdef CONFIG_OMAP54XX
1886 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1887 {
1888         return NULL;
1889 }
1890 #endif
1891
1892 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1893 {
1894         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1895         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1896
1897         struct mmc_config *cfg = &plat->cfg;
1898 #ifdef CONFIG_OMAP54XX
1899         const struct mmc_platform_fixups *fixups;
1900 #endif
1901         const void *fdt = gd->fdt_blob;
1902         int node = dev_of_offset(dev);
1903         int ret;
1904
1905         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1906                                       sizeof(struct hsmmc *),
1907                                       MAP_NOCACHE);
1908
1909         ret = mmc_of_parse(dev, cfg);
1910         if (ret < 0)
1911                 return ret;
1912
1913         if (!cfg->f_max)
1914                 cfg->f_max = 52000000;
1915         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1916         cfg->f_min = 400000;
1917         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1918         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1919         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1920                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1921         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1922                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1923         if (of_data)
1924                 plat->controller_flags |= of_data->controller_flags;
1925
1926 #ifdef CONFIG_OMAP54XX
1927         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1928         if (fixups) {
1929                 plat->hw_rev = fixups->hw_rev;
1930                 cfg->host_caps &= ~fixups->unsupported_caps;
1931                 cfg->f_max = fixups->max_freq;
1932         }
1933 #endif
1934
1935         return 0;
1936 }
1937 #endif
1938
1939 #ifdef CONFIG_BLK
1940
1941 static int omap_hsmmc_bind(struct udevice *dev)
1942 {
1943         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1944         plat->mmc = calloc(1, sizeof(struct mmc));
1945         return mmc_bind(dev, plat->mmc, &plat->cfg);
1946 }
1947 #endif
1948 static int omap_hsmmc_probe(struct udevice *dev)
1949 {
1950         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1951         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1952         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1953         struct mmc_config *cfg = &plat->cfg;
1954         struct mmc *mmc;
1955 #ifdef CONFIG_IODELAY_RECALIBRATION
1956         int ret;
1957 #endif
1958
1959         cfg->name = "OMAP SD/MMC";
1960         priv->base_addr = plat->base_addr;
1961         priv->controller_flags = plat->controller_flags;
1962         priv->hw_rev = plat->hw_rev;
1963
1964 #ifdef CONFIG_BLK
1965         mmc = plat->mmc;
1966 #else
1967         mmc = mmc_create(cfg, priv);
1968         if (mmc == NULL)
1969                 return -1;
1970 #endif
1971 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1972         device_get_supply_regulator(dev, "pbias-supply",
1973                                     &priv->pbias_supply);
1974 #endif
1975 #if defined(OMAP_HSMMC_USE_GPIO)
1976 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1977         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1978         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1979 #endif
1980 #endif
1981
1982         mmc->dev = dev;
1983         upriv->mmc = mmc;
1984
1985 #ifdef CONFIG_IODELAY_RECALIBRATION
1986         ret = omap_hsmmc_get_pinctrl_state(mmc);
1987         /*
1988          * disable high speed modes for the platforms that require IO delay
1989          * and for which we don't have this information
1990          */
1991         if ((ret < 0) &&
1992             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1993                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1994                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1995                                     UHS_CAPS);
1996         }
1997 #endif
1998
1999         return omap_hsmmc_init_setup(mmc);
2000 }
2001
2002 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2003
2004 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2005         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2006 };
2007
2008 static const struct udevice_id omap_hsmmc_ids[] = {
2009         { .compatible = "ti,omap3-hsmmc" },
2010         { .compatible = "ti,omap4-hsmmc" },
2011         { .compatible = "ti,am33xx-hsmmc" },
2012         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2013         { }
2014 };
2015 #endif
2016
2017 U_BOOT_DRIVER(omap_hsmmc) = {
2018         .name   = "omap_hsmmc",
2019         .id     = UCLASS_MMC,
2020 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2021         .of_match = omap_hsmmc_ids,
2022         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2023         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2024 #endif
2025 #ifdef CONFIG_BLK
2026         .bind = omap_hsmmc_bind,
2027 #endif
2028         .ops = &omap_hsmmc_ops,
2029         .probe  = omap_hsmmc_probe,
2030         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2031 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2032         .flags  = DM_FLAG_PRE_RELOC,
2033 #endif
2034 };
2035 #endif