3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #include <asm/arch/mmc_host_def.h>
36 #if !defined(CONFIG_SOC_KEYSTONE)
38 #include <asm/arch/sys_proto.h>
40 #ifdef CONFIG_MMC_OMAP36XX_PINS
41 #include <asm/arch/mux.h>
45 DECLARE_GLOBAL_DATA_PTR;
47 /* simplify defines to OMAP_HSMMC_USE_GPIO */
48 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
49 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
50 #define OMAP_HSMMC_USE_GPIO
52 #undef OMAP_HSMMC_USE_GPIO
55 /* common definitions for all OMAPs */
56 #define SYSCTL_SRC (1 << 25)
57 #define SYSCTL_SRD (1 << 26)
59 struct omap_hsmmc_data {
60 struct hsmmc *base_addr;
61 struct mmc_config cfg;
62 #ifdef OMAP_HSMMC_USE_GPIO
64 struct gpio_desc cd_gpio; /* Change Detect GPIO */
65 struct gpio_desc wp_gpio; /* Write Protect GPIO */
74 /* If we fail after 1 second wait, something is really bad */
75 #define MAX_RETRY_MS 1000
77 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
78 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
81 #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
82 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
86 #ifndef CONFIG_DM_GPIO
87 if (!gpio_is_valid(gpio))
90 ret = gpio_request(gpio, label);
94 ret = gpio_direction_input(gpio);
102 static unsigned char mmc_board_init(struct mmc *mmc)
104 #if defined(CONFIG_OMAP34XX)
105 t2_t *t2_base = (t2_t *)T2_BASE;
106 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
108 #ifdef CONFIG_MMC_OMAP36XX_PINS
109 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
112 pbias_lite = readl(&t2_base->pbias_lite);
113 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
114 #ifdef CONFIG_TARGET_OMAP3_CAIRO
115 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
116 pbias_lite &= ~PBIASLITEVMODE0;
118 #ifdef CONFIG_MMC_OMAP36XX_PINS
119 if (get_cpu_family() == CPU_OMAP36XX) {
120 /* Disable extended drain IO before changing PBIAS */
121 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
122 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
125 writel(pbias_lite, &t2_base->pbias_lite);
127 writel(pbias_lite | PBIASLITEPWRDNZ1 |
128 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
129 &t2_base->pbias_lite);
131 #ifdef CONFIG_MMC_OMAP36XX_PINS
132 if (get_cpu_family() == CPU_OMAP36XX)
133 /* Enable extended drain IO after changing PBIAS */
135 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
136 OMAP34XX_CTRL_WKUP_CTRL);
138 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
141 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
144 /* Change from default of 52MHz to 26MHz if necessary */
145 if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
146 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
147 &t2_base->ctl_prog_io1);
149 writel(readl(&prcm_base->fclken1_core) |
150 EN_MMC1 | EN_MMC2 | EN_MMC3,
151 &prcm_base->fclken1_core);
153 writel(readl(&prcm_base->iclken1_core) |
154 EN_MMC1 | EN_MMC2 | EN_MMC3,
155 &prcm_base->iclken1_core);
158 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
159 /* PBIAS config needed for MMC1 only */
160 if (mmc->block_dev.devnum == 0)
161 vmmc_pbias_config(LDO_VOLT_3V0);
167 void mmc_init_stream(struct hsmmc *mmc_base)
171 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
173 writel(MMC_CMD0, &mmc_base->cmd);
174 start = get_timer(0);
175 while (!(readl(&mmc_base->stat) & CC_MASK)) {
176 if (get_timer(0) - start > MAX_RETRY_MS) {
177 printf("%s: timedout waiting for cc!\n", __func__);
181 writel(CC_MASK, &mmc_base->stat)
183 writel(MMC_CMD0, &mmc_base->cmd)
185 start = get_timer(0);
186 while (!(readl(&mmc_base->stat) & CC_MASK)) {
187 if (get_timer(0) - start > MAX_RETRY_MS) {
188 printf("%s: timedout waiting for cc2!\n", __func__);
192 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
195 static int omap_hsmmc_init_setup(struct mmc *mmc)
197 struct hsmmc *mmc_base;
198 unsigned int reg_val;
202 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
205 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
206 &mmc_base->sysconfig);
207 start = get_timer(0);
208 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
209 if (get_timer(0) - start > MAX_RETRY_MS) {
210 printf("%s: timedout waiting for cc2!\n", __func__);
214 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
215 start = get_timer(0);
216 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
217 if (get_timer(0) - start > MAX_RETRY_MS) {
218 printf("%s: timedout waiting for softresetall!\n",
223 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
224 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
227 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
229 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
230 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
231 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
234 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
235 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
236 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
237 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
238 start = get_timer(0);
239 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
240 if (get_timer(0) - start > MAX_RETRY_MS) {
241 printf("%s: timedout waiting for ics!\n", __func__);
245 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
247 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
249 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
250 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
253 mmc_init_stream(mmc_base);
259 * MMC controller internal finite state machine reset
261 * Used to reset command or data internal state machines, using respectively
262 * SRC or SRD bit of SYSCTL register
264 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
268 mmc_reg_out(&mmc_base->sysctl, bit, bit);
271 * CMD(DAT) lines reset procedures are slightly different
272 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
273 * According to OMAP3 TRM:
274 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
276 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
277 * procedure steps must be as follows:
278 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
279 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
280 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
281 * 3. Wait until the SRC (SRD) bit returns to 0x0
282 * (reset procedure is completed).
284 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
285 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
286 if (!(readl(&mmc_base->sysctl) & bit)) {
287 start = get_timer(0);
288 while (!(readl(&mmc_base->sysctl) & bit)) {
289 if (get_timer(0) - start > MAX_RETRY_MS)
294 start = get_timer(0);
295 while ((readl(&mmc_base->sysctl) & bit) != 0) {
296 if (get_timer(0) - start > MAX_RETRY_MS) {
297 printf("%s: timedout waiting for sysctl %x to clear\n",
304 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
305 struct mmc_data *data)
307 struct hsmmc *mmc_base;
308 unsigned int flags, mmc_stat;
311 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
312 start = get_timer(0);
313 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
314 if (get_timer(0) - start > MAX_RETRY_MS) {
315 printf("%s: timedout waiting on cmd inhibit to clear\n",
320 writel(0xFFFFFFFF, &mmc_base->stat);
321 start = get_timer(0);
322 while (readl(&mmc_base->stat)) {
323 if (get_timer(0) - start > MAX_RETRY_MS) {
324 printf("%s: timedout waiting for STAT (%x) to clear\n",
325 __func__, readl(&mmc_base->stat));
331 * CMDIDX[13:8] : Command index
332 * DATAPRNT[5] : Data Present Select
333 * ENCMDIDX[4] : Command Index Check Enable
334 * ENCMDCRC[3] : Command CRC Check Enable
339 * 11 = Length 48 Check busy after response
341 /* Delay added before checking the status of frq change
342 * retry not supported by mmc.c(core file)
344 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
345 udelay(50000); /* wait 50 ms */
347 if (!(cmd->resp_type & MMC_RSP_PRESENT))
349 else if (cmd->resp_type & MMC_RSP_136)
350 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
351 else if (cmd->resp_type & MMC_RSP_BUSY)
352 flags = RSP_TYPE_LGHT48B;
354 flags = RSP_TYPE_LGHT48;
356 /* enable default flags */
357 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
358 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
360 if (cmd->resp_type & MMC_RSP_CRC)
362 if (cmd->resp_type & MMC_RSP_OPCODE)
366 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
367 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
368 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
369 data->blocksize = 512;
370 writel(data->blocksize | (data->blocks << 16),
373 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
375 if (data->flags & MMC_DATA_READ)
376 flags |= (DP_DATA | DDIR_READ);
378 flags |= (DP_DATA | DDIR_WRITE);
381 writel(cmd->cmdarg, &mmc_base->arg);
382 udelay(20); /* To fix "No status update" error on eMMC */
383 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
385 start = get_timer(0);
387 mmc_stat = readl(&mmc_base->stat);
388 if (get_timer(0) - start > MAX_RETRY_MS) {
389 printf("%s : timeout: No status update\n", __func__);
394 if ((mmc_stat & IE_CTO) != 0) {
395 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
397 } else if ((mmc_stat & ERRI_MASK) != 0)
400 if (mmc_stat & CC_MASK) {
401 writel(CC_MASK, &mmc_base->stat);
402 if (cmd->resp_type & MMC_RSP_PRESENT) {
403 if (cmd->resp_type & MMC_RSP_136) {
404 /* response type 2 */
405 cmd->response[3] = readl(&mmc_base->rsp10);
406 cmd->response[2] = readl(&mmc_base->rsp32);
407 cmd->response[1] = readl(&mmc_base->rsp54);
408 cmd->response[0] = readl(&mmc_base->rsp76);
410 /* response types 1, 1b, 3, 4, 5, 6 */
411 cmd->response[0] = readl(&mmc_base->rsp10);
415 if (data && (data->flags & MMC_DATA_READ)) {
416 mmc_read_data(mmc_base, data->dest,
417 data->blocksize * data->blocks);
418 } else if (data && (data->flags & MMC_DATA_WRITE)) {
419 mmc_write_data(mmc_base, data->src,
420 data->blocksize * data->blocks);
425 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
427 unsigned int *output_buf = (unsigned int *)buf;
428 unsigned int mmc_stat;
434 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
438 ulong start = get_timer(0);
440 mmc_stat = readl(&mmc_base->stat);
441 if (get_timer(0) - start > MAX_RETRY_MS) {
442 printf("%s: timedout waiting for status!\n",
446 } while (mmc_stat == 0);
448 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
449 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
451 if ((mmc_stat & ERRI_MASK) != 0)
454 if (mmc_stat & BRR_MASK) {
457 writel(readl(&mmc_base->stat) | BRR_MASK,
459 for (k = 0; k < count; k++) {
460 *output_buf = readl(&mmc_base->data);
466 if (mmc_stat & BWR_MASK)
467 writel(readl(&mmc_base->stat) | BWR_MASK,
470 if (mmc_stat & TC_MASK) {
471 writel(readl(&mmc_base->stat) | TC_MASK,
479 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
482 unsigned int *input_buf = (unsigned int *)buf;
483 unsigned int mmc_stat;
489 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
493 ulong start = get_timer(0);
495 mmc_stat = readl(&mmc_base->stat);
496 if (get_timer(0) - start > MAX_RETRY_MS) {
497 printf("%s: timedout waiting for status!\n",
501 } while (mmc_stat == 0);
503 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
504 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
506 if ((mmc_stat & ERRI_MASK) != 0)
509 if (mmc_stat & BWR_MASK) {
512 writel(readl(&mmc_base->stat) | BWR_MASK,
514 for (k = 0; k < count; k++) {
515 writel(*input_buf, &mmc_base->data);
521 if (mmc_stat & BRR_MASK)
522 writel(readl(&mmc_base->stat) | BRR_MASK,
525 if (mmc_stat & TC_MASK) {
526 writel(readl(&mmc_base->stat) | TC_MASK,
534 static int omap_hsmmc_set_ios(struct mmc *mmc)
536 struct hsmmc *mmc_base;
537 unsigned int dsor = 0;
540 mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
541 /* configue bus width */
542 switch (mmc->bus_width) {
544 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
549 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
551 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
557 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
559 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
564 /* configure clock with 96Mhz system clock.
566 if (mmc->clock != 0) {
567 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
568 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
572 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
573 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
575 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
576 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
578 start = get_timer(0);
579 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
580 if (get_timer(0) - start > MAX_RETRY_MS) {
581 printf("%s: timedout waiting for ics!\n", __func__);
585 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
590 #ifdef OMAP_HSMMC_USE_GPIO
592 static int omap_hsmmc_getcd(struct mmc *mmc)
594 struct omap_hsmmc_data *priv = mmc->priv;
597 value = dm_gpio_get_value(&priv->cd_gpio);
598 /* if no CD return as 1 */
602 if (priv->cd_inverted)
607 static int omap_hsmmc_getwp(struct mmc *mmc)
609 struct omap_hsmmc_data *priv = mmc->priv;
612 value = dm_gpio_get_value(&priv->wp_gpio);
613 /* if no WP return as 0 */
619 static int omap_hsmmc_getcd(struct mmc *mmc)
621 struct omap_hsmmc_data *priv_data = mmc->priv;
624 /* if no CD return as 1 */
625 cd_gpio = priv_data->cd_gpio;
629 /* NOTE: assumes card detect signal is active-low */
630 return !gpio_get_value(cd_gpio);
633 static int omap_hsmmc_getwp(struct mmc *mmc)
635 struct omap_hsmmc_data *priv_data = mmc->priv;
638 /* if no WP return as 0 */
639 wp_gpio = priv_data->wp_gpio;
643 /* NOTE: assumes write protect signal is active-high */
644 return gpio_get_value(wp_gpio);
649 static const struct mmc_ops omap_hsmmc_ops = {
650 .send_cmd = omap_hsmmc_send_cmd,
651 .set_ios = omap_hsmmc_set_ios,
652 .init = omap_hsmmc_init_setup,
653 #ifdef OMAP_HSMMC_USE_GPIO
654 .getcd = omap_hsmmc_getcd,
655 .getwp = omap_hsmmc_getwp,
659 #ifndef CONFIG_DM_MMC
660 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
664 struct omap_hsmmc_data *priv_data;
665 struct mmc_config *cfg;
668 priv_data = malloc(sizeof(*priv_data));
669 if (priv_data == NULL)
672 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
676 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
678 #ifdef OMAP_HSMMC2_BASE
680 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
681 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
682 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
683 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
684 defined(CONFIG_HSMMC2_8BIT)
685 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
686 host_caps_val |= MMC_MODE_8BIT;
690 #ifdef OMAP_HSMMC3_BASE
692 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
693 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
694 /* Enable 8-bit interface for eMMC on DRA7XX */
695 host_caps_val |= MMC_MODE_8BIT;
700 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
703 #ifdef OMAP_HSMMC_USE_GPIO
704 /* on error gpio values are set to -1, which is what we want */
705 priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
706 priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
709 cfg = &priv_data->cfg;
711 cfg->name = "OMAP SD/MMC";
712 cfg->ops = &omap_hsmmc_ops;
714 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
715 cfg->host_caps = host_caps_val & ~host_caps_mask;
722 if (cfg->host_caps & MMC_MODE_HS) {
723 if (cfg->host_caps & MMC_MODE_HS_52MHz)
724 cfg->f_max = 52000000;
726 cfg->f_max = 26000000;
728 cfg->f_max = 20000000;
731 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
733 #if defined(CONFIG_OMAP34XX)
735 * Silicon revs 2.1 and older do not support multiblock transfers.
737 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
740 mmc = mmc_create(cfg, priv_data);
747 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
749 struct omap_hsmmc_data *priv = dev_get_priv(dev);
750 const void *fdt = gd->fdt_blob;
751 int node = dev_of_offset(dev);
752 struct mmc_config *cfg;
755 priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *),
759 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
760 val = fdtdec_get_int(fdt, node, "bus-width", -1);
762 printf("error: bus-width property missing\n");
768 cfg->host_caps |= MMC_MODE_8BIT;
770 cfg->host_caps |= MMC_MODE_4BIT;
773 printf("error: invalid bus-width property\n");
778 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
779 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
780 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
782 #ifdef OMAP_HSMMC_USE_GPIO
783 priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
789 static int omap_hsmmc_probe(struct udevice *dev)
791 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
792 struct omap_hsmmc_data *priv = dev_get_priv(dev);
793 struct mmc_config *cfg;
797 cfg->name = "OMAP SD/MMC";
798 cfg->ops = &omap_hsmmc_ops;
800 mmc = mmc_create(cfg, priv);
804 #ifdef OMAP_HSMMC_USE_GPIO
805 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
806 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
815 static const struct udevice_id omap_hsmmc_ids[] = {
816 { .compatible = "ti,omap3-hsmmc" },
817 { .compatible = "ti,omap4-hsmmc" },
818 { .compatible = "ti,am33xx-hsmmc" },
822 U_BOOT_DRIVER(omap_hsmmc) = {
823 .name = "omap_hsmmc",
825 .of_match = omap_hsmmc_ids,
826 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
827 .probe = omap_hsmmc_probe,
828 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),