drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <mmc.h>
  29 #include <part.h>
  30 #include <i2c.h>
  31 #include <twl4030.h>
  32 #include <twl6030.h>
  33 #include <palmas.h>
  34 #include <asm/io.h>
  35 #include <asm/arch/mmc_host_def.h>
  36 #if !defined(CONFIG_SOC_KEYSTONE)
  37 #include <asm/gpio.h>
  38 #include <asm/arch/sys_proto.h>
  39 #endif
  40 #ifdef CONFIG_MMC_OMAP36XX_PINS
  41 #include <asm/arch/mux.h>
  42 #endif
  43 #include <dm.h>
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  48 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  49         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  50 #define OMAP_HSMMC_USE_GPIO
  51 #else
  52 #undef OMAP_HSMMC_USE_GPIO
  53 #endif
  54
  55 /* common definitions for all OMAPs */
  56 #define SYSCTL_SRC      (1 << 25)
  57 #define SYSCTL_SRD      (1 << 26)
  58
  59 struct omap_hsmmc_data {
  60         struct hsmmc *base_addr;
  61         struct mmc_config cfg;
  62 #ifdef OMAP_HSMMC_USE_GPIO
  63 #ifdef CONFIG_DM_MMC
  64         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  65         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  66         bool cd_inverted;
  67 #else
  68         int cd_gpio;
  69         int wp_gpio;
  70 #endif
  71 #endif
  72 };
  73
  74 /* If we fail after 1 second wait, something is really bad */
  75 #define MAX_RETRY_MS    1000
  76
  77 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  78 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  79                         unsigned int siz);
  80
  81 #if defined(OMAP_HSMMC_USE_GPIO) && !defined(CONFIG_DM_MMC)
  82 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
  83 {
  84         int ret;
  85
  86 #ifndef CONFIG_DM_GPIO
  87         if (!gpio_is_valid(gpio))
  88                 return -1;
  89 #endif
  90         ret = gpio_request(gpio, label);
  91         if (ret)
  92                 return ret;
  93
  94         ret = gpio_direction_input(gpio);
  95         if (ret)
  96                 return ret;
  97
  98         return gpio;
  99 }
 100 #endif
 101
 102 static unsigned char mmc_board_init(struct mmc *mmc)
 103 {
 104 #if defined(CONFIG_OMAP34XX)
 105         t2_t *t2_base = (t2_t *)T2_BASE;
 106         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 107         u32 pbias_lite;
 108 #ifdef CONFIG_MMC_OMAP36XX_PINS
 109         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 110 #endif
 111
 112         pbias_lite = readl(&t2_base->pbias_lite);
 113         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 114 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 115         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 116         pbias_lite &= ~PBIASLITEVMODE0;
 117 #endif
 118 #ifdef CONFIG_MMC_OMAP36XX_PINS
 119         if (get_cpu_family() == CPU_OMAP36XX) {
 120                 /* Disable extended drain IO before changing PBIAS */
 121                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 122                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 123         }
 124 #endif
 125         writel(pbias_lite, &t2_base->pbias_lite);
 126
 127         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 128                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 129                 &t2_base->pbias_lite);
 130
 131 #ifdef CONFIG_MMC_OMAP36XX_PINS
 132         if (get_cpu_family() == CPU_OMAP36XX)
 133                 /* Enable extended drain IO after changing PBIAS */
 134                 writel(wkup_ctrl |
 135                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 136                                 OMAP34XX_CTRL_WKUP_CTRL);
 137 #endif
 138         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 139                 &t2_base->devconf0);
 140
 141         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 142                 &t2_base->devconf1);
 143
 144         /* Change from default of 52MHz to 26MHz if necessary */
 145         if (!(mmc->cfg->host_caps & MMC_MODE_HS_52MHz))
 146                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 147                         &t2_base->ctl_prog_io1);
 148
 149         writel(readl(&prcm_base->fclken1_core) |
 150                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 151                 &prcm_base->fclken1_core);
 152
 153         writel(readl(&prcm_base->iclken1_core) |
 154                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 155                 &prcm_base->iclken1_core);
 156 #endif
 157
 158 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
 159         /* PBIAS config needed for MMC1 only */
 160         if (mmc->block_dev.devnum == 0)
 161                 vmmc_pbias_config(LDO_VOLT_3V0);
 162 #endif
 163
 164         return 0;
 165 }
 166
 167 void mmc_init_stream(struct hsmmc *mmc_base)
 168 {
 169         ulong start;
 170
 171         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 172
 173         writel(MMC_CMD0, &mmc_base->cmd);
 174         start = get_timer(0);
 175         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 176                 if (get_timer(0) - start > MAX_RETRY_MS) {
 177                         printf("%s: timedout waiting for cc!\n", __func__);
 178                         return;
 179                 }
 180         }
 181         writel(CC_MASK, &mmc_base->stat)
 182                 ;
 183         writel(MMC_CMD0, &mmc_base->cmd)
 184                 ;
 185         start = get_timer(0);
 186         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 187                 if (get_timer(0) - start > MAX_RETRY_MS) {
 188                         printf("%s: timedout waiting for cc2!\n", __func__);
 189                         return;
 190                 }
 191         }
 192         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 193 }
 194
 195 static int omap_hsmmc_init_setup(struct mmc *mmc)
 196 {
 197         struct hsmmc *mmc_base;
 198         unsigned int reg_val;
 199         unsigned int dsor;
 200         ulong start;
 201
 202         mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
 203         mmc_board_init(mmc);
 204
 205         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 206                 &mmc_base->sysconfig);
 207         start = get_timer(0);
 208         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 209                 if (get_timer(0) - start > MAX_RETRY_MS) {
 210                         printf("%s: timedout waiting for cc2!\n", __func__);
 211                         return -ETIMEDOUT;
 212                 }
 213         }
 214         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 215         start = get_timer(0);
 216         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 217                 if (get_timer(0) - start > MAX_RETRY_MS) {
 218                         printf("%s: timedout waiting for softresetall!\n",
 219                                 __func__);
 220                         return -ETIMEDOUT;
 221                 }
 222         }
 223         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 224         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 225                 &mmc_base->capa);
 226
 227         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 228
 229         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 230                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 231                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 232
 233         dsor = 240;
 234         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 235                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 236         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 237                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 238         start = get_timer(0);
 239         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 240                 if (get_timer(0) - start > MAX_RETRY_MS) {
 241                         printf("%s: timedout waiting for ics!\n", __func__);
 242                         return -ETIMEDOUT;
 243                 }
 244         }
 245         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 246
 247         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 248
 249         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 250                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 251                 &mmc_base->ie);
 252
 253         mmc_init_stream(mmc_base);
 254
 255         return 0;
 256 }
 257
 258 /*
 259  * MMC controller internal finite state machine reset
 260  *
 261  * Used to reset command or data internal state machines, using respectively
 262  * SRC or SRD bit of SYSCTL register
 263  */
 264 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 265 {
 266         ulong start;
 267
 268         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 269
 270         /*
 271          * CMD(DAT) lines reset procedures are slightly different
 272          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 273          * According to OMAP3 TRM:
 274          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 275          * returns to 0x0.
 276          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 277          * procedure steps must be as follows:
 278          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 279          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 280          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 281          * 3. Wait until the SRC (SRD) bit returns to 0x0
 282          *    (reset procedure is completed).
 283          */
 284 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 285         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 286         if (!(readl(&mmc_base->sysctl) & bit)) {
 287                 start = get_timer(0);
 288                 while (!(readl(&mmc_base->sysctl) & bit)) {
 289                         if (get_timer(0) - start > MAX_RETRY_MS)
 290                                 return;
 291                 }
 292         }
 293 #endif
 294         start = get_timer(0);
 295         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 296                 if (get_timer(0) - start > MAX_RETRY_MS) {
 297                         printf("%s: timedout waiting for sysctl %x to clear\n",
 298                                 __func__, bit);
 299                         return;
 300                 }
 301         }
 302 }
 303
 304 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 305                         struct mmc_data *data)
 306 {
 307         struct hsmmc *mmc_base;
 308         unsigned int flags, mmc_stat;
 309         ulong start;
 310
 311         mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
 312         start = get_timer(0);
 313         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 314                 if (get_timer(0) - start > MAX_RETRY_MS) {
 315                         printf("%s: timedout waiting on cmd inhibit to clear\n",
 316                                         __func__);
 317                         return -ETIMEDOUT;
 318                 }
 319         }
 320         writel(0xFFFFFFFF, &mmc_base->stat);
 321         start = get_timer(0);
 322         while (readl(&mmc_base->stat)) {
 323                 if (get_timer(0) - start > MAX_RETRY_MS) {
 324                         printf("%s: timedout waiting for STAT (%x) to clear\n",
 325                                 __func__, readl(&mmc_base->stat));
 326                         return -ETIMEDOUT;
 327                 }
 328         }
 329         /*
 330          * CMDREG
 331          * CMDIDX[13:8] : Command index
 332          * DATAPRNT[5]  : Data Present Select
 333          * ENCMDIDX[4]  : Command Index Check Enable
 334          * ENCMDCRC[3]  : Command CRC Check Enable
 335          * RSPTYP[1:0]
 336          *      00 = No Response
 337          *      01 = Length 136
 338          *      10 = Length 48
 339          *      11 = Length 48 Check busy after response
 340          */
 341         /* Delay added before checking the status of frq change
 342          * retry not supported by mmc.c(core file)
 343          */
 344         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 345                 udelay(50000); /* wait 50 ms */
 346
 347         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 348                 flags = 0;
 349         else if (cmd->resp_type & MMC_RSP_136)
 350                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 351         else if (cmd->resp_type & MMC_RSP_BUSY)
 352                 flags = RSP_TYPE_LGHT48B;
 353         else
 354                 flags = RSP_TYPE_LGHT48;
 355
 356         /* enable default flags */
 357         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 358                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 359
 360         if (cmd->resp_type & MMC_RSP_CRC)
 361                 flags |= CCCE_CHECK;
 362         if (cmd->resp_type & MMC_RSP_OPCODE)
 363                 flags |= CICE_CHECK;
 364
 365         if (data) {
 366                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 367                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 368                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 369                         data->blocksize = 512;
 370                         writel(data->blocksize | (data->blocks << 16),
 371                                                         &mmc_base->blk);
 372                 } else
 373                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 374
 375                 if (data->flags & MMC_DATA_READ)
 376                         flags |= (DP_DATA | DDIR_READ);
 377                 else
 378                         flags |= (DP_DATA | DDIR_WRITE);
 379         }
 380
 381         writel(cmd->cmdarg, &mmc_base->arg);
 382         udelay(20);             /* To fix "No status update" error on eMMC */
 383         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 384
 385         start = get_timer(0);
 386         do {
 387                 mmc_stat = readl(&mmc_base->stat);
 388                 if (get_timer(0) - start > MAX_RETRY_MS) {
 389                         printf("%s : timeout: No status update\n", __func__);
 390                         return -ETIMEDOUT;
 391                 }
 392         } while (!mmc_stat);
 393
 394         if ((mmc_stat & IE_CTO) != 0) {
 395                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 396                 return -ETIMEDOUT;
 397         } else if ((mmc_stat & ERRI_MASK) != 0)
 398                 return -1;
 399
 400         if (mmc_stat & CC_MASK) {
 401                 writel(CC_MASK, &mmc_base->stat);
 402                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 403                         if (cmd->resp_type & MMC_RSP_136) {
 404                                 /* response type 2 */
 405                                 cmd->response[3] = readl(&mmc_base->rsp10);
 406                                 cmd->response[2] = readl(&mmc_base->rsp32);
 407                                 cmd->response[1] = readl(&mmc_base->rsp54);
 408                                 cmd->response[0] = readl(&mmc_base->rsp76);
 409                         } else
 410                                 /* response types 1, 1b, 3, 4, 5, 6 */
 411                                 cmd->response[0] = readl(&mmc_base->rsp10);
 412                 }
 413         }
 414
 415         if (data && (data->flags & MMC_DATA_READ)) {
 416                 mmc_read_data(mmc_base, data->dest,
 417                                 data->blocksize * data->blocks);
 418         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 419                 mmc_write_data(mmc_base, data->src,
 420                                 data->blocksize * data->blocks);
 421         }
 422         return 0;
 423 }
 424
 425 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 426 {
 427         unsigned int *output_buf = (unsigned int *)buf;
 428         unsigned int mmc_stat;
 429         unsigned int count;
 430
 431         /*
 432          * Start Polled Read
 433          */
 434         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 435         count /= 4;
 436
 437         while (size) {
 438                 ulong start = get_timer(0);
 439                 do {
 440                         mmc_stat = readl(&mmc_base->stat);
 441                         if (get_timer(0) - start > MAX_RETRY_MS) {
 442                                 printf("%s: timedout waiting for status!\n",
 443                                                 __func__);
 444                                 return -ETIMEDOUT;
 445                         }
 446                 } while (mmc_stat == 0);
 447
 448                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 449                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 450
 451                 if ((mmc_stat & ERRI_MASK) != 0)
 452                         return 1;
 453
 454                 if (mmc_stat & BRR_MASK) {
 455                         unsigned int k;
 456
 457                         writel(readl(&mmc_base->stat) | BRR_MASK,
 458                                 &mmc_base->stat);
 459                         for (k = 0; k < count; k++) {
 460                                 *output_buf = readl(&mmc_base->data);
 461                                 output_buf++;
 462                         }
 463                         size -= (count*4);
 464                 }
 465
 466                 if (mmc_stat & BWR_MASK)
 467                         writel(readl(&mmc_base->stat) | BWR_MASK,
 468                                 &mmc_base->stat);
 469
 470                 if (mmc_stat & TC_MASK) {
 471                         writel(readl(&mmc_base->stat) | TC_MASK,
 472                                 &mmc_base->stat);
 473                         break;
 474                 }
 475         }
 476         return 0;
 477 }
 478
 479 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 480                                 unsigned int size)
 481 {
 482         unsigned int *input_buf = (unsigned int *)buf;
 483         unsigned int mmc_stat;
 484         unsigned int count;
 485
 486         /*
 487          * Start Polled Write
 488          */
 489         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 490         count /= 4;
 491
 492         while (size) {
 493                 ulong start = get_timer(0);
 494                 do {
 495                         mmc_stat = readl(&mmc_base->stat);
 496                         if (get_timer(0) - start > MAX_RETRY_MS) {
 497                                 printf("%s: timedout waiting for status!\n",
 498                                                 __func__);
 499                                 return -ETIMEDOUT;
 500                         }
 501                 } while (mmc_stat == 0);
 502
 503                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 504                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 505
 506                 if ((mmc_stat & ERRI_MASK) != 0)
 507                         return 1;
 508
 509                 if (mmc_stat & BWR_MASK) {
 510                         unsigned int k;
 511
 512                         writel(readl(&mmc_base->stat) | BWR_MASK,
 513                                         &mmc_base->stat);
 514                         for (k = 0; k < count; k++) {
 515                                 writel(*input_buf, &mmc_base->data);
 516                                 input_buf++;
 517                         }
 518                         size -= (count*4);
 519                 }
 520
 521                 if (mmc_stat & BRR_MASK)
 522                         writel(readl(&mmc_base->stat) | BRR_MASK,
 523                                 &mmc_base->stat);
 524
 525                 if (mmc_stat & TC_MASK) {
 526                         writel(readl(&mmc_base->stat) | TC_MASK,
 527                                 &mmc_base->stat);
 528                         break;
 529                 }
 530         }
 531         return 0;
 532 }
 533
 534 static int omap_hsmmc_set_ios(struct mmc *mmc)
 535 {
 536         struct hsmmc *mmc_base;
 537         unsigned int dsor = 0;
 538         ulong start;
 539
 540         mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
 541         /* configue bus width */
 542         switch (mmc->bus_width) {
 543         case 8:
 544                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 545                         &mmc_base->con);
 546                 break;
 547
 548         case 4:
 549                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 550                         &mmc_base->con);
 551                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 552                         &mmc_base->hctl);
 553                 break;
 554
 555         case 1:
 556         default:
 557                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 558                         &mmc_base->con);
 559                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 560                         &mmc_base->hctl);
 561                 break;
 562         }
 563
 564         /* configure clock with 96Mhz system clock.
 565          */
 566         if (mmc->clock != 0) {
 567                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 568                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 569                         dsor++;
 570         }
 571
 572         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 573                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 574
 575         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 576                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 577
 578         start = get_timer(0);
 579         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 580                 if (get_timer(0) - start > MAX_RETRY_MS) {
 581                         printf("%s: timedout waiting for ics!\n", __func__);
 582                         return -ETIMEDOUT;
 583                 }
 584         }
 585         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 586
 587         return 0;
 588 }
 589
 590 #ifdef OMAP_HSMMC_USE_GPIO
 591 #ifdef CONFIG_DM_MMC
 592 static int omap_hsmmc_getcd(struct mmc *mmc)
 593 {
 594         struct omap_hsmmc_data *priv = mmc->priv;
 595         int value;
 596
 597         value = dm_gpio_get_value(&priv->cd_gpio);
 598         /* if no CD return as 1 */
 599         if (value < 0)
 600                 return 1;
 601
 602         if (priv->cd_inverted)
 603                 return !value;
 604         return value;
 605 }
 606
 607 static int omap_hsmmc_getwp(struct mmc *mmc)
 608 {
 609         struct omap_hsmmc_data *priv = mmc->priv;
 610         int value;
 611
 612         value = dm_gpio_get_value(&priv->wp_gpio);
 613         /* if no WP return as 0 */
 614         if (value < 0)
 615                 return 0;
 616         return value;
 617 }
 618 #else
 619 static int omap_hsmmc_getcd(struct mmc *mmc)
 620 {
 621         struct omap_hsmmc_data *priv_data = mmc->priv;
 622         int cd_gpio;
 623
 624         /* if no CD return as 1 */
 625         cd_gpio = priv_data->cd_gpio;
 626         if (cd_gpio < 0)
 627                 return 1;
 628
 629         /* NOTE: assumes card detect signal is active-low */
 630         return !gpio_get_value(cd_gpio);
 631 }
 632
 633 static int omap_hsmmc_getwp(struct mmc *mmc)
 634 {
 635         struct omap_hsmmc_data *priv_data = mmc->priv;
 636         int wp_gpio;
 637
 638         /* if no WP return as 0 */
 639         wp_gpio = priv_data->wp_gpio;
 640         if (wp_gpio < 0)
 641                 return 0;
 642
 643         /* NOTE: assumes write protect signal is active-high */
 644         return gpio_get_value(wp_gpio);
 645 }
 646 #endif
 647 #endif
 648
 649 static const struct mmc_ops omap_hsmmc_ops = {
 650         .send_cmd       = omap_hsmmc_send_cmd,
 651         .set_ios        = omap_hsmmc_set_ios,
 652         .init           = omap_hsmmc_init_setup,
 653 #ifdef OMAP_HSMMC_USE_GPIO
 654         .getcd          = omap_hsmmc_getcd,
 655         .getwp          = omap_hsmmc_getwp,
 656 #endif
 657 };
 658
 659 #ifndef CONFIG_DM_MMC
 660 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 661                 int wp_gpio)
 662 {
 663         struct mmc *mmc;
 664         struct omap_hsmmc_data *priv_data;
 665         struct mmc_config *cfg;
 666         uint host_caps_val;
 667
 668         priv_data = malloc(sizeof(*priv_data));
 669         if (priv_data == NULL)
 670                 return -1;
 671
 672         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
 673
 674         switch (dev_index) {
 675         case 0:
 676                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 677                 break;
 678 #ifdef OMAP_HSMMC2_BASE
 679         case 1:
 680                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
 681 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 682         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
 683         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
 684                 defined(CONFIG_HSMMC2_8BIT)
 685                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
 686                 host_caps_val |= MMC_MODE_8BIT;
 687 #endif
 688                 break;
 689 #endif
 690 #ifdef OMAP_HSMMC3_BASE
 691         case 2:
 692                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
 693 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
 694                 /* Enable 8-bit interface for eMMC on DRA7XX */
 695                 host_caps_val |= MMC_MODE_8BIT;
 696 #endif
 697                 break;
 698 #endif
 699         default:
 700                 priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 701                 return 1;
 702         }
 703 #ifdef OMAP_HSMMC_USE_GPIO
 704         /* on error gpio values are set to -1, which is what we want */
 705         priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
 706         priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
 707 #endif
 708
 709         cfg = &priv_data->cfg;
 710
 711         cfg->name = "OMAP SD/MMC";
 712         cfg->ops = &omap_hsmmc_ops;
 713
 714         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 715         cfg->host_caps = host_caps_val & ~host_caps_mask;
 716
 717         cfg->f_min = 400000;
 718
 719         if (f_max != 0)
 720                 cfg->f_max = f_max;
 721         else {
 722                 if (cfg->host_caps & MMC_MODE_HS) {
 723                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
 724                                 cfg->f_max = 52000000;
 725                         else
 726                                 cfg->f_max = 26000000;
 727                 } else
 728                         cfg->f_max = 20000000;
 729         }
 730
 731         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 732
 733 #if defined(CONFIG_OMAP34XX)
 734         /*
 735          * Silicon revs 2.1 and older do not support multiblock transfers.
 736          */
 737         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 738                 cfg->b_max = 1;
 739 #endif
 740         mmc = mmc_create(cfg, priv_data);
 741         if (mmc == NULL)
 742                 return -1;
 743
 744         return 0;
 745 }
 746 #else
 747 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
 748 {
 749         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 750         const void *fdt = gd->fdt_blob;
 751         int node = dev_of_offset(dev);
 752         struct mmc_config *cfg;
 753         int val;
 754
 755         priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *),
 756                                       MAP_NOCACHE);
 757         cfg = &priv->cfg;
 758
 759         cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
 760         val = fdtdec_get_int(fdt, node, "bus-width", -1);
 761         if (val < 0) {
 762                 printf("error: bus-width property missing\n");
 763                 return -ENOENT;
 764         }
 765
 766         switch (val) {
 767         case 0x8:
 768                 cfg->host_caps |= MMC_MODE_8BIT;
 769         case 0x4:
 770                 cfg->host_caps |= MMC_MODE_4BIT;
 771                 break;
 772         default:
 773                 printf("error: invalid bus-width property\n");
 774                 return -ENOENT;
 775         }
 776
 777         cfg->f_min = 400000;
 778         cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
 779         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 780         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 781
 782 #ifdef OMAP_HSMMC_USE_GPIO
 783         priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
 784 #endif
 785
 786         return 0;
 787 }
 788
 789 static int omap_hsmmc_probe(struct udevice *dev)
 790 {
 791         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 792         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 793         struct mmc_config *cfg;
 794         struct mmc *mmc;
 795
 796         cfg = &priv->cfg;
 797         cfg->name = "OMAP SD/MMC";
 798         cfg->ops = &omap_hsmmc_ops;
 799
 800         mmc = mmc_create(cfg, priv);
 801         if (mmc == NULL)
 802                 return -1;
 803
 804 #ifdef OMAP_HSMMC_USE_GPIO
 805         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
 806         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
 807 #endif
 808
 809         mmc->dev = dev;
 810         upriv->mmc = mmc;
 811
 812         return 0;
 813 }
 814
 815 static const struct udevice_id omap_hsmmc_ids[] = {
 816         { .compatible = "ti,omap3-hsmmc" },
 817         { .compatible = "ti,omap4-hsmmc" },
 818         { .compatible = "ti,am33xx-hsmmc" },
 819         { }
 820 };
 821
 822 U_BOOT_DRIVER(omap_hsmmc) = {
 823         .name   = "omap_hsmmc",
 824         .id     = UCLASS_MMC,
 825         .of_match = omap_hsmmc_ids,
 826         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
 827         .probe  = omap_hsmmc_probe,
 828         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
 829 };
 830 #endif