3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
35 #include <asm/arch/mmc_host_def.h>
36 #if !defined(CONFIG_SOC_KEYSTONE)
38 #include <asm/arch/sys_proto.h>
40 #ifdef CONFIG_MMC_OMAP36XX_PINS
41 #include <asm/arch/mux.h>
45 DECLARE_GLOBAL_DATA_PTR;
47 /* simplify defines to OMAP_HSMMC_USE_GPIO */
48 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
49 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
50 #define OMAP_HSMMC_USE_GPIO
52 #undef OMAP_HSMMC_USE_GPIO
55 /* common definitions for all OMAPs */
56 #define SYSCTL_SRC (1 << 25)
57 #define SYSCTL_SRD (1 << 26)
59 struct omap2_mmc_platform_config {
63 struct omap_hsmmc_data {
64 struct hsmmc *base_addr;
65 #if !CONFIG_IS_ENABLED(DM_MMC)
66 struct mmc_config cfg;
68 #ifdef OMAP_HSMMC_USE_GPIO
69 #if CONFIG_IS_ENABLED(DM_MMC)
70 struct gpio_desc cd_gpio; /* Change Detect GPIO */
71 struct gpio_desc wp_gpio; /* Write Protect GPIO */
80 /* If we fail after 1 second wait, something is really bad */
81 #define MAX_RETRY_MS 1000
83 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
84 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
87 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
89 #if CONFIG_IS_ENABLED(DM_MMC)
90 return dev_get_priv(mmc->dev);
92 return (struct omap_hsmmc_data *)mmc->priv;
95 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
97 #if CONFIG_IS_ENABLED(DM_MMC)
98 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
101 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
105 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
106 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
110 #ifndef CONFIG_DM_GPIO
111 if (!gpio_is_valid(gpio))
114 ret = gpio_request(gpio, label);
118 ret = gpio_direction_input(gpio);
126 static unsigned char mmc_board_init(struct mmc *mmc)
128 #if defined(CONFIG_OMAP34XX)
129 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
130 t2_t *t2_base = (t2_t *)T2_BASE;
131 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
133 #ifdef CONFIG_MMC_OMAP36XX_PINS
134 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
137 pbias_lite = readl(&t2_base->pbias_lite);
138 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
139 #ifdef CONFIG_TARGET_OMAP3_CAIRO
140 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
141 pbias_lite &= ~PBIASLITEVMODE0;
143 #ifdef CONFIG_MMC_OMAP36XX_PINS
144 if (get_cpu_family() == CPU_OMAP36XX) {
145 /* Disable extended drain IO before changing PBIAS */
146 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
147 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
150 writel(pbias_lite, &t2_base->pbias_lite);
152 writel(pbias_lite | PBIASLITEPWRDNZ1 |
153 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
154 &t2_base->pbias_lite);
156 #ifdef CONFIG_MMC_OMAP36XX_PINS
157 if (get_cpu_family() == CPU_OMAP36XX)
158 /* Enable extended drain IO after changing PBIAS */
160 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
161 OMAP34XX_CTRL_WKUP_CTRL);
163 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
166 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
169 /* Change from default of 52MHz to 26MHz if necessary */
170 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
171 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
172 &t2_base->ctl_prog_io1);
174 writel(readl(&prcm_base->fclken1_core) |
175 EN_MMC1 | EN_MMC2 | EN_MMC3,
176 &prcm_base->fclken1_core);
178 writel(readl(&prcm_base->iclken1_core) |
179 EN_MMC1 | EN_MMC2 | EN_MMC3,
180 &prcm_base->iclken1_core);
183 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
184 /* PBIAS config needed for MMC1 only */
185 if (mmc_get_blk_desc(mmc)->devnum == 0)
186 vmmc_pbias_config(LDO_VOLT_3V0);
192 void mmc_init_stream(struct hsmmc *mmc_base)
196 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
198 writel(MMC_CMD0, &mmc_base->cmd);
199 start = get_timer(0);
200 while (!(readl(&mmc_base->stat) & CC_MASK)) {
201 if (get_timer(0) - start > MAX_RETRY_MS) {
202 printf("%s: timedout waiting for cc!\n", __func__);
206 writel(CC_MASK, &mmc_base->stat)
208 writel(MMC_CMD0, &mmc_base->cmd)
210 start = get_timer(0);
211 while (!(readl(&mmc_base->stat) & CC_MASK)) {
212 if (get_timer(0) - start > MAX_RETRY_MS) {
213 printf("%s: timedout waiting for cc2!\n", __func__);
217 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
220 static int omap_hsmmc_init_setup(struct mmc *mmc)
222 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
223 struct hsmmc *mmc_base;
224 unsigned int reg_val;
228 mmc_base = priv->base_addr;
231 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
232 &mmc_base->sysconfig);
233 start = get_timer(0);
234 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
235 if (get_timer(0) - start > MAX_RETRY_MS) {
236 printf("%s: timedout waiting for cc2!\n", __func__);
240 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
241 start = get_timer(0);
242 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
243 if (get_timer(0) - start > MAX_RETRY_MS) {
244 printf("%s: timedout waiting for softresetall!\n",
249 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
250 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
253 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
255 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
256 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
257 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
260 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
261 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
262 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
263 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
264 start = get_timer(0);
265 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
266 if (get_timer(0) - start > MAX_RETRY_MS) {
267 printf("%s: timedout waiting for ics!\n", __func__);
271 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
273 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
275 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
276 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
279 mmc_init_stream(mmc_base);
285 * MMC controller internal finite state machine reset
287 * Used to reset command or data internal state machines, using respectively
288 * SRC or SRD bit of SYSCTL register
290 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
294 mmc_reg_out(&mmc_base->sysctl, bit, bit);
297 * CMD(DAT) lines reset procedures are slightly different
298 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
299 * According to OMAP3 TRM:
300 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
302 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
303 * procedure steps must be as follows:
304 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
305 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
306 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
307 * 3. Wait until the SRC (SRD) bit returns to 0x0
308 * (reset procedure is completed).
310 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
311 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
312 if (!(readl(&mmc_base->sysctl) & bit)) {
313 start = get_timer(0);
314 while (!(readl(&mmc_base->sysctl) & bit)) {
315 if (get_timer(0) - start > MAX_RETRY_MS)
320 start = get_timer(0);
321 while ((readl(&mmc_base->sysctl) & bit) != 0) {
322 if (get_timer(0) - start > MAX_RETRY_MS) {
323 printf("%s: timedout waiting for sysctl %x to clear\n",
329 #if !CONFIG_IS_ENABLED(DM_MMC)
330 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
331 struct mmc_data *data)
333 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
335 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
336 struct mmc_data *data)
338 struct omap_hsmmc_data *priv = dev_get_priv(dev);
340 struct hsmmc *mmc_base;
341 unsigned int flags, mmc_stat;
344 mmc_base = priv->base_addr;
345 start = get_timer(0);
346 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
347 if (get_timer(0) - start > MAX_RETRY_MS) {
348 printf("%s: timedout waiting on cmd inhibit to clear\n",
353 writel(0xFFFFFFFF, &mmc_base->stat);
354 start = get_timer(0);
355 while (readl(&mmc_base->stat)) {
356 if (get_timer(0) - start > MAX_RETRY_MS) {
357 printf("%s: timedout waiting for STAT (%x) to clear\n",
358 __func__, readl(&mmc_base->stat));
364 * CMDIDX[13:8] : Command index
365 * DATAPRNT[5] : Data Present Select
366 * ENCMDIDX[4] : Command Index Check Enable
367 * ENCMDCRC[3] : Command CRC Check Enable
372 * 11 = Length 48 Check busy after response
374 /* Delay added before checking the status of frq change
375 * retry not supported by mmc.c(core file)
377 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
378 udelay(50000); /* wait 50 ms */
380 if (!(cmd->resp_type & MMC_RSP_PRESENT))
382 else if (cmd->resp_type & MMC_RSP_136)
383 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
384 else if (cmd->resp_type & MMC_RSP_BUSY)
385 flags = RSP_TYPE_LGHT48B;
387 flags = RSP_TYPE_LGHT48;
389 /* enable default flags */
390 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
391 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
393 if (cmd->resp_type & MMC_RSP_CRC)
395 if (cmd->resp_type & MMC_RSP_OPCODE)
399 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
400 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
401 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
402 data->blocksize = 512;
403 writel(data->blocksize | (data->blocks << 16),
406 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
408 if (data->flags & MMC_DATA_READ)
409 flags |= (DP_DATA | DDIR_READ);
411 flags |= (DP_DATA | DDIR_WRITE);
414 writel(cmd->cmdarg, &mmc_base->arg);
415 udelay(20); /* To fix "No status update" error on eMMC */
416 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
418 start = get_timer(0);
420 mmc_stat = readl(&mmc_base->stat);
421 if (get_timer(0) - start > MAX_RETRY_MS) {
422 printf("%s : timeout: No status update\n", __func__);
427 if ((mmc_stat & IE_CTO) != 0) {
428 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
430 } else if ((mmc_stat & ERRI_MASK) != 0)
433 if (mmc_stat & CC_MASK) {
434 writel(CC_MASK, &mmc_base->stat);
435 if (cmd->resp_type & MMC_RSP_PRESENT) {
436 if (cmd->resp_type & MMC_RSP_136) {
437 /* response type 2 */
438 cmd->response[3] = readl(&mmc_base->rsp10);
439 cmd->response[2] = readl(&mmc_base->rsp32);
440 cmd->response[1] = readl(&mmc_base->rsp54);
441 cmd->response[0] = readl(&mmc_base->rsp76);
443 /* response types 1, 1b, 3, 4, 5, 6 */
444 cmd->response[0] = readl(&mmc_base->rsp10);
448 if (data && (data->flags & MMC_DATA_READ)) {
449 mmc_read_data(mmc_base, data->dest,
450 data->blocksize * data->blocks);
451 } else if (data && (data->flags & MMC_DATA_WRITE)) {
452 mmc_write_data(mmc_base, data->src,
453 data->blocksize * data->blocks);
458 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
460 unsigned int *output_buf = (unsigned int *)buf;
461 unsigned int mmc_stat;
467 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
471 ulong start = get_timer(0);
473 mmc_stat = readl(&mmc_base->stat);
474 if (get_timer(0) - start > MAX_RETRY_MS) {
475 printf("%s: timedout waiting for status!\n",
479 } while (mmc_stat == 0);
481 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
482 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
484 if ((mmc_stat & ERRI_MASK) != 0)
487 if (mmc_stat & BRR_MASK) {
490 writel(readl(&mmc_base->stat) | BRR_MASK,
492 for (k = 0; k < count; k++) {
493 *output_buf = readl(&mmc_base->data);
499 if (mmc_stat & BWR_MASK)
500 writel(readl(&mmc_base->stat) | BWR_MASK,
503 if (mmc_stat & TC_MASK) {
504 writel(readl(&mmc_base->stat) | TC_MASK,
512 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
515 unsigned int *input_buf = (unsigned int *)buf;
516 unsigned int mmc_stat;
522 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
526 ulong start = get_timer(0);
528 mmc_stat = readl(&mmc_base->stat);
529 if (get_timer(0) - start > MAX_RETRY_MS) {
530 printf("%s: timedout waiting for status!\n",
534 } while (mmc_stat == 0);
536 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
537 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
539 if ((mmc_stat & ERRI_MASK) != 0)
542 if (mmc_stat & BWR_MASK) {
545 writel(readl(&mmc_base->stat) | BWR_MASK,
547 for (k = 0; k < count; k++) {
548 writel(*input_buf, &mmc_base->data);
554 if (mmc_stat & BRR_MASK)
555 writel(readl(&mmc_base->stat) | BRR_MASK,
558 if (mmc_stat & TC_MASK) {
559 writel(readl(&mmc_base->stat) | TC_MASK,
567 #if !CONFIG_IS_ENABLED(DM_MMC)
568 static int omap_hsmmc_set_ios(struct mmc *mmc)
570 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
572 static int omap_hsmmc_set_ios(struct udevice *dev)
574 struct omap_hsmmc_data *priv = dev_get_priv(dev);
575 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
576 struct mmc *mmc = upriv->mmc;
578 struct hsmmc *mmc_base;
579 unsigned int dsor = 0;
582 mmc_base = priv->base_addr;
583 /* configue bus width */
584 switch (mmc->bus_width) {
586 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
591 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
593 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
599 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
601 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
606 /* configure clock with 96Mhz system clock.
608 if (mmc->clock != 0) {
609 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
610 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
614 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
615 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
617 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
618 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
620 start = get_timer(0);
621 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
622 if (get_timer(0) - start > MAX_RETRY_MS) {
623 printf("%s: timedout waiting for ics!\n", __func__);
627 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
632 #ifdef OMAP_HSMMC_USE_GPIO
633 #if CONFIG_IS_ENABLED(DM_MMC)
634 static int omap_hsmmc_getcd(struct udevice *dev)
636 struct omap_hsmmc_data *priv = dev_get_priv(dev);
639 value = dm_gpio_get_value(&priv->cd_gpio);
640 /* if no CD return as 1 */
644 if (priv->cd_inverted)
649 static int omap_hsmmc_getwp(struct udevice *dev)
651 struct omap_hsmmc_data *priv = dev_get_priv(dev);
654 value = dm_gpio_get_value(&priv->wp_gpio);
655 /* if no WP return as 0 */
661 static int omap_hsmmc_getcd(struct mmc *mmc)
663 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
666 /* if no CD return as 1 */
667 cd_gpio = priv->cd_gpio;
671 /* NOTE: assumes card detect signal is active-low */
672 return !gpio_get_value(cd_gpio);
675 static int omap_hsmmc_getwp(struct mmc *mmc)
677 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
680 /* if no WP return as 0 */
681 wp_gpio = priv->wp_gpio;
685 /* NOTE: assumes write protect signal is active-high */
686 return gpio_get_value(wp_gpio);
691 #if CONFIG_IS_ENABLED(DM_MMC)
692 static const struct dm_mmc_ops omap_hsmmc_ops = {
693 .send_cmd = omap_hsmmc_send_cmd,
694 .set_ios = omap_hsmmc_set_ios,
695 #ifdef OMAP_HSMMC_USE_GPIO
696 .get_cd = omap_hsmmc_getcd,
697 .get_wp = omap_hsmmc_getwp,
701 static const struct mmc_ops omap_hsmmc_ops = {
702 .send_cmd = omap_hsmmc_send_cmd,
703 .set_ios = omap_hsmmc_set_ios,
704 .init = omap_hsmmc_init_setup,
705 #ifdef OMAP_HSMMC_USE_GPIO
706 .getcd = omap_hsmmc_getcd,
707 .getwp = omap_hsmmc_getwp,
712 #if !CONFIG_IS_ENABLED(DM_MMC)
713 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
717 struct omap_hsmmc_data *priv;
718 struct mmc_config *cfg;
721 priv = malloc(sizeof(*priv));
725 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
729 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
731 #ifdef OMAP_HSMMC2_BASE
733 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
734 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
735 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
736 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
737 defined(CONFIG_HSMMC2_8BIT)
738 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
739 host_caps_val |= MMC_MODE_8BIT;
743 #ifdef OMAP_HSMMC3_BASE
745 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
746 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
747 /* Enable 8-bit interface for eMMC on DRA7XX */
748 host_caps_val |= MMC_MODE_8BIT;
753 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
756 #ifdef OMAP_HSMMC_USE_GPIO
757 /* on error gpio values are set to -1, which is what we want */
758 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
759 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
764 cfg->name = "OMAP SD/MMC";
765 cfg->ops = &omap_hsmmc_ops;
767 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
768 cfg->host_caps = host_caps_val & ~host_caps_mask;
775 if (cfg->host_caps & MMC_MODE_HS) {
776 if (cfg->host_caps & MMC_MODE_HS_52MHz)
777 cfg->f_max = 52000000;
779 cfg->f_max = 26000000;
781 cfg->f_max = 20000000;
784 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
786 #if defined(CONFIG_OMAP34XX)
788 * Silicon revs 2.1 and older do not support multiblock transfers.
790 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
793 mmc = mmc_create(cfg, priv);
800 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
801 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
803 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
804 struct mmc_config *cfg = &plat->cfg;
805 struct omap2_mmc_platform_config *data =
806 (struct omap2_mmc_platform_config *)dev_get_driver_data(dev);
807 const void *fdt = gd->fdt_blob;
808 int node = dev_of_offset(dev);
811 plat->base_addr = map_physmem(devfdt_get_addr(dev),
812 sizeof(struct hsmmc *),
813 MAP_NOCACHE) + data->reg_offset;
815 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
816 val = fdtdec_get_int(fdt, node, "bus-width", -1);
818 printf("error: bus-width property missing\n");
824 cfg->host_caps |= MMC_MODE_8BIT;
826 cfg->host_caps |= MMC_MODE_4BIT;
829 printf("error: invalid bus-width property\n");
834 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
835 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
836 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
838 #ifdef OMAP_HSMMC_USE_GPIO
839 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
848 static int omap_hsmmc_bind(struct udevice *dev)
850 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
852 return mmc_bind(dev, &plat->mmc, &plat->cfg);
855 static int omap_hsmmc_probe(struct udevice *dev)
857 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
858 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
859 struct omap_hsmmc_data *priv = dev_get_priv(dev);
860 struct mmc_config *cfg = &plat->cfg;
863 cfg->name = "OMAP SD/MMC";
864 priv->base_addr = plat->base_addr;
865 #ifdef OMAP_HSMMC_USE_GPIO
866 priv->cd_inverted = plat->cd_inverted;
872 mmc = mmc_create(cfg, priv);
877 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
878 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
879 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
885 return omap_hsmmc_init_setup(mmc);
888 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
889 static const struct omap2_mmc_platform_config omap3_mmc_pdata = {
893 static const struct omap2_mmc_platform_config am33xx_mmc_pdata = {
897 static const struct omap2_mmc_platform_config omap4_mmc_pdata = {
901 static const struct udevice_id omap_hsmmc_ids[] = {
903 .compatible = "ti,omap3-hsmmc",
904 .data = (ulong)&omap3_mmc_pdata
907 .compatible = "ti,omap4-hsmmc",
908 .data = (ulong)&omap4_mmc_pdata
911 .compatible = "ti,am33xx-hsmmc",
912 .data = (ulong)&am33xx_mmc_pdata
918 U_BOOT_DRIVER(omap_hsmmc) = {
919 .name = "omap_hsmmc",
921 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
922 .of_match = omap_hsmmc_ids,
923 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
924 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
927 .bind = omap_hsmmc_bind,
929 .ops = &omap_hsmmc_ops,
930 .probe = omap_hsmmc_probe,
931 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
932 .flags = DM_FLAG_PRE_RELOC,