3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/mmc_host_def.h>
34 #include <asm/arch/sys_proto.h>
36 /* If we fail after 1 second wait, something is really bad */
37 #define MAX_RETRY_MS 1000
39 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
40 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
42 static struct mmc hsmmc_dev[2];
44 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
45 static void omap4_vmmc_pbias_config(struct mmc *mmc)
48 struct omap4_sys_ctrl_regs *const ctrl =
49 (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
52 value = readl(&ctrl->control_pbiaslite);
53 value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
54 writel(value, &ctrl->control_pbiaslite);
56 twl6030_power_mmc_init();
57 value = readl(&ctrl->control_pbiaslite);
58 value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
59 writel(value, &ctrl->control_pbiaslite);
63 unsigned char mmc_board_init(struct mmc *mmc)
65 #if defined(CONFIG_TWL4030_POWER)
66 twl4030_power_mmc_init();
69 #if defined(CONFIG_OMAP34XX)
70 t2_t *t2_base = (t2_t *)T2_BASE;
71 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
73 writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
74 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
75 &t2_base->pbias_lite);
77 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
80 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
83 writel(readl(&prcm_base->fclken1_core) |
84 EN_MMC1 | EN_MMC2 | EN_MMC3,
85 &prcm_base->fclken1_core);
87 writel(readl(&prcm_base->iclken1_core) |
88 EN_MMC1 | EN_MMC2 | EN_MMC3,
89 &prcm_base->iclken1_core);
92 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
93 /* PBIAS config needed for MMC1 only */
94 if (mmc->block_dev.dev == 0)
95 omap4_vmmc_pbias_config(mmc);
101 void mmc_init_stream(struct hsmmc *mmc_base)
105 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
107 writel(MMC_CMD0, &mmc_base->cmd);
108 start = get_timer(0);
109 while (!(readl(&mmc_base->stat) & CC_MASK)) {
110 if (get_timer(0) - start > MAX_RETRY_MS) {
111 printf("%s: timedout waiting for cc!\n", __func__);
115 writel(CC_MASK, &mmc_base->stat)
117 writel(MMC_CMD0, &mmc_base->cmd)
119 start = get_timer(0);
120 while (!(readl(&mmc_base->stat) & CC_MASK)) {
121 if (get_timer(0) - start > MAX_RETRY_MS) {
122 printf("%s: timedout waiting for cc2!\n", __func__);
126 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
130 static int mmc_init_setup(struct mmc *mmc)
132 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
133 unsigned int reg_val;
139 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
140 &mmc_base->sysconfig);
141 start = get_timer(0);
142 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
143 if (get_timer(0) - start > MAX_RETRY_MS) {
144 printf("%s: timedout waiting for cc2!\n", __func__);
148 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
149 start = get_timer(0);
150 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
151 if (get_timer(0) - start > MAX_RETRY_MS) {
152 printf("%s: timedout waiting for softresetall!\n",
157 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
158 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
161 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
163 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
164 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
165 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
168 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
169 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
170 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
171 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
172 start = get_timer(0);
173 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
174 if (get_timer(0) - start > MAX_RETRY_MS) {
175 printf("%s: timedout waiting for ics!\n", __func__);
179 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
181 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
183 writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
184 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
187 mmc_init_stream(mmc_base);
193 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
194 struct mmc_data *data)
196 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
197 unsigned int flags, mmc_stat;
200 start = get_timer(0);
201 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
202 if (get_timer(0) - start > MAX_RETRY_MS) {
203 printf("%s: timedout waiting on cmd inhibit to clear\n",
208 writel(0xFFFFFFFF, &mmc_base->stat);
209 start = get_timer(0);
210 while (readl(&mmc_base->stat)) {
211 if (get_timer(0) - start > MAX_RETRY_MS) {
212 printf("%s: timedout waiting for stat!\n", __func__);
218 * CMDIDX[13:8] : Command index
219 * DATAPRNT[5] : Data Present Select
220 * ENCMDIDX[4] : Command Index Check Enable
221 * ENCMDCRC[3] : Command CRC Check Enable
226 * 11 = Length 48 Check busy after response
228 /* Delay added before checking the status of frq change
229 * retry not supported by mmc.c(core file)
231 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
232 udelay(50000); /* wait 50 ms */
234 if (!(cmd->resp_type & MMC_RSP_PRESENT))
236 else if (cmd->resp_type & MMC_RSP_136)
237 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
238 else if (cmd->resp_type & MMC_RSP_BUSY)
239 flags = RSP_TYPE_LGHT48B;
241 flags = RSP_TYPE_LGHT48;
243 /* enable default flags */
244 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
245 MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
247 if (cmd->resp_type & MMC_RSP_CRC)
249 if (cmd->resp_type & MMC_RSP_OPCODE)
253 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
254 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
255 flags |= (MSBS_MULTIBLK | BCE_ENABLE);
256 data->blocksize = 512;
257 writel(data->blocksize | (data->blocks << 16),
260 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
262 if (data->flags & MMC_DATA_READ)
263 flags |= (DP_DATA | DDIR_READ);
265 flags |= (DP_DATA | DDIR_WRITE);
268 writel(cmd->cmdarg, &mmc_base->arg);
269 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
271 start = get_timer(0);
273 mmc_stat = readl(&mmc_base->stat);
274 if (get_timer(0) - start > MAX_RETRY_MS) {
275 printf("%s : timeout: No status update\n", __func__);
280 if ((mmc_stat & IE_CTO) != 0)
282 else if ((mmc_stat & ERRI_MASK) != 0)
285 if (mmc_stat & CC_MASK) {
286 writel(CC_MASK, &mmc_base->stat);
287 if (cmd->resp_type & MMC_RSP_PRESENT) {
288 if (cmd->resp_type & MMC_RSP_136) {
289 /* response type 2 */
290 cmd->response[3] = readl(&mmc_base->rsp10);
291 cmd->response[2] = readl(&mmc_base->rsp32);
292 cmd->response[1] = readl(&mmc_base->rsp54);
293 cmd->response[0] = readl(&mmc_base->rsp76);
295 /* response types 1, 1b, 3, 4, 5, 6 */
296 cmd->response[0] = readl(&mmc_base->rsp10);
300 if (data && (data->flags & MMC_DATA_READ)) {
301 mmc_read_data(mmc_base, data->dest,
302 data->blocksize * data->blocks);
303 } else if (data && (data->flags & MMC_DATA_WRITE)) {
304 mmc_write_data(mmc_base, data->src,
305 data->blocksize * data->blocks);
310 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
312 unsigned int *output_buf = (unsigned int *)buf;
313 unsigned int mmc_stat;
319 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
323 ulong start = get_timer(0);
325 mmc_stat = readl(&mmc_base->stat);
326 if (get_timer(0) - start > MAX_RETRY_MS) {
327 printf("%s: timedout waiting for status!\n",
331 } while (mmc_stat == 0);
333 if ((mmc_stat & ERRI_MASK) != 0)
336 if (mmc_stat & BRR_MASK) {
339 writel(readl(&mmc_base->stat) | BRR_MASK,
341 for (k = 0; k < count; k++) {
342 *output_buf = readl(&mmc_base->data);
348 if (mmc_stat & BWR_MASK)
349 writel(readl(&mmc_base->stat) | BWR_MASK,
352 if (mmc_stat & TC_MASK) {
353 writel(readl(&mmc_base->stat) | TC_MASK,
361 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
364 unsigned int *input_buf = (unsigned int *)buf;
365 unsigned int mmc_stat;
371 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
375 ulong start = get_timer(0);
377 mmc_stat = readl(&mmc_base->stat);
378 if (get_timer(0) - start > MAX_RETRY_MS) {
379 printf("%s: timedout waiting for status!\n",
383 } while (mmc_stat == 0);
385 if ((mmc_stat & ERRI_MASK) != 0)
388 if (mmc_stat & BWR_MASK) {
391 writel(readl(&mmc_base->stat) | BWR_MASK,
393 for (k = 0; k < count; k++) {
394 writel(*input_buf, &mmc_base->data);
400 if (mmc_stat & BRR_MASK)
401 writel(readl(&mmc_base->stat) | BRR_MASK,
404 if (mmc_stat & TC_MASK) {
405 writel(readl(&mmc_base->stat) | TC_MASK,
413 static void mmc_set_ios(struct mmc *mmc)
415 struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
416 unsigned int dsor = 0;
419 /* configue bus width */
420 switch (mmc->bus_width) {
422 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
427 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
429 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
435 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
437 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
442 /* configure clock with 96Mhz system clock.
444 if (mmc->clock != 0) {
445 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
446 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
450 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
451 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
453 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
454 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
456 start = get_timer(0);
457 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
458 if (get_timer(0) - start > MAX_RETRY_MS) {
459 printf("%s: timedout waiting for ics!\n", __func__);
463 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
466 int omap_mmc_init(int dev_index)
470 mmc = &hsmmc_dev[dev_index];
472 sprintf(mmc->name, "OMAP SD/MMC");
473 mmc->send_cmd = mmc_send_cmd;
474 mmc->set_ios = mmc_set_ios;
475 mmc->init = mmc_init_setup;
480 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
482 #ifdef OMAP_HSMMC2_BASE
484 mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
487 #ifdef OMAP_HSMMC3_BASE
489 mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
493 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
496 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
497 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
501 mmc->f_max = 52000000;
505 #if defined(CONFIG_OMAP34XX)
507 * Silicon revs 2.1 and older do not support multiblock transfers.
509 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))