drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <memalign.h>
  29 #include <mmc.h>
  30 #include <part.h>
  31 #include <i2c.h>
  32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  33 #include <palmas.h>
  34 #endif
  35 #include <asm/io.h>
  36 #include <asm/arch/mmc_host_def.h>
  37 #ifdef CONFIG_OMAP54XX
  38 #include <asm/arch/mux_dra7xx.h>
  39 #include <asm/arch/dra7xx_iodelay.h>
  40 #endif
  41 #if !defined(CONFIG_SOC_KEYSTONE)
  42 #include <asm/gpio.h>
  43 #include <asm/arch/sys_proto.h>
  44 #endif
  45 #ifdef CONFIG_MMC_OMAP36XX_PINS
  46 #include <asm/arch/mux.h>
  47 #endif
  48 #include <dm.h>
  49 #include <power/regulator.h>
  50 #include <thermal.h>
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 /* simplify defines to OMAP_HSMMC_USE_GPIO */
  55 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  56         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  57 #define OMAP_HSMMC_USE_GPIO
  58 #else
  59 #undef OMAP_HSMMC_USE_GPIO
  60 #endif
  61
  62 /* common definitions for all OMAPs */
  63 #define SYSCTL_SRC      (1 << 25)
  64 #define SYSCTL_SRD      (1 << 26)
  65
  66 #ifdef CONFIG_IODELAY_RECALIBRATION
  67 struct omap_hsmmc_pinctrl_state {
  68         struct pad_conf_entry *padconf;
  69         int npads;
  70         struct iodelay_cfg_entry *iodelay;
  71         int niodelays;
  72 };
  73 #endif
  74
  75 struct omap_hsmmc_data {
  76         struct hsmmc *base_addr;
  77 #if !CONFIG_IS_ENABLED(DM_MMC)
  78         struct mmc_config cfg;
  79 #endif
  80         uint bus_width;
  81         uint clock;
  82         ushort last_cmd;
  83 #ifdef OMAP_HSMMC_USE_GPIO
  84 #if CONFIG_IS_ENABLED(DM_MMC)
  85         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  86         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  87 #else
  88         int cd_gpio;
  89         int wp_gpio;
  90 #endif
  91 #endif
  92 #if CONFIG_IS_ENABLED(DM_MMC)
  93         enum bus_mode mode;
  94 #endif
  95         u8 controller_flags;
  96 #ifdef CONFIG_MMC_OMAP_HS_ADMA
  97         struct omap_hsmmc_adma_desc *adma_desc_table;
  98         uint desc_slot;
  99 #endif
 100         const char *hw_rev;
 101         struct udevice *pbias_supply;
 102         uint signal_voltage;
 103 #ifdef CONFIG_IODELAY_RECALIBRATION
 104         struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
 105         struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
 106         struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
 107         struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
 108         struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
 109         struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
 110         struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
 111         struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
 112         struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
 113 #endif
 114 };
 115
 116 struct omap_mmc_of_data {
 117         u8 controller_flags;
 118 };
 119
 120 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 121 struct omap_hsmmc_adma_desc {
 122         u8 attr;
 123         u8 reserved;
 124         u16 len;
 125         u32 addr;
 126 };
 127
 128 #define ADMA_MAX_LEN    63488
 129
 130 /* Decriptor table defines */
 131 #define ADMA_DESC_ATTR_VALID            BIT(0)
 132 #define ADMA_DESC_ATTR_END              BIT(1)
 133 #define ADMA_DESC_ATTR_INT              BIT(2)
 134 #define ADMA_DESC_ATTR_ACT1             BIT(4)
 135 #define ADMA_DESC_ATTR_ACT2             BIT(5)
 136
 137 #define ADMA_DESC_TRANSFER_DATA         ADMA_DESC_ATTR_ACT2
 138 #define ADMA_DESC_LINK_DESC     (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
 139 #endif
 140
 141 /* If we fail after 1 second wait, something is really bad */
 142 #define MAX_RETRY_MS    1000
 143 #define MMC_TIMEOUT_MS  20
 144
 145 /* DMA transfers can take a long time if a lot a data is transferred.
 146  * The timeout must take in account the amount of data. Let's assume
 147  * that the time will never exceed 333 ms per MB (in other word we assume
 148  * that the bandwidth is always above 3MB/s).
 149  */
 150 #define DMA_TIMEOUT_PER_MB      333
 151 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT           BIT(0)
 152 #define OMAP_HSMMC_NO_1_8_V                     BIT(1)
 153 #define OMAP_HSMMC_USE_ADMA                     BIT(2)
 154 #define OMAP_HSMMC_REQUIRE_IODELAY              BIT(3)
 155
 156 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
 157 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 158                         unsigned int siz);
 159 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
 160 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
 161 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
 162
 163 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
 164 {
 165 #if CONFIG_IS_ENABLED(DM_MMC)
 166         return dev_get_priv(mmc->dev);
 167 #else
 168         return (struct omap_hsmmc_data *)mmc->priv;
 169 #endif
 170 }
 171 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
 172 {
 173 #if CONFIG_IS_ENABLED(DM_MMC)
 174         struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
 175         return &plat->cfg;
 176 #else
 177         return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
 178 #endif
 179 }
 180
 181 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
 182 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
 183 {
 184         int ret;
 185
 186 #ifndef CONFIG_DM_GPIO
 187         if (!gpio_is_valid(gpio))
 188                 return -1;
 189 #endif
 190         ret = gpio_request(gpio, label);
 191         if (ret)
 192                 return ret;
 193
 194         ret = gpio_direction_input(gpio);
 195         if (ret)
 196                 return ret;
 197
 198         return gpio;
 199 }
 200 #endif
 201
 202 static unsigned char mmc_board_init(struct mmc *mmc)
 203 {
 204 #if defined(CONFIG_OMAP34XX)
 205         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
 206         t2_t *t2_base = (t2_t *)T2_BASE;
 207         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 208         u32 pbias_lite;
 209 #ifdef CONFIG_MMC_OMAP36XX_PINS
 210         u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
 211 #endif
 212
 213         pbias_lite = readl(&t2_base->pbias_lite);
 214         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 215 #ifdef CONFIG_TARGET_OMAP3_CAIRO
 216         /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
 217         pbias_lite &= ~PBIASLITEVMODE0;
 218 #endif
 219 #ifdef CONFIG_TARGET_OMAP3_LOGIC
 220         /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
 221         pbias_lite &= ~PBIASLITEVMODE1;
 222 #endif
 223 #ifdef CONFIG_MMC_OMAP36XX_PINS
 224         if (get_cpu_family() == CPU_OMAP36XX) {
 225                 /* Disable extended drain IO before changing PBIAS */
 226                 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
 227                 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
 228         }
 229 #endif
 230         writel(pbias_lite, &t2_base->pbias_lite);
 231
 232         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 233                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 234                 &t2_base->pbias_lite);
 235
 236 #ifdef CONFIG_MMC_OMAP36XX_PINS
 237         if (get_cpu_family() == CPU_OMAP36XX)
 238                 /* Enable extended drain IO after changing PBIAS */
 239                 writel(wkup_ctrl |
 240                                 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
 241                                 OMAP34XX_CTRL_WKUP_CTRL);
 242 #endif
 243         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 244                 &t2_base->devconf0);
 245
 246         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 247                 &t2_base->devconf1);
 248
 249         /* Change from default of 52MHz to 26MHz if necessary */
 250         if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
 251                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 252                         &t2_base->ctl_prog_io1);
 253
 254         writel(readl(&prcm_base->fclken1_core) |
 255                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 256                 &prcm_base->fclken1_core);
 257
 258         writel(readl(&prcm_base->iclken1_core) |
 259                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 260                 &prcm_base->iclken1_core);
 261 #endif
 262
 263 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
 264         !CONFIG_IS_ENABLED(DM_REGULATOR)
 265         /* PBIAS config needed for MMC1 only */
 266         if (mmc_get_blk_desc(mmc)->devnum == 0)
 267                 vmmc_pbias_config(LDO_VOLT_3V3);
 268 #endif
 269
 270         return 0;
 271 }
 272
 273 void mmc_init_stream(struct hsmmc *mmc_base)
 274 {
 275         ulong start;
 276
 277         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 278
 279         writel(MMC_CMD0, &mmc_base->cmd);
 280         start = get_timer(0);
 281         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 282                 if (get_timer(0) - start > MAX_RETRY_MS) {
 283                         printf("%s: timedout waiting for cc!\n", __func__);
 284                         return;
 285                 }
 286         }
 287         writel(CC_MASK, &mmc_base->stat)
 288                 ;
 289         writel(MMC_CMD0, &mmc_base->cmd)
 290                 ;
 291         start = get_timer(0);
 292         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 293                 if (get_timer(0) - start > MAX_RETRY_MS) {
 294                         printf("%s: timedout waiting for cc2!\n", __func__);
 295                         return;
 296                 }
 297         }
 298         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 299 }
 300
 301 #if CONFIG_IS_ENABLED(DM_MMC)
 302 #ifdef CONFIG_IODELAY_RECALIBRATION
 303 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
 304 {
 305         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 306         struct omap_hsmmc_pinctrl_state *pinctrl_state;
 307
 308         switch (priv->mode) {
 309         case MMC_HS_200:
 310                 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
 311                 break;
 312         case UHS_SDR104:
 313                 pinctrl_state = priv->sdr104_pinctrl_state;
 314                 break;
 315         case UHS_SDR50:
 316                 pinctrl_state = priv->sdr50_pinctrl_state;
 317                 break;
 318         case UHS_DDR50:
 319                 pinctrl_state = priv->ddr50_pinctrl_state;
 320                 break;
 321         case UHS_SDR25:
 322                 pinctrl_state = priv->sdr25_pinctrl_state;
 323                 break;
 324         case UHS_SDR12:
 325                 pinctrl_state = priv->sdr12_pinctrl_state;
 326                 break;
 327         case SD_HS:
 328         case MMC_HS:
 329         case MMC_HS_52:
 330                 pinctrl_state = priv->hs_pinctrl_state;
 331                 break;
 332         case MMC_DDR_52:
 333                 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
 334         default:
 335                 pinctrl_state = priv->default_pinctrl_state;
 336                 break;
 337         }
 338
 339         if (!pinctrl_state)
 340                 pinctrl_state = priv->default_pinctrl_state;
 341
 342         if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
 343                 if (pinctrl_state->iodelay)
 344                         late_recalibrate_iodelay(pinctrl_state->padconf,
 345                                                  pinctrl_state->npads,
 346                                                  pinctrl_state->iodelay,
 347                                                  pinctrl_state->niodelays);
 348                 else
 349                         do_set_mux32((*ctrl)->control_padconf_core_base,
 350                                      pinctrl_state->padconf,
 351                                      pinctrl_state->npads);
 352         }
 353 }
 354 #endif
 355 static void omap_hsmmc_set_timing(struct mmc *mmc)
 356 {
 357         u32 val;
 358         struct hsmmc *mmc_base;
 359         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 360
 361         mmc_base = priv->base_addr;
 362
 363         omap_hsmmc_stop_clock(mmc_base);
 364         val = readl(&mmc_base->ac12);
 365         val &= ~AC12_UHSMC_MASK;
 366         priv->mode = mmc->selected_mode;
 367
 368         if (mmc_is_mode_ddr(priv->mode))
 369                 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
 370         else
 371                 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
 372
 373         switch (priv->mode) {
 374         case MMC_HS_200:
 375         case UHS_SDR104:
 376                 val |= AC12_UHSMC_SDR104;
 377                 break;
 378         case UHS_SDR50:
 379                 val |= AC12_UHSMC_SDR50;
 380                 break;
 381         case MMC_DDR_52:
 382         case UHS_DDR50:
 383                 val |= AC12_UHSMC_DDR50;
 384                 break;
 385         case SD_HS:
 386         case MMC_HS_52:
 387         case UHS_SDR25:
 388                 val |= AC12_UHSMC_SDR25;
 389                 break;
 390         case MMC_LEGACY:
 391         case MMC_HS:
 392         case SD_LEGACY:
 393         case UHS_SDR12:
 394                 val |= AC12_UHSMC_SDR12;
 395                 break;
 396         default:
 397                 val |= AC12_UHSMC_RES;
 398                 break;
 399         }
 400         writel(val, &mmc_base->ac12);
 401
 402 #ifdef CONFIG_IODELAY_RECALIBRATION
 403         omap_hsmmc_io_recalibrate(mmc);
 404 #endif
 405         omap_hsmmc_start_clock(mmc_base);
 406 }
 407
 408 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
 409 {
 410         struct hsmmc *mmc_base;
 411         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 412         u32 hctl, ac12;
 413
 414         mmc_base = priv->base_addr;
 415
 416         hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
 417         ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
 418
 419         switch (signal_voltage) {
 420         case MMC_SIGNAL_VOLTAGE_330:
 421                 hctl |= SDVS_3V3;
 422                 break;
 423         case MMC_SIGNAL_VOLTAGE_180:
 424                 hctl |= SDVS_1V8;
 425                 ac12 |= AC12_V1V8_SIGEN;
 426                 break;
 427         }
 428
 429         writel(hctl, &mmc_base->hctl);
 430         writel(ac12, &mmc_base->ac12);
 431 }
 432
 433 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
 434 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout)
 435 {
 436         int ret = -ETIMEDOUT;
 437         u32 con;
 438         bool dat0_high;
 439         bool target_dat0_high = !!state;
 440         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 441         struct hsmmc *mmc_base = priv->base_addr;
 442
 443         con = readl(&mmc_base->con);
 444         writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
 445
 446         timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
 447         while (timeout--)       {
 448                 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
 449                 if (dat0_high == target_dat0_high) {
 450                         ret = 0;
 451                         break;
 452                 }
 453                 udelay(10);
 454         }
 455         writel(con, &mmc_base->con);
 456
 457         return ret;
 458 }
 459 #endif
 460
 461 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 462 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 463 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
 464 {
 465         int ret = 0;
 466         int uV = mV * 1000;
 467
 468         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 469
 470         if (!mmc->vqmmc_supply)
 471                 return 0;
 472
 473         /* Disable PBIAS */
 474         ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
 475         if (ret)
 476                 return ret;
 477
 478         /* Turn off IO voltage */
 479         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
 480         if (ret)
 481                 return ret;
 482         /* Program a new IO voltage value */
 483         ret = regulator_set_value(mmc->vqmmc_supply, uV);
 484         if (ret)
 485                 return ret;
 486         /* Turn on IO voltage */
 487         ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 488         if (ret)
 489                 return ret;
 490
 491         /* Program PBIAS voltage*/
 492         ret = regulator_set_value(priv->pbias_supply, uV);
 493         if (ret && ret != -ENOSYS)
 494                 return ret;
 495         /* Enable PBIAS */
 496         ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
 497         if (ret)
 498                 return ret;
 499
 500         return 0;
 501 }
 502 #endif
 503
 504 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
 505 {
 506         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 507         struct hsmmc *mmc_base = priv->base_addr;
 508         int mv = mmc_voltage_to_mv(mmc->signal_voltage);
 509         u32 capa_mask;
 510         __maybe_unused u8 palmas_ldo_volt;
 511         u32 val;
 512
 513         if (mv < 0)
 514                 return -EINVAL;
 515
 516         if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 517                 mv = 3300;
 518                 capa_mask = VS33_3V3SUP;
 519                 palmas_ldo_volt = LDO_VOLT_3V3;
 520         } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 521                 capa_mask = VS18_1V8SUP;
 522                 palmas_ldo_volt = LDO_VOLT_1V8;
 523         } else {
 524                 return -EOPNOTSUPP;
 525         }
 526
 527         val = readl(&mmc_base->capa);
 528         if (!(val & capa_mask))
 529                 return -EOPNOTSUPP;
 530
 531         priv->signal_voltage = mmc->signal_voltage;
 532
 533         omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
 534
 535 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 536         return omap_hsmmc_set_io_regulator(mmc, mv);
 537 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
 538         defined(CONFIG_PALMAS_POWER)
 539         if (mmc_get_blk_desc(mmc)->devnum == 0)
 540                 vmmc_pbias_config(palmas_ldo_volt);
 541         return 0;
 542 #else
 543         return 0;
 544 #endif
 545 }
 546 #endif
 547
 548 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
 549 {
 550         struct hsmmc *mmc_base;
 551         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 552         u32 val;
 553
 554         mmc_base = priv->base_addr;
 555         val = readl(&mmc_base->capa);
 556
 557         if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 558                 val |= (VS33_3V3SUP | VS18_1V8SUP);
 559         } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
 560                 val |= VS33_3V3SUP;
 561                 val &= ~VS18_1V8SUP;
 562         } else {
 563                 val |= VS18_1V8SUP;
 564                 val &= ~VS33_3V3SUP;
 565         }
 566
 567         writel(val, &mmc_base->capa);
 568
 569         return val;
 570 }
 571
 572 #ifdef MMC_SUPPORTS_TUNING
 573 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
 574 {
 575         struct hsmmc *mmc_base;
 576         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 577         u32 val;
 578
 579         mmc_base = priv->base_addr;
 580         val = readl(&mmc_base->ac12);
 581         val &= ~(AC12_SCLK_SEL);
 582         writel(val, &mmc_base->ac12);
 583
 584         val = readl(&mmc_base->dll);
 585         val &= ~(DLL_FORCE_VALUE | DLL_SWT);
 586         writel(val, &mmc_base->dll);
 587 }
 588
 589 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
 590 {
 591         int i;
 592         struct hsmmc *mmc_base;
 593         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 594         u32 val;
 595
 596         mmc_base = priv->base_addr;
 597         val = readl(&mmc_base->dll);
 598         val |= DLL_FORCE_VALUE;
 599         val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
 600         val |= (count << DLL_FORCE_SR_C_SHIFT);
 601         writel(val, &mmc_base->dll);
 602
 603         val |= DLL_CALIB;
 604         writel(val, &mmc_base->dll);
 605         for (i = 0; i < 1000; i++) {
 606                 if (readl(&mmc_base->dll) & DLL_CALIB)
 607                         break;
 608         }
 609         val &= ~DLL_CALIB;
 610         writel(val, &mmc_base->dll);
 611 }
 612
 613 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
 614 {
 615         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 616         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 617         struct mmc *mmc = upriv->mmc;
 618         struct hsmmc *mmc_base;
 619         u32 val;
 620         u8 cur_match, prev_match = 0;
 621         int ret;
 622         u32 phase_delay = 0;
 623         u32 start_window = 0, max_window = 0;
 624         u32 length = 0, max_len = 0;
 625         bool single_point_failure = false;
 626         struct udevice *thermal_dev;
 627         int temperature;
 628         int i;
 629
 630         mmc_base = priv->base_addr;
 631         val = readl(&mmc_base->capa2);
 632
 633         /* clock tuning is not needed for upto 52MHz */
 634         if (!((mmc->selected_mode == MMC_HS_200) ||
 635               (mmc->selected_mode == UHS_SDR104) ||
 636               ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
 637                 return 0;
 638
 639         ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
 640         if (ret) {
 641                 printf("Couldn't get thermal device for tuning\n");
 642                 return ret;
 643         }
 644         ret = thermal_get_temp(thermal_dev, &temperature);
 645         if (ret) {
 646                 printf("Couldn't get temperature for tuning\n");
 647                 return ret;
 648         }
 649         val = readl(&mmc_base->dll);
 650         val |= DLL_SWT;
 651         writel(val, &mmc_base->dll);
 652
 653         /*
 654          * Stage 1: Search for a maximum pass window ignoring any
 655          * any single point failures. If the tuning value ends up
 656          * near it, move away from it in stage 2 below
 657          */
 658         while (phase_delay <= MAX_PHASE_DELAY) {
 659                 omap_hsmmc_set_dll(mmc, phase_delay);
 660
 661                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 662
 663                 if (cur_match) {
 664                         if (prev_match) {
 665                                 length++;
 666                         } else if (single_point_failure) {
 667                                 /* ignore single point failure */
 668                                 length++;
 669                                 single_point_failure = false;
 670                         } else {
 671                                 start_window = phase_delay;
 672                                 length = 1;
 673                         }
 674                 } else {
 675                         single_point_failure = prev_match;
 676                 }
 677
 678                 if (length > max_len) {
 679                         max_window = start_window;
 680                         max_len = length;
 681                 }
 682
 683                 prev_match = cur_match;
 684                 phase_delay += 4;
 685         }
 686
 687         if (!max_len) {
 688                 ret = -EIO;
 689                 goto tuning_error;
 690         }
 691
 692         val = readl(&mmc_base->ac12);
 693         if (!(val & AC12_SCLK_SEL)) {
 694                 ret = -EIO;
 695                 goto tuning_error;
 696         }
 697         /*
 698          * Assign tuning value as a ratio of maximum pass window based
 699          * on temperature
 700          */
 701         if (temperature < -20000)
 702                 phase_delay = min(max_window + 4 * max_len - 24,
 703                                   max_window +
 704                                   DIV_ROUND_UP(13 * max_len, 16) * 4);
 705         else if (temperature < 20000)
 706                 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
 707         else if (temperature < 40000)
 708                 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
 709         else if (temperature < 70000)
 710                 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
 711         else if (temperature < 90000)
 712                 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
 713         else if (temperature < 120000)
 714                 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
 715         else
 716                 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
 717
 718         /*
 719          * Stage 2: Search for a single point failure near the chosen tuning
 720          * value in two steps. First in the +3 to +10 range and then in the
 721          * +2 to -10 range. If found, move away from it in the appropriate
 722          * direction by the appropriate amount depending on the temperature.
 723          */
 724         for (i = 3; i <= 10; i++) {
 725                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 726                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 727                         if (temperature < 10000)
 728                                 phase_delay += i + 6;
 729                         else if (temperature < 20000)
 730                                 phase_delay += i - 12;
 731                         else if (temperature < 70000)
 732                                 phase_delay += i - 8;
 733                         else if (temperature < 90000)
 734                                 phase_delay += i - 6;
 735                         else
 736                                 phase_delay += i - 6;
 737
 738                         goto single_failure_found;
 739                 }
 740         }
 741
 742         for (i = 2; i >= -10; i--) {
 743                 omap_hsmmc_set_dll(mmc, phase_delay + i);
 744                 if (mmc_send_tuning(mmc, opcode, NULL)) {
 745                         if (temperature < 10000)
 746                                 phase_delay += i + 12;
 747                         else if (temperature < 20000)
 748                                 phase_delay += i + 8;
 749                         else if (temperature < 70000)
 750                                 phase_delay += i + 8;
 751                         else if (temperature < 90000)
 752                                 phase_delay += i + 10;
 753                         else
 754                                 phase_delay += i + 12;
 755
 756                         goto single_failure_found;
 757                 }
 758         }
 759
 760 single_failure_found:
 761
 762         omap_hsmmc_set_dll(mmc, phase_delay);
 763
 764         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 765         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 766
 767         return 0;
 768
 769 tuning_error:
 770
 771         omap_hsmmc_disable_tuning(mmc);
 772         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 773         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 774
 775         return ret;
 776 }
 777 #endif
 778
 779 static void omap_hsmmc_send_init_stream(struct udevice *dev)
 780 {
 781         struct omap_hsmmc_data *priv = dev_get_priv(dev);
 782         struct hsmmc *mmc_base = priv->base_addr;
 783
 784         mmc_init_stream(mmc_base);
 785 }
 786 #endif
 787
 788 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
 789 {
 790         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 791         struct hsmmc *mmc_base = priv->base_addr;
 792         u32 irq_mask = INT_EN_MASK;
 793
 794         /*
 795          * TODO: Errata i802 indicates only DCRC interrupts can occur during
 796          * tuning procedure and DCRC should be disabled. But see occurences
 797          * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
 798          * interrupts occur along with BRR, so the data is actually in the
 799          * buffer. It has to be debugged why these interrutps occur
 800          */
 801         if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
 802                 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
 803
 804         writel(irq_mask, &mmc_base->ie);
 805 }
 806
 807 static int omap_hsmmc_init_setup(struct mmc *mmc)
 808 {
 809         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 810         struct hsmmc *mmc_base;
 811         unsigned int reg_val;
 812         unsigned int dsor;
 813         ulong start;
 814
 815         mmc_base = priv->base_addr;
 816         mmc_board_init(mmc);
 817
 818         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 819                 &mmc_base->sysconfig);
 820         start = get_timer(0);
 821         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 822                 if (get_timer(0) - start > MAX_RETRY_MS) {
 823                         printf("%s: timedout waiting for cc2!\n", __func__);
 824                         return -ETIMEDOUT;
 825                 }
 826         }
 827         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 828         start = get_timer(0);
 829         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 830                 if (get_timer(0) - start > MAX_RETRY_MS) {
 831                         printf("%s: timedout waiting for softresetall!\n",
 832                                 __func__);
 833                         return -ETIMEDOUT;
 834                 }
 835         }
 836 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 837         reg_val = readl(&mmc_base->hl_hwinfo);
 838         if (reg_val & MADMA_EN)
 839                 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
 840 #endif
 841
 842 #if CONFIG_IS_ENABLED(DM_MMC)
 843         reg_val = omap_hsmmc_set_capabilities(mmc);
 844         omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
 845                           MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
 846 #else
 847         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 848         writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
 849                 &mmc_base->capa);
 850 #endif
 851
 852         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 853
 854         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 855                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 856                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 857
 858         dsor = 240;
 859         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 860                 (ICE_STOP | DTO_15THDTO));
 861         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 862                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 863         start = get_timer(0);
 864         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 865                 if (get_timer(0) - start > MAX_RETRY_MS) {
 866                         printf("%s: timedout waiting for ics!\n", __func__);
 867                         return -ETIMEDOUT;
 868                 }
 869         }
 870         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 871
 872         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 873
 874         mmc_enable_irq(mmc, NULL);
 875
 876 #if !CONFIG_IS_ENABLED(DM_MMC)
 877         mmc_init_stream(mmc_base);
 878 #endif
 879
 880         return 0;
 881 }
 882
 883 /*
 884  * MMC controller internal finite state machine reset
 885  *
 886  * Used to reset command or data internal state machines, using respectively
 887  * SRC or SRD bit of SYSCTL register
 888  */
 889 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 890 {
 891         ulong start;
 892
 893         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 894
 895         /*
 896          * CMD(DAT) lines reset procedures are slightly different
 897          * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
 898          * According to OMAP3 TRM:
 899          * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
 900          * returns to 0x0.
 901          * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
 902          * procedure steps must be as follows:
 903          * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
 904          *    MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
 905          * 2. Poll the SRC(SRD) bit until it is set to 0x1.
 906          * 3. Wait until the SRC (SRD) bit returns to 0x0
 907          *    (reset procedure is completed).
 908          */
 909 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 910         defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
 911         if (!(readl(&mmc_base->sysctl) & bit)) {
 912                 start = get_timer(0);
 913                 while (!(readl(&mmc_base->sysctl) & bit)) {
 914                         if (get_timer(0) - start > MMC_TIMEOUT_MS)
 915                                 return;
 916                 }
 917         }
 918 #endif
 919         start = get_timer(0);
 920         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 921                 if (get_timer(0) - start > MAX_RETRY_MS) {
 922                         printf("%s: timedout waiting for sysctl %x to clear\n",
 923                                 __func__, bit);
 924                         return;
 925                 }
 926         }
 927 }
 928
 929 #ifdef CONFIG_MMC_OMAP_HS_ADMA
 930 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 931 {
 932         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 933         struct omap_hsmmc_adma_desc *desc;
 934         u8 attr;
 935
 936         desc = &priv->adma_desc_table[priv->desc_slot];
 937
 938         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
 939         if (!end)
 940                 priv->desc_slot++;
 941         else
 942                 attr |= ADMA_DESC_ATTR_END;
 943
 944         desc->len = len;
 945         desc->addr = (u32)buf;
 946         desc->reserved = 0;
 947         desc->attr = attr;
 948 }
 949
 950 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
 951                                           struct mmc_data *data)
 952 {
 953         uint total_len = data->blocksize * data->blocks;
 954         uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
 955         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 956         int i = desc_count;
 957         char *buf;
 958
 959         priv->desc_slot = 0;
 960         priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
 961                                 memalign(ARCH_DMA_MINALIGN, desc_count *
 962                                 sizeof(struct omap_hsmmc_adma_desc));
 963
 964         if (data->flags & MMC_DATA_READ)
 965                 buf = data->dest;
 966         else
 967                 buf = (char *)data->src;
 968
 969         while (--i) {
 970                 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
 971                 buf += ADMA_MAX_LEN;
 972                 total_len -= ADMA_MAX_LEN;
 973         }
 974
 975         omap_hsmmc_adma_desc(mmc, buf, total_len, true);
 976
 977         flush_dcache_range((long)priv->adma_desc_table,
 978                            (long)priv->adma_desc_table +
 979                            ROUND(desc_count *
 980                            sizeof(struct omap_hsmmc_adma_desc),
 981                            ARCH_DMA_MINALIGN));
 982 }
 983
 984 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
 985 {
 986         struct hsmmc *mmc_base;
 987         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
 988         u32 val;
 989         char *buf;
 990
 991         mmc_base = priv->base_addr;
 992         omap_hsmmc_prepare_adma_table(mmc, data);
 993
 994         if (data->flags & MMC_DATA_READ)
 995                 buf = data->dest;
 996         else
 997                 buf = (char *)data->src;
 998
 999         val = readl(&mmc_base->hctl);
1000         val |= DMA_SELECT;
1001         writel(val, &mmc_base->hctl);
1002
1003         val = readl(&mmc_base->con);
1004         val |= DMA_MASTER;
1005         writel(val, &mmc_base->con);
1006
1007         writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1008
1009         flush_dcache_range((u32)buf,
1010                            (u32)buf +
1011                            ROUND(data->blocksize * data->blocks,
1012                                  ARCH_DMA_MINALIGN));
1013 }
1014
1015 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1016 {
1017         struct hsmmc *mmc_base;
1018         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1019         u32 val;
1020
1021         mmc_base = priv->base_addr;
1022
1023         val = readl(&mmc_base->con);
1024         val &= ~DMA_MASTER;
1025         writel(val, &mmc_base->con);
1026
1027         val = readl(&mmc_base->hctl);
1028         val &= ~DMA_SELECT;
1029         writel(val, &mmc_base->hctl);
1030
1031         kfree(priv->adma_desc_table);
1032 }
1033 #else
1034 #define omap_hsmmc_adma_desc
1035 #define omap_hsmmc_prepare_adma_table
1036 #define omap_hsmmc_prepare_data
1037 #define omap_hsmmc_dma_cleanup
1038 #endif
1039
1040 #if !CONFIG_IS_ENABLED(DM_MMC)
1041 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1042                         struct mmc_data *data)
1043 {
1044         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1045 #else
1046 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1047                         struct mmc_data *data)
1048 {
1049         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1050         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1051         struct mmc *mmc = upriv->mmc;
1052 #endif
1053         struct hsmmc *mmc_base;
1054         unsigned int flags, mmc_stat;
1055         ulong start;
1056         priv->last_cmd = cmd->cmdidx;
1057
1058         mmc_base = priv->base_addr;
1059
1060         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1061                 return 0;
1062
1063         start = get_timer(0);
1064         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1065                 if (get_timer(0) - start > MAX_RETRY_MS) {
1066                         printf("%s: timedout waiting on cmd inhibit to clear\n",
1067                                         __func__);
1068                         return -ETIMEDOUT;
1069                 }
1070         }
1071         writel(0xFFFFFFFF, &mmc_base->stat);
1072         start = get_timer(0);
1073         while (readl(&mmc_base->stat)) {
1074                 if (get_timer(0) - start > MAX_RETRY_MS) {
1075                         printf("%s: timedout waiting for STAT (%x) to clear\n",
1076                                 __func__, readl(&mmc_base->stat));
1077                         return -ETIMEDOUT;
1078                 }
1079         }
1080         /*
1081          * CMDREG
1082          * CMDIDX[13:8] : Command index
1083          * DATAPRNT[5]  : Data Present Select
1084          * ENCMDIDX[4]  : Command Index Check Enable
1085          * ENCMDCRC[3]  : Command CRC Check Enable
1086          * RSPTYP[1:0]
1087          *      00 = No Response
1088          *      01 = Length 136
1089          *      10 = Length 48
1090          *      11 = Length 48 Check busy after response
1091          */
1092         /* Delay added before checking the status of frq change
1093          * retry not supported by mmc.c(core file)
1094          */
1095         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1096                 udelay(50000); /* wait 50 ms */
1097
1098         if (!(cmd->resp_type & MMC_RSP_PRESENT))
1099                 flags = 0;
1100         else if (cmd->resp_type & MMC_RSP_136)
1101                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1102         else if (cmd->resp_type & MMC_RSP_BUSY)
1103                 flags = RSP_TYPE_LGHT48B;
1104         else
1105                 flags = RSP_TYPE_LGHT48;
1106
1107         /* enable default flags */
1108         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1109                         MSBS_SGLEBLK);
1110         flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1111
1112         if (cmd->resp_type & MMC_RSP_CRC)
1113                 flags |= CCCE_CHECK;
1114         if (cmd->resp_type & MMC_RSP_OPCODE)
1115                 flags |= CICE_CHECK;
1116
1117         if (data) {
1118                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1119                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1120                         flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1121                         data->blocksize = 512;
1122                         writel(data->blocksize | (data->blocks << 16),
1123                                                         &mmc_base->blk);
1124                 } else
1125                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1126
1127                 if (data->flags & MMC_DATA_READ)
1128                         flags |= (DP_DATA | DDIR_READ);
1129                 else
1130                         flags |= (DP_DATA | DDIR_WRITE);
1131
1132 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1133                 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1134                     !mmc_is_tuning_cmd(cmd->cmdidx)) {
1135                         omap_hsmmc_prepare_data(mmc, data);
1136                         flags |= DE_ENABLE;
1137                 }
1138 #endif
1139         }
1140
1141         mmc_enable_irq(mmc, cmd);
1142
1143         writel(cmd->cmdarg, &mmc_base->arg);
1144         udelay(20);             /* To fix "No status update" error on eMMC */
1145         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1146
1147         start = get_timer(0);
1148         do {
1149                 mmc_stat = readl(&mmc_base->stat);
1150                 if (get_timer(start) > MAX_RETRY_MS) {
1151                         printf("%s : timeout: No status update\n", __func__);
1152                         return -ETIMEDOUT;
1153                 }
1154         } while (!mmc_stat);
1155
1156         if ((mmc_stat & IE_CTO) != 0) {
1157                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1158                 return -ETIMEDOUT;
1159         } else if ((mmc_stat & ERRI_MASK) != 0)
1160                 return -1;
1161
1162         if (mmc_stat & CC_MASK) {
1163                 writel(CC_MASK, &mmc_base->stat);
1164                 if (cmd->resp_type & MMC_RSP_PRESENT) {
1165                         if (cmd->resp_type & MMC_RSP_136) {
1166                                 /* response type 2 */
1167                                 cmd->response[3] = readl(&mmc_base->rsp10);
1168                                 cmd->response[2] = readl(&mmc_base->rsp32);
1169                                 cmd->response[1] = readl(&mmc_base->rsp54);
1170                                 cmd->response[0] = readl(&mmc_base->rsp76);
1171                         } else
1172                                 /* response types 1, 1b, 3, 4, 5, 6 */
1173                                 cmd->response[0] = readl(&mmc_base->rsp10);
1174                 }
1175         }
1176
1177 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1178         if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1179             !mmc_is_tuning_cmd(cmd->cmdidx)) {
1180                 u32 sz_mb, timeout;
1181
1182                 if (mmc_stat & IE_ADMAE) {
1183                         omap_hsmmc_dma_cleanup(mmc);
1184                         return -EIO;
1185                 }
1186
1187                 sz_mb = DIV_ROUND_UP(data->blocksize *  data->blocks, 1 << 20);
1188                 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1189                 if (timeout < MAX_RETRY_MS)
1190                         timeout = MAX_RETRY_MS;
1191
1192                 start = get_timer(0);
1193                 do {
1194                         mmc_stat = readl(&mmc_base->stat);
1195                         if (mmc_stat & TC_MASK) {
1196                                 writel(readl(&mmc_base->stat) | TC_MASK,
1197                                        &mmc_base->stat);
1198                                 break;
1199                         }
1200                         if (get_timer(start) > timeout) {
1201                                 printf("%s : DMA timeout: No status update\n",
1202                                        __func__);
1203                                 return -ETIMEDOUT;
1204                         }
1205                 } while (1);
1206
1207                 omap_hsmmc_dma_cleanup(mmc);
1208                 return 0;
1209         }
1210 #endif
1211
1212         if (data && (data->flags & MMC_DATA_READ)) {
1213                 mmc_read_data(mmc_base, data->dest,
1214                                 data->blocksize * data->blocks);
1215         } else if (data && (data->flags & MMC_DATA_WRITE)) {
1216                 mmc_write_data(mmc_base, data->src,
1217                                 data->blocksize * data->blocks);
1218         }
1219         return 0;
1220 }
1221
1222 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1223 {
1224         unsigned int *output_buf = (unsigned int *)buf;
1225         unsigned int mmc_stat;
1226         unsigned int count;
1227
1228         /*
1229          * Start Polled Read
1230          */
1231         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1232         count /= 4;
1233
1234         while (size) {
1235                 ulong start = get_timer(0);
1236                 do {
1237                         mmc_stat = readl(&mmc_base->stat);
1238                         if (get_timer(0) - start > MAX_RETRY_MS) {
1239                                 printf("%s: timedout waiting for status!\n",
1240                                                 __func__);
1241                                 return -ETIMEDOUT;
1242                         }
1243                 } while (mmc_stat == 0);
1244
1245                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1246                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1247
1248                 if ((mmc_stat & ERRI_MASK) != 0)
1249                         return 1;
1250
1251                 if (mmc_stat & BRR_MASK) {
1252                         unsigned int k;
1253
1254                         writel(readl(&mmc_base->stat) | BRR_MASK,
1255                                 &mmc_base->stat);
1256                         for (k = 0; k < count; k++) {
1257                                 *output_buf = readl(&mmc_base->data);
1258                                 output_buf++;
1259                         }
1260                         size -= (count*4);
1261                 }
1262
1263                 if (mmc_stat & BWR_MASK)
1264                         writel(readl(&mmc_base->stat) | BWR_MASK,
1265                                 &mmc_base->stat);
1266
1267                 if (mmc_stat & TC_MASK) {
1268                         writel(readl(&mmc_base->stat) | TC_MASK,
1269                                 &mmc_base->stat);
1270                         break;
1271                 }
1272         }
1273         return 0;
1274 }
1275
1276 #if CONFIG_IS_ENABLED(MMC_WRITE)
1277 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1278                           unsigned int size)
1279 {
1280         unsigned int *input_buf = (unsigned int *)buf;
1281         unsigned int mmc_stat;
1282         unsigned int count;
1283
1284         /*
1285          * Start Polled Write
1286          */
1287         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1288         count /= 4;
1289
1290         while (size) {
1291                 ulong start = get_timer(0);
1292                 do {
1293                         mmc_stat = readl(&mmc_base->stat);
1294                         if (get_timer(0) - start > MAX_RETRY_MS) {
1295                                 printf("%s: timedout waiting for status!\n",
1296                                                 __func__);
1297                                 return -ETIMEDOUT;
1298                         }
1299                 } while (mmc_stat == 0);
1300
1301                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1302                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1303
1304                 if ((mmc_stat & ERRI_MASK) != 0)
1305                         return 1;
1306
1307                 if (mmc_stat & BWR_MASK) {
1308                         unsigned int k;
1309
1310                         writel(readl(&mmc_base->stat) | BWR_MASK,
1311                                         &mmc_base->stat);
1312                         for (k = 0; k < count; k++) {
1313                                 writel(*input_buf, &mmc_base->data);
1314                                 input_buf++;
1315                         }
1316                         size -= (count*4);
1317                 }
1318
1319                 if (mmc_stat & BRR_MASK)
1320                         writel(readl(&mmc_base->stat) | BRR_MASK,
1321                                 &mmc_base->stat);
1322
1323                 if (mmc_stat & TC_MASK) {
1324                         writel(readl(&mmc_base->stat) | TC_MASK,
1325                                 &mmc_base->stat);
1326                         break;
1327                 }
1328         }
1329         return 0;
1330 }
1331 #else
1332 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1333                           unsigned int size)
1334 {
1335         return -ENOTSUPP;
1336 }
1337 #endif
1338 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1339 {
1340         writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1341 }
1342
1343 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1344 {
1345         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1346 }
1347
1348 static void omap_hsmmc_set_clock(struct mmc *mmc)
1349 {
1350         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1351         struct hsmmc *mmc_base;
1352         unsigned int dsor = 0;
1353         ulong start;
1354
1355         mmc_base = priv->base_addr;
1356         omap_hsmmc_stop_clock(mmc_base);
1357
1358         /* TODO: Is setting DTO required here? */
1359         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1360                     (ICE_STOP | DTO_15THDTO));
1361
1362         if (mmc->clock != 0) {
1363                 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1364                 if (dsor > CLKD_MAX)
1365                         dsor = CLKD_MAX;
1366         } else {
1367                 dsor = CLKD_MAX;
1368         }
1369
1370         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1371                     (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1372
1373         start = get_timer(0);
1374         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1375                 if (get_timer(0) - start > MAX_RETRY_MS) {
1376                         printf("%s: timedout waiting for ics!\n", __func__);
1377                         return;
1378                 }
1379         }
1380
1381         priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1382         mmc->clock = priv->clock;
1383         omap_hsmmc_start_clock(mmc_base);
1384 }
1385
1386 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1387 {
1388         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1389         struct hsmmc *mmc_base;
1390
1391         mmc_base = priv->base_addr;
1392         /* configue bus width */
1393         switch (mmc->bus_width) {
1394         case 8:
1395                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1396                         &mmc_base->con);
1397                 break;
1398
1399         case 4:
1400                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1401                         &mmc_base->con);
1402                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1403                         &mmc_base->hctl);
1404                 break;
1405
1406         case 1:
1407         default:
1408                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1409                         &mmc_base->con);
1410                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1411                         &mmc_base->hctl);
1412                 break;
1413         }
1414
1415         priv->bus_width = mmc->bus_width;
1416 }
1417
1418 #if !CONFIG_IS_ENABLED(DM_MMC)
1419 static int omap_hsmmc_set_ios(struct mmc *mmc)
1420 {
1421         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1422 #else
1423 static int omap_hsmmc_set_ios(struct udevice *dev)
1424 {
1425         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1426         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1427         struct mmc *mmc = upriv->mmc;
1428 #endif
1429         struct hsmmc *mmc_base = priv->base_addr;
1430         int ret = 0;
1431
1432         if (priv->bus_width != mmc->bus_width)
1433                 omap_hsmmc_set_bus_width(mmc);
1434
1435         if (priv->clock != mmc->clock)
1436                 omap_hsmmc_set_clock(mmc);
1437
1438         if (mmc->clk_disable)
1439                 omap_hsmmc_stop_clock(mmc_base);
1440         else
1441                 omap_hsmmc_start_clock(mmc_base);
1442
1443 #if CONFIG_IS_ENABLED(DM_MMC)
1444         if (priv->mode != mmc->selected_mode)
1445                 omap_hsmmc_set_timing(mmc);
1446
1447 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1448         if (priv->signal_voltage != mmc->signal_voltage)
1449                 ret = omap_hsmmc_set_signal_voltage(mmc);
1450 #endif
1451 #endif
1452         return ret;
1453 }
1454
1455 #ifdef OMAP_HSMMC_USE_GPIO
1456 #if CONFIG_IS_ENABLED(DM_MMC)
1457 static int omap_hsmmc_getcd(struct udevice *dev)
1458 {
1459         int value = -1;
1460 #if CONFIG_IS_ENABLED(DM_GPIO)
1461         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1462         value = dm_gpio_get_value(&priv->cd_gpio);
1463 #endif
1464         /* if no CD return as 1 */
1465         if (value < 0)
1466                 return 1;
1467
1468         return value;
1469 }
1470
1471 static int omap_hsmmc_getwp(struct udevice *dev)
1472 {
1473         int value = 0;
1474 #if CONFIG_IS_ENABLED(DM_GPIO)
1475         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1476         value = dm_gpio_get_value(&priv->wp_gpio);
1477 #endif
1478         /* if no WP return as 0 */
1479         if (value < 0)
1480                 return 0;
1481         return value;
1482 }
1483 #else
1484 static int omap_hsmmc_getcd(struct mmc *mmc)
1485 {
1486         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1487         int cd_gpio;
1488
1489         /* if no CD return as 1 */
1490         cd_gpio = priv->cd_gpio;
1491         if (cd_gpio < 0)
1492                 return 1;
1493
1494         /* NOTE: assumes card detect signal is active-low */
1495         return !gpio_get_value(cd_gpio);
1496 }
1497
1498 static int omap_hsmmc_getwp(struct mmc *mmc)
1499 {
1500         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1501         int wp_gpio;
1502
1503         /* if no WP return as 0 */
1504         wp_gpio = priv->wp_gpio;
1505         if (wp_gpio < 0)
1506                 return 0;
1507
1508         /* NOTE: assumes write protect signal is active-high */
1509         return gpio_get_value(wp_gpio);
1510 }
1511 #endif
1512 #endif
1513
1514 #if CONFIG_IS_ENABLED(DM_MMC)
1515 static const struct dm_mmc_ops omap_hsmmc_ops = {
1516         .send_cmd       = omap_hsmmc_send_cmd,
1517         .set_ios        = omap_hsmmc_set_ios,
1518 #ifdef OMAP_HSMMC_USE_GPIO
1519         .get_cd         = omap_hsmmc_getcd,
1520         .get_wp         = omap_hsmmc_getwp,
1521 #endif
1522 #ifdef MMC_SUPPORTS_TUNING
1523         .execute_tuning = omap_hsmmc_execute_tuning,
1524 #endif
1525         .send_init_stream       = omap_hsmmc_send_init_stream,
1526 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1527         .wait_dat0      = omap_hsmmc_wait_dat0,
1528 #endif
1529 };
1530 #else
1531 static const struct mmc_ops omap_hsmmc_ops = {
1532         .send_cmd       = omap_hsmmc_send_cmd,
1533         .set_ios        = omap_hsmmc_set_ios,
1534         .init           = omap_hsmmc_init_setup,
1535 #ifdef OMAP_HSMMC_USE_GPIO
1536         .getcd          = omap_hsmmc_getcd,
1537         .getwp          = omap_hsmmc_getwp,
1538 #endif
1539 };
1540 #endif
1541
1542 #if !CONFIG_IS_ENABLED(DM_MMC)
1543 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1544                 int wp_gpio)
1545 {
1546         struct mmc *mmc;
1547         struct omap_hsmmc_data *priv;
1548         struct mmc_config *cfg;
1549         uint host_caps_val;
1550
1551         priv = calloc(1, sizeof(*priv));
1552         if (priv == NULL)
1553                 return -1;
1554
1555         host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1556
1557         switch (dev_index) {
1558         case 0:
1559                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1560                 break;
1561 #ifdef OMAP_HSMMC2_BASE
1562         case 1:
1563                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1564 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1565         defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1566         defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1567                 defined(CONFIG_HSMMC2_8BIT)
1568                 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1569                 host_caps_val |= MMC_MODE_8BIT;
1570 #endif
1571                 break;
1572 #endif
1573 #ifdef OMAP_HSMMC3_BASE
1574         case 2:
1575                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1576 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1577                 /* Enable 8-bit interface for eMMC on DRA7XX */
1578                 host_caps_val |= MMC_MODE_8BIT;
1579 #endif
1580                 break;
1581 #endif
1582         default:
1583                 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1584                 return 1;
1585         }
1586 #ifdef OMAP_HSMMC_USE_GPIO
1587         /* on error gpio values are set to -1, which is what we want */
1588         priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1589         priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1590 #endif
1591
1592         cfg = &priv->cfg;
1593
1594         cfg->name = "OMAP SD/MMC";
1595         cfg->ops = &omap_hsmmc_ops;
1596
1597         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1598         cfg->host_caps = host_caps_val & ~host_caps_mask;
1599
1600         cfg->f_min = 400000;
1601
1602         if (f_max != 0)
1603                 cfg->f_max = f_max;
1604         else {
1605                 if (cfg->host_caps & MMC_MODE_HS) {
1606                         if (cfg->host_caps & MMC_MODE_HS_52MHz)
1607                                 cfg->f_max = 52000000;
1608                         else
1609                                 cfg->f_max = 26000000;
1610                 } else
1611                         cfg->f_max = 20000000;
1612         }
1613
1614         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1615
1616 #if defined(CONFIG_OMAP34XX)
1617         /*
1618          * Silicon revs 2.1 and older do not support multiblock transfers.
1619          */
1620         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1621                 cfg->b_max = 1;
1622 #endif
1623
1624         mmc = mmc_create(cfg, priv);
1625         if (mmc == NULL)
1626                 return -1;
1627
1628         return 0;
1629 }
1630 #else
1631
1632 #ifdef CONFIG_IODELAY_RECALIBRATION
1633 static struct pad_conf_entry *
1634 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1635 {
1636         int index = 0;
1637         struct pad_conf_entry *padconf;
1638
1639         padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1640         if (!padconf) {
1641                 debug("failed to allocate memory\n");
1642                 return 0;
1643         }
1644
1645         while (index < count) {
1646                 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1647                 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1648                 index++;
1649         }
1650
1651         return padconf;
1652 }
1653
1654 static struct iodelay_cfg_entry *
1655 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1656 {
1657         int index = 0;
1658         struct iodelay_cfg_entry *iodelay;
1659
1660         iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1661         if (!iodelay) {
1662                 debug("failed to allocate memory\n");
1663                 return 0;
1664         }
1665
1666         while (index < count) {
1667                 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1668                 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1669                 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1670                 index++;
1671         }
1672
1673         return iodelay;
1674 }
1675
1676 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32  phandle,
1677                                                    const char *name, int *len)
1678 {
1679         const void *fdt = gd->fdt_blob;
1680         int offset;
1681         const fdt32_t *pinctrl;
1682
1683         offset = fdt_node_offset_by_phandle(fdt, phandle);
1684         if (offset < 0) {
1685                 debug("failed to get pinctrl node %s.\n",
1686                       fdt_strerror(offset));
1687                 return 0;
1688         }
1689
1690         pinctrl = fdt_getprop(fdt, offset, name, len);
1691         if (!pinctrl) {
1692                 debug("failed to get property %s\n", name);
1693                 return 0;
1694         }
1695
1696         return pinctrl;
1697 }
1698
1699 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1700                                                 char *prop_name)
1701 {
1702         const void *fdt = gd->fdt_blob;
1703         const __be32 *phandle;
1704         int node = dev_of_offset(mmc->dev);
1705
1706         phandle = fdt_getprop(fdt, node, prop_name, NULL);
1707         if (!phandle) {
1708                 debug("failed to get property %s\n", prop_name);
1709                 return 0;
1710         }
1711
1712         return fdt32_to_cpu(*phandle);
1713 }
1714
1715 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1716                                                char *prop_name)
1717 {
1718         const void *fdt = gd->fdt_blob;
1719         const __be32 *phandle;
1720         int len;
1721         int count;
1722         int node = dev_of_offset(mmc->dev);
1723
1724         phandle = fdt_getprop(fdt, node, prop_name, &len);
1725         if (!phandle) {
1726                 debug("failed to get property %s\n", prop_name);
1727                 return 0;
1728         }
1729
1730         /* No manual mode iodelay values if count < 2 */
1731         count = len / sizeof(*phandle);
1732         if (count < 2)
1733                 return 0;
1734
1735         return fdt32_to_cpu(*(phandle + 1));
1736 }
1737
1738 static struct pad_conf_entry *
1739 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1740 {
1741         int len;
1742         int count;
1743         struct pad_conf_entry *padconf;
1744         u32 phandle;
1745         const fdt32_t *pinctrl;
1746
1747         phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1748         if (!phandle)
1749                 return ERR_PTR(-EINVAL);
1750
1751         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1752                                                &len);
1753         if (!pinctrl)
1754                 return ERR_PTR(-EINVAL);
1755
1756         count = (len / sizeof(*pinctrl)) / 2;
1757         padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1758         if (!padconf)
1759                 return ERR_PTR(-EINVAL);
1760
1761         *npads = count;
1762
1763         return padconf;
1764 }
1765
1766 static struct iodelay_cfg_entry *
1767 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1768 {
1769         int len;
1770         int count;
1771         struct iodelay_cfg_entry *iodelay;
1772         u32 phandle;
1773         const fdt32_t *pinctrl;
1774
1775         phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1776         /* Not all modes have manual mode iodelay values. So its not fatal */
1777         if (!phandle)
1778                 return 0;
1779
1780         pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1781                                                &len);
1782         if (!pinctrl)
1783                 return ERR_PTR(-EINVAL);
1784
1785         count = (len / sizeof(*pinctrl)) / 3;
1786         iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1787         if (!iodelay)
1788                 return ERR_PTR(-EINVAL);
1789
1790         *niodelay = count;
1791
1792         return iodelay;
1793 }
1794
1795 static struct omap_hsmmc_pinctrl_state *
1796 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1797 {
1798         int index;
1799         int npads = 0;
1800         int niodelays = 0;
1801         const void *fdt = gd->fdt_blob;
1802         int node = dev_of_offset(mmc->dev);
1803         char prop_name[11];
1804         struct omap_hsmmc_pinctrl_state *pinctrl_state;
1805
1806         pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1807                          malloc(sizeof(*pinctrl_state));
1808         if (!pinctrl_state) {
1809                 debug("failed to allocate memory\n");
1810                 return 0;
1811         }
1812
1813         index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1814         if (index < 0) {
1815                 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1816                 goto err_pinctrl_state;
1817         }
1818
1819         sprintf(prop_name, "pinctrl-%d", index);
1820
1821         pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1822                                                          &npads);
1823         if (IS_ERR(pinctrl_state->padconf))
1824                 goto err_pinctrl_state;
1825         pinctrl_state->npads = npads;
1826
1827         pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1828                                                         &niodelays);
1829         if (IS_ERR(pinctrl_state->iodelay))
1830                 goto err_padconf;
1831         pinctrl_state->niodelays = niodelays;
1832
1833         return pinctrl_state;
1834
1835 err_padconf:
1836         kfree(pinctrl_state->padconf);
1837
1838 err_pinctrl_state:
1839         kfree(pinctrl_state);
1840         return 0;
1841 }
1842
1843 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional)               \
1844         do {                                                            \
1845                 struct omap_hsmmc_pinctrl_state *s = NULL;              \
1846                 char str[20];                                           \
1847                 if (!(cfg->host_caps & capmask))                        \
1848                         break;                                          \
1849                                                                         \
1850                 if (priv->hw_rev) {                                     \
1851                         sprintf(str, "%s-%s", #mode, priv->hw_rev);     \
1852                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, str);   \
1853                 }                                                       \
1854                                                                         \
1855                 if (!s)                                                 \
1856                         s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1857                                                                         \
1858                 if (!s && !optional) {                                  \
1859                         debug("%s: no pinctrl for %s\n",                \
1860                               mmc->dev->name, #mode);                   \
1861                         cfg->host_caps &= ~(capmask);                   \
1862                 } else {                                                \
1863                         priv->mode##_pinctrl_state = s;                 \
1864                 }                                                       \
1865         } while (0)
1866
1867 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1868 {
1869         struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1870         struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1871         struct omap_hsmmc_pinctrl_state *default_pinctrl;
1872
1873         if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1874                 return 0;
1875
1876         default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1877         if (!default_pinctrl) {
1878                 printf("no pinctrl state for default mode\n");
1879                 return -EINVAL;
1880         }
1881
1882         priv->default_pinctrl_state = default_pinctrl;
1883
1884         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1885         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1886         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1887         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1888         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1889
1890         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1891         OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1892         OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1893
1894         return 0;
1895 }
1896 #endif
1897
1898 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1899 #ifdef CONFIG_OMAP54XX
1900 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1901 {
1902         return NULL;
1903 }
1904 #endif
1905
1906 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1907 {
1908         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1909         struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1910
1911         struct mmc_config *cfg = &plat->cfg;
1912 #ifdef CONFIG_OMAP54XX
1913         const struct mmc_platform_fixups *fixups;
1914 #endif
1915         const void *fdt = gd->fdt_blob;
1916         int node = dev_of_offset(dev);
1917         int ret;
1918
1919         plat->base_addr = map_physmem(devfdt_get_addr(dev),
1920                                       sizeof(struct hsmmc *),
1921                                       MAP_NOCACHE);
1922
1923         ret = mmc_of_parse(dev, cfg);
1924         if (ret < 0)
1925                 return ret;
1926
1927         if (!cfg->f_max)
1928                 cfg->f_max = 52000000;
1929         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1930         cfg->f_min = 400000;
1931         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1932         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1933         if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1934                 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1935         if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1936                 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1937         if (of_data)
1938                 plat->controller_flags |= of_data->controller_flags;
1939
1940 #ifdef CONFIG_OMAP54XX
1941         fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1942         if (fixups) {
1943                 plat->hw_rev = fixups->hw_rev;
1944                 cfg->host_caps &= ~fixups->unsupported_caps;
1945                 cfg->f_max = fixups->max_freq;
1946         }
1947 #endif
1948
1949         return 0;
1950 }
1951 #endif
1952
1953 #ifdef CONFIG_BLK
1954
1955 static int omap_hsmmc_bind(struct udevice *dev)
1956 {
1957         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1958         plat->mmc = calloc(1, sizeof(struct mmc));
1959         return mmc_bind(dev, plat->mmc, &plat->cfg);
1960 }
1961 #endif
1962 static int omap_hsmmc_probe(struct udevice *dev)
1963 {
1964         struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1965         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1966         struct omap_hsmmc_data *priv = dev_get_priv(dev);
1967         struct mmc_config *cfg = &plat->cfg;
1968         struct mmc *mmc;
1969 #ifdef CONFIG_IODELAY_RECALIBRATION
1970         int ret;
1971 #endif
1972
1973         cfg->name = "OMAP SD/MMC";
1974         priv->base_addr = plat->base_addr;
1975         priv->controller_flags = plat->controller_flags;
1976         priv->hw_rev = plat->hw_rev;
1977
1978 #ifdef CONFIG_BLK
1979         mmc = plat->mmc;
1980 #else
1981         mmc = mmc_create(cfg, priv);
1982         if (mmc == NULL)
1983                 return -1;
1984 #endif
1985 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1986         device_get_supply_regulator(dev, "pbias-supply",
1987                                     &priv->pbias_supply);
1988 #endif
1989 #if defined(OMAP_HSMMC_USE_GPIO)
1990 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1991         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1992         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1993 #endif
1994 #endif
1995
1996         mmc->dev = dev;
1997         upriv->mmc = mmc;
1998
1999 #ifdef CONFIG_IODELAY_RECALIBRATION
2000         ret = omap_hsmmc_get_pinctrl_state(mmc);
2001         /*
2002          * disable high speed modes for the platforms that require IO delay
2003          * and for which we don't have this information
2004          */
2005         if ((ret < 0) &&
2006             (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
2007                 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
2008                 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2009                                     UHS_CAPS);
2010         }
2011 #endif
2012
2013         return omap_hsmmc_init_setup(mmc);
2014 }
2015
2016 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2017
2018 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2019         .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2020 };
2021
2022 static const struct udevice_id omap_hsmmc_ids[] = {
2023         { .compatible = "ti,omap3-hsmmc" },
2024         { .compatible = "ti,omap4-hsmmc" },
2025         { .compatible = "ti,am33xx-hsmmc" },
2026         { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2027         { }
2028 };
2029 #endif
2030
2031 U_BOOT_DRIVER(omap_hsmmc) = {
2032         .name   = "omap_hsmmc",
2033         .id     = UCLASS_MMC,
2034 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2035         .of_match = omap_hsmmc_ids,
2036         .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2037         .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2038 #endif
2039 #ifdef CONFIG_BLK
2040         .bind = omap_hsmmc_bind,
2041 #endif
2042         .ops = &omap_hsmmc_ops,
2043         .probe  = omap_hsmmc_probe,
2044         .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2045 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2046         .flags  = DM_FLAG_PRE_RELOC,
2047 #endif
2048 };
2049 #endif