2 * Freescale i.MX28 SSP MMC driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
11 * Copyright 2007, Freescale Semiconductor, Inc
14 * Based vaguely on the pxa mmc code:
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
18 * See file CREDITS for list of people who contributed to this
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/errno.h>
41 #include <asm/arch/clock.h>
42 #include <asm/arch/imx-regs.h>
43 #include <asm/arch/sys_proto.h>
44 #include <asm/arch/dma.h>
48 struct mx28_ssp_regs *regs;
49 uint32_t clkseq_bypass;
50 uint32_t *clkctrl_ssp;
52 int (*mmc_is_wp)(int);
53 struct mxs_dma_desc *desc;
56 #define MXSMMC_MAX_TIMEOUT 10000
59 * Sends a command out on the bus. Takes the mmc pointer,
60 * a command pointer, and an optional data pointer.
63 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
65 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
66 struct mx28_ssp_regs *ssp_regs = priv->regs;
69 uint32_t data_count, cache_data_count;
72 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
75 timeout = MXSMMC_MAX_TIMEOUT;
78 reg = readl(&ssp_regs->hw_ssp_status);
80 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
81 SSP_STATUS_CMD_BUSY))) {
87 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
91 /* See if card is present */
92 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
93 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
97 /* Start building CTRL0 contents */
98 ctrl0 = priv->buswidth;
101 if (!(cmd->resp_type & MMC_RSP_CRC))
102 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
103 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
104 ctrl0 |= SSP_CTRL0_GET_RESP;
105 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
106 ctrl0 |= SSP_CTRL0_LONG_RESP;
109 reg = readl(&ssp_regs->hw_ssp_cmd0);
110 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
111 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
112 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
113 reg |= SSP_CMD0_APPEND_8CYC;
114 writel(reg, &ssp_regs->hw_ssp_cmd0);
116 /* Command argument */
117 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
122 if (data->flags & MMC_DATA_READ) {
123 ctrl0 |= SSP_CTRL0_READ;
124 } else if (priv->mmc_is_wp(mmc->block_dev.dev)) {
125 printf("MMC%d: Can not write a locked card!\n",
130 ctrl0 |= SSP_CTRL0_DATA_XFER;
131 reg = ((data->blocks - 1) <<
132 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
133 ((ffs(data->blocksize) - 1) <<
134 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
135 writel(reg, &ssp_regs->hw_ssp_block_size);
137 reg = data->blocksize * data->blocks;
138 writel(reg, &ssp_regs->hw_ssp_xfer_size);
141 /* Kick off the command */
142 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
143 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
145 /* Wait for the command to complete */
146 timeout = MXSMMC_MAX_TIMEOUT;
149 reg = readl(&ssp_regs->hw_ssp_status);
150 if (!(reg & SSP_STATUS_CMD_BUSY))
155 printf("MMC%d: Command %d busy\n",
156 mmc->block_dev.dev, cmd->cmdidx);
160 /* Check command timeout */
161 if (reg & SSP_STATUS_RESP_TIMEOUT) {
162 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
163 mmc->block_dev.dev, cmd->cmdidx, reg);
167 /* Check command errors */
168 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
169 printf("MMC%d: Command %d error (status 0x%08x)!\n",
170 mmc->block_dev.dev, cmd->cmdidx, reg);
174 /* Copy response to response buffer */
175 if (cmd->resp_type & MMC_RSP_136) {
176 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
177 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
178 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
179 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
181 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
183 /* Return if no data to process */
187 data_count = data->blocksize * data->blocks;
189 if (data_count % ARCH_DMA_MINALIGN)
190 cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN);
192 cache_data_count = data_count;
194 if (data->flags & MMC_DATA_READ) {
195 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
196 priv->desc->cmd.address = (dma_addr_t)data->dest;
198 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
199 priv->desc->cmd.address = (dma_addr_t)data->src;
201 /* Flush data to DRAM so DMA can pick them up */
202 flush_dcache_range((uint32_t)priv->desc->cmd.address,
203 (uint32_t)(priv->desc->cmd.address + cache_data_count));
206 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
207 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
210 mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc);
211 if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) {
212 printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev);
216 /* The data arrived into DRAM, invalidate cache over them */
217 if (data->flags & MMC_DATA_READ) {
218 invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
219 (uint32_t)(priv->desc->cmd.address + cache_data_count));
222 /* Check data errors */
223 reg = readl(&ssp_regs->hw_ssp_status);
225 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
226 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
227 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
228 mmc->block_dev.dev, cmd->cmdidx, reg);
235 static void mxsmmc_set_ios(struct mmc *mmc)
237 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
238 struct mx28_ssp_regs *ssp_regs = priv->regs;
240 /* Set the clock speed */
242 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000);
244 switch (mmc->bus_width) {
246 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
249 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
252 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
256 /* Set the bus width */
257 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
258 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
260 debug("MMC%d: Set %d bits bus width\n",
261 mmc->block_dev.dev, mmc->bus_width);
264 static int mxsmmc_init(struct mmc *mmc)
266 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
267 struct mx28_ssp_regs *ssp_regs = priv->regs;
270 mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
272 /* 8 bits word length in MMC mode */
273 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
274 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK,
275 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
276 SSP_CTRL1_DMA_ENABLE);
278 /* Set initial bit clock 400 KHz */
279 mx28_set_ssp_busclock(priv->id, 400);
281 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
282 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
284 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
289 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
291 struct mx28_clkctrl_regs *clkctrl_regs =
292 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
293 struct mmc *mmc = NULL;
294 struct mxsmmc_priv *priv = NULL;
296 mmc = malloc(sizeof(struct mmc));
300 priv = malloc(sizeof(struct mxsmmc_priv));
306 priv->desc = mxs_dma_desc_alloc();
313 priv->mmc_is_wp = wp;
317 priv->regs = (struct mx28_ssp_regs *)MXS_SSP0_BASE;
318 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
319 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
322 priv->regs = (struct mx28_ssp_regs *)MXS_SSP1_BASE;
323 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
324 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
327 priv->regs = (struct mx28_ssp_regs *)MXS_SSP2_BASE;
328 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
329 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
332 priv->regs = (struct mx28_ssp_regs *)MXS_SSP3_BASE;
333 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
334 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
338 sprintf(mmc->name, "MXS MMC");
339 mmc->send_cmd = mxsmmc_send_cmd;
340 mmc->set_ios = mxsmmc_set_ios;
341 mmc->init = mxsmmc_init;
345 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
347 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
348 MMC_MODE_HS_52MHz | MMC_MODE_HS;
351 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
352 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
353 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
354 * CLOCK_RATE could be any integer from 0 to 255.
357 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;