2 * Freescale i.MX28 SSP MMC driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
11 * Copyright 2007, Freescale Semiconductor, Inc
14 * Based vaguely on the pxa mmc code:
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
18 * See file CREDITS for list of people who contributed to this
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 #include <asm/errno.h>
41 #include <asm/arch/clock.h>
42 #include <asm/arch/imx-regs.h>
43 #include <asm/arch/sys_proto.h>
47 struct mx28_ssp_regs *regs;
48 uint32_t clkseq_bypass;
49 uint32_t *clkctrl_ssp;
51 int (*mmc_is_wp)(int);
54 #define MXSMMC_MAX_TIMEOUT 10000
57 * Sends a command out on the bus. Takes the mmc pointer,
58 * a command pointer, and an optional data pointer.
61 mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
63 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
64 struct mx28_ssp_regs *ssp_regs = priv->regs;
71 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
74 timeout = MXSMMC_MAX_TIMEOUT;
77 reg = readl(&ssp_regs->hw_ssp_status);
79 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
80 SSP_STATUS_CMD_BUSY))) {
86 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
90 /* See if card is present */
91 if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
92 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
96 /* Start building CTRL0 contents */
97 ctrl0 = priv->buswidth;
100 if (!(cmd->resp_type & MMC_RSP_CRC))
101 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
102 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
103 ctrl0 |= SSP_CTRL0_GET_RESP;
104 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
105 ctrl0 |= SSP_CTRL0_LONG_RESP;
108 reg = readl(&ssp_regs->hw_ssp_cmd0);
109 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
110 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
111 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
112 reg |= SSP_CMD0_APPEND_8CYC;
113 writel(reg, &ssp_regs->hw_ssp_cmd0);
115 /* Command argument */
116 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
121 if (data->flags & MMC_DATA_READ) {
122 ctrl0 |= SSP_CTRL0_READ;
123 } else if (priv->mmc_is_wp(mmc->block_dev.dev)) {
124 printf("MMC%d: Can not write a locked card!\n",
129 ctrl0 |= SSP_CTRL0_DATA_XFER;
130 reg = ((data->blocks - 1) <<
131 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
132 ((ffs(data->blocksize) - 1) <<
133 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
134 writel(reg, &ssp_regs->hw_ssp_block_size);
136 reg = data->blocksize * data->blocks;
137 writel(reg, &ssp_regs->hw_ssp_xfer_size);
140 /* Kick off the command */
141 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
142 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
144 /* Wait for the command to complete */
145 timeout = MXSMMC_MAX_TIMEOUT;
148 reg = readl(&ssp_regs->hw_ssp_status);
149 if (!(reg & SSP_STATUS_CMD_BUSY))
154 printf("MMC%d: Command %d busy\n",
155 mmc->block_dev.dev, cmd->cmdidx);
159 /* Check command timeout */
160 if (reg & SSP_STATUS_RESP_TIMEOUT) {
161 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
162 mmc->block_dev.dev, cmd->cmdidx, reg);
166 /* Check command errors */
167 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
168 printf("MMC%d: Command %d error (status 0x%08x)!\n",
169 mmc->block_dev.dev, cmd->cmdidx, reg);
173 /* Copy response to response buffer */
174 if (cmd->resp_type & MMC_RSP_136) {
175 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
176 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
177 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
178 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
180 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
182 /* Return if no data to process */
186 /* Process the data */
187 data_count = data->blocksize * data->blocks;
188 timeout = MXSMMC_MAX_TIMEOUT;
189 if (data->flags & MMC_DATA_READ) {
190 data_ptr = (uint32_t *)data->dest;
191 while (data_count && --timeout) {
192 reg = readl(&ssp_regs->hw_ssp_status);
193 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
194 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
196 timeout = MXSMMC_MAX_TIMEOUT;
201 data_ptr = (uint32_t *)data->src;
203 while (data_count && --timeout) {
204 reg = readl(&ssp_regs->hw_ssp_status);
205 if (!(reg & SSP_STATUS_FIFO_FULL)) {
206 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
208 timeout = MXSMMC_MAX_TIMEOUT;
215 printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n",
216 mmc->block_dev.dev, cmd->cmdidx, reg);
220 /* Check data errors */
221 reg = readl(&ssp_regs->hw_ssp_status);
223 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
224 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
225 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
226 mmc->block_dev.dev, cmd->cmdidx, reg);
233 static void mxsmmc_set_ios(struct mmc *mmc)
235 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
236 struct mx28_ssp_regs *ssp_regs = priv->regs;
238 /* Set the clock speed */
240 mx28_set_ssp_busclock(priv->id, mmc->clock / 1000);
242 switch (mmc->bus_width) {
244 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
247 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
250 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
254 /* Set the bus width */
255 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
256 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
258 debug("MMC%d: Set %d bits bus width\n",
259 mmc->block_dev.dev, mmc->bus_width);
262 static int mxsmmc_init(struct mmc *mmc)
264 struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
265 struct mx28_ssp_regs *ssp_regs = priv->regs;
268 mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
270 /* 8 bits word length in MMC mode */
271 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
272 SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK,
273 SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
275 /* Set initial bit clock 400 KHz */
276 mx28_set_ssp_busclock(priv->id, 400);
278 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
279 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
281 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
286 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
288 struct mx28_clkctrl_regs *clkctrl_regs =
289 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
290 struct mmc *mmc = NULL;
291 struct mxsmmc_priv *priv = NULL;
293 mmc = malloc(sizeof(struct mmc));
297 priv = malloc(sizeof(struct mxsmmc_priv));
303 priv->mmc_is_wp = wp;
307 priv->regs = (struct mx28_ssp_regs *)MXS_SSP0_BASE;
308 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
309 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
312 priv->regs = (struct mx28_ssp_regs *)MXS_SSP1_BASE;
313 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
314 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
317 priv->regs = (struct mx28_ssp_regs *)MXS_SSP2_BASE;
318 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
319 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
322 priv->regs = (struct mx28_ssp_regs *)MXS_SSP3_BASE;
323 priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
324 priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
328 sprintf(mmc->name, "MXS MMC");
329 mmc->send_cmd = mxsmmc_send_cmd;
330 mmc->set_ios = mxsmmc_set_ios;
331 mmc->init = mxsmmc_init;
334 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
336 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
337 MMC_MODE_HS_52MHz | MMC_MODE_HS;
340 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
341 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
342 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
343 * CLOCK_RATE could be any integer from 0 to 255.
346 mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;