2 * Marvell MMC/SD/SDIO driver
4 * (C) Copyright 2012-2014
5 * Marvell Semiconductor <www.marvell.com>
6 * Written-by: Maen Suleiman, Gerald Kerma
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/soc.h>
19 #include <mvebu_mmc.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 #define DRIVER_NAME "MVEBU_MMC"
25 #define MVEBU_TARGET_DRAM 0
27 #define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */
29 static void mvebu_mmc_write(u32 offs, u32 val)
31 writel(val, CONFIG_SYS_MMC_BASE + (offs));
34 static u32 mvebu_mmc_read(u32 offs)
36 return readl(CONFIG_SYS_MMC_BASE + (offs));
39 static int mvebu_mmc_setup_data(struct mmc_data *data)
43 debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
44 (data->flags & MMC_DATA_READ) ? "read" : "write",
45 data->blocks, data->blocksize);
47 /* default to maximum timeout */
48 ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
49 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
50 mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
52 if (data->flags & MMC_DATA_READ) {
53 mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
54 mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
56 mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
57 mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
60 mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);
61 mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);
66 static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
67 struct mmc_data *data)
75 debug("%s: cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
76 DRIVER_NAME, cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
78 debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
79 cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
82 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
83 * register is sometimes not set before a while when some
84 * "unusual" data block sizes are used (such as with the SWITCH
85 * command), even despite the fact that the XFER_DONE interrupt
86 * was raised. And if another data transfer starts before
87 * this bit comes to good sense (which eventually happens by
88 * itself) then the new transfer simply fails with a timeout.
90 if (!(mvebu_mmc_read(SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
91 ushort hw_state, count = 0;
95 hw_state = mvebu_mmc_read(SDIO_HW_STATE);
96 if ((get_timer(0) - start) > TIMEOUT_DELAY) {
97 printf("%s : FIFO_EMPTY bit missing\n",
102 } while (!(hw_state & CMD_FIFO_EMPTY));
103 debug("%s *** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
104 DRIVER_NAME, hw_state, count, (get_timer(0) - (start)));
108 mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
109 mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
111 resptype = SDIO_CMD_INDEX(cmd->cmdidx);
113 /* Analyzing resptype/xfertype/waittype for the command */
114 if (cmd->resp_type & MMC_RSP_BUSY)
115 resptype |= SDIO_CMD_RSP_48BUSY;
116 else if (cmd->resp_type & MMC_RSP_136)
117 resptype |= SDIO_CMD_RSP_136;
118 else if (cmd->resp_type & MMC_RSP_PRESENT)
119 resptype |= SDIO_CMD_RSP_48;
121 resptype |= SDIO_CMD_RSP_NONE;
123 if (cmd->resp_type & MMC_RSP_CRC)
124 resptype |= SDIO_CMD_CHECK_CMDCRC;
126 if (cmd->resp_type & MMC_RSP_OPCODE)
127 resptype |= SDIO_CMD_INDX_CHECK;
129 if (cmd->resp_type & MMC_RSP_PRESENT) {
130 resptype |= SDIO_UNEXPECTED_RESP;
131 waittype |= SDIO_NOR_UNEXP_RSP;
135 int err = mvebu_mmc_setup_data(data);
138 debug("%s: command DATA error :%x\n",
143 resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
144 xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
145 if (data->flags & MMC_DATA_READ) {
146 xfertype |= SDIO_XFER_MODE_TO_HOST;
147 waittype = SDIO_NOR_DMA_INI;
149 waittype |= SDIO_NOR_XFER_DONE;
152 waittype |= SDIO_NOR_CMD_DONE;
155 /* Setting cmd arguments */
156 mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
157 mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
159 /* Setting Xfer mode */
160 mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
162 /* Sending command */
163 mvebu_mmc_write(SDIO_CMD, resptype);
165 start = get_timer(0);
167 while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
168 if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
169 debug("%s: error! cmdidx : %d, err reg: %04x\n",
170 DRIVER_NAME, cmd->cmdidx,
171 mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
172 if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
173 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
174 debug("%s: command READ timed out\n",
178 debug("%s: command READ error\n", DRIVER_NAME);
182 if ((get_timer(0) - start) > TIMEOUT_DELAY) {
183 debug("%s: command timed out\n", DRIVER_NAME);
188 /* Handling response */
189 if (cmd->resp_type & MMC_RSP_136) {
192 for (resp_indx = 0; resp_indx < 8; resp_indx++)
194 = mvebu_mmc_read(SDIO_RSP(resp_indx));
196 cmd->response[0] = ((response[0] & 0x03ff) << 22) |
197 ((response[1] & 0xffff) << 6) |
198 ((response[2] & 0xfc00) >> 10);
199 cmd->response[1] = ((response[2] & 0x03ff) << 22) |
200 ((response[3] & 0xffff) << 6) |
201 ((response[4] & 0xfc00) >> 10);
202 cmd->response[2] = ((response[4] & 0x03ff) << 22) |
203 ((response[5] & 0xffff) << 6) |
204 ((response[6] & 0xfc00) >> 10);
205 cmd->response[3] = ((response[6] & 0x03ff) << 22) |
206 ((response[7] & 0x3fff) << 8);
207 } else if (cmd->resp_type & MMC_RSP_PRESENT) {
210 for (resp_indx = 0; resp_indx < 3; resp_indx++)
212 = mvebu_mmc_read(SDIO_RSP(resp_indx));
214 cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
215 ((response[1] & 0xffff) << (14 - 8)) |
216 ((response[0] & 0x03ff) << (30 - 8));
217 cmd->response[1] = ((response[0] & 0xfc00) >> 10);
218 cmd->response[2] = 0;
219 cmd->response[3] = 0;
221 cmd->response[0] = 0;
222 cmd->response[1] = 0;
223 cmd->response[2] = 0;
224 cmd->response[3] = 0;
227 debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
228 debug("[0x%x] ", cmd->response[0]);
229 debug("[0x%x] ", cmd->response[1]);
230 debug("[0x%x] ", cmd->response[2]);
231 debug("[0x%x] ", cmd->response[3]);
234 if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
235 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
241 static void mvebu_mmc_power_up(void)
243 debug("%s: power up\n", DRIVER_NAME);
245 /* disable interrupts */
246 mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
247 mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
250 mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
252 mvebu_mmc_write(SDIO_XFER_MODE, 0);
255 mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
256 mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
258 /* enable interrupts status */
259 mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
260 mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
263 static void mvebu_mmc_set_clk(unsigned int clock)
268 debug("%s: clock off\n", DRIVER_NAME);
269 mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
270 mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
272 m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
273 if (m > MVEBU_MMC_BASE_DIV_MAX)
274 m = MVEBU_MMC_BASE_DIV_MAX;
275 mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
276 debug("%s: clock (%d) div : %d\n", DRIVER_NAME, clock, m);
280 static void mvebu_mmc_set_bus(unsigned int bus)
284 ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
285 ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
289 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
293 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
296 /* default transfer mode */
297 ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
298 ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
300 /* default to maximum timeout */
301 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
302 ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN;
304 ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
306 ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
308 debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
309 (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
310 "push-pull" : "open-drain",
311 (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
312 "4bit-width" : "1bit-width",
313 (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
316 mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
319 static int mvebu_mmc_set_ios(struct mmc *mmc)
321 debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,
322 mmc->bus_width, mmc->clock);
323 mvebu_mmc_set_bus(mmc->bus_width);
324 mvebu_mmc_set_clk(mmc->clock);
330 * Set window register.
332 static void mvebu_window_setup(void)
336 for (i = 0; i < 4; i++) {
337 mvebu_mmc_write(WINDOW_CTRL(i), 0);
338 mvebu_mmc_write(WINDOW_BASE(i), 0);
340 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
341 u32 size, base, attrib;
343 /* Enable DRAM bank */
346 attrib = KWCPU_ATTR_DRAM_CS0;
349 attrib = KWCPU_ATTR_DRAM_CS1;
352 attrib = KWCPU_ATTR_DRAM_CS2;
355 attrib = KWCPU_ATTR_DRAM_CS3;
358 /* invalide bank, disable access */
363 size = gd->bd->bi_dram[i].size;
364 base = gd->bd->bi_dram[i].start;
365 if (size && attrib) {
366 mvebu_mmc_write(WINDOW_CTRL(i),
367 MVCPU_WIN_CTRL_DATA(size,
372 mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
374 mvebu_mmc_write(WINDOW_BASE(i), base);
378 static int mvebu_mmc_initialize(struct mmc *mmc)
380 debug("%s: mvebu_mmc_initialize\n", DRIVER_NAME);
383 * Setting host parameters
384 * Initial Host Ctrl : Timeout : max , Normal Speed mode,
385 * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
387 mvebu_mmc_write(SDIO_HOST_CTRL,
388 SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
389 SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
390 SDIO_HOST_CTRL_BIG_ENDIAN |
391 SDIO_HOST_CTRL_PUSH_PULL_EN |
392 SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
394 mvebu_mmc_write(SDIO_CLK_CTRL, 0);
397 mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
398 mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
400 /* disable interrupts */
401 mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
402 mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
404 mvebu_window_setup();
407 mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
412 static const struct mmc_ops mvebu_mmc_ops = {
413 .send_cmd = mvebu_mmc_send_cmd,
414 .set_ios = mvebu_mmc_set_ios,
415 .init = mvebu_mmc_initialize,
418 static struct mmc_config mvebu_mmc_cfg = {
420 .ops = &mvebu_mmc_ops,
421 .f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
422 .f_max = MVEBU_MMC_CLOCKRATE_MAX,
423 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
424 .host_caps = MMC_MODE_4BIT | MMC_MODE_HS |
426 .part_type = PART_TYPE_DOS,
427 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
430 int mvebu_mmc_init(bd_t *bis)
434 mvebu_mmc_power_up();
436 mmc = mmc_create(&mvebu_mmc_cfg, bis);