1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek SD/MMC Card Interface driver
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
17 #include <dm/pinctrl.h>
18 #include <linux/bitops.h>
20 #include <linux/iopoll.h>
23 #define MSDC_CFG_HS400_CK_MODE_EXT BIT(22)
24 #define MSDC_CFG_CKMOD_EXT_M 0x300000
25 #define MSDC_CFG_CKMOD_EXT_S 20
26 #define MSDC_CFG_CKDIV_EXT_M 0xfff00
27 #define MSDC_CFG_CKDIV_EXT_S 8
28 #define MSDC_CFG_HS400_CK_MODE BIT(18)
29 #define MSDC_CFG_CKMOD_M 0x30000
30 #define MSDC_CFG_CKMOD_S 16
31 #define MSDC_CFG_CKDIV_M 0xff00
32 #define MSDC_CFG_CKDIV_S 8
33 #define MSDC_CFG_CKSTB BIT(7)
34 #define MSDC_CFG_PIO BIT(3)
35 #define MSDC_CFG_RST BIT(2)
36 #define MSDC_CFG_CKPDN BIT(1)
37 #define MSDC_CFG_MODE BIT(0)
40 #define MSDC_IOCON_W_DSPL BIT(8)
41 #define MSDC_IOCON_DSPL BIT(2)
42 #define MSDC_IOCON_RSPL BIT(1)
45 #define MSDC_PS_DAT0 BIT(16)
46 #define MSDC_PS_CDDBCE_M 0xf000
47 #define MSDC_PS_CDDBCE_S 12
48 #define MSDC_PS_CDSTS BIT(1)
49 #define MSDC_PS_CDEN BIT(0)
51 /* #define MSDC_INT(EN) */
52 #define MSDC_INT_ACMDRDY BIT(3)
53 #define MSDC_INT_ACMDTMO BIT(4)
54 #define MSDC_INT_ACMDCRCERR BIT(5)
55 #define MSDC_INT_CMDRDY BIT(8)
56 #define MSDC_INT_CMDTMO BIT(9)
57 #define MSDC_INT_RSPCRCERR BIT(10)
58 #define MSDC_INT_XFER_COMPL BIT(12)
59 #define MSDC_INT_DATTMO BIT(14)
60 #define MSDC_INT_DATCRCERR BIT(15)
63 #define MSDC_FIFOCS_CLR BIT(31)
64 #define MSDC_FIFOCS_TXCNT_M 0xff0000
65 #define MSDC_FIFOCS_TXCNT_S 16
66 #define MSDC_FIFOCS_RXCNT_M 0xff
67 #define MSDC_FIFOCS_RXCNT_S 0
70 #define SDC_CFG_DTOC_M 0xff000000
71 #define SDC_CFG_DTOC_S 24
72 #define SDC_CFG_SDIOIDE BIT(20)
73 #define SDC_CFG_SDIO BIT(19)
74 #define SDC_CFG_BUSWIDTH_M 0x30000
75 #define SDC_CFG_BUSWIDTH_S 16
78 #define SDC_CMD_BLK_LEN_M 0xfff0000
79 #define SDC_CMD_BLK_LEN_S 16
80 #define SDC_CMD_STOP BIT(14)
81 #define SDC_CMD_WR BIT(13)
82 #define SDC_CMD_DTYPE_M 0x1800
83 #define SDC_CMD_DTYPE_S 11
84 #define SDC_CMD_RSPTYP_M 0x380
85 #define SDC_CMD_RSPTYP_S 7
86 #define SDC_CMD_CMD_M 0x3f
87 #define SDC_CMD_CMD_S 0
90 #define SDC_STS_CMDBUSY BIT(1)
91 #define SDC_STS_SDCBUSY BIT(0)
94 #define SDC_RX_ENHANCE_EN BIT(20)
97 #define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380
98 #define MSDC_INT_DAT_LATCH_CK_SEL_S 7
101 #define MSDC_PB1_STOP_DLY_M 0xf00
102 #define MSDC_PB1_STOP_DLY_S 8
105 #define MSDC_PB2_CRCSTSENSEL_M 0xe0000000
106 #define MSDC_PB2_CRCSTSENSEL_S 29
107 #define MSDC_PB2_CFGCRCSTS BIT(28)
108 #define MSDC_PB2_RESPSTSENSEL_M 0x70000
109 #define MSDC_PB2_RESPSTSENSEL_S 16
110 #define MSDC_PB2_CFGRESP BIT(15)
111 #define MSDC_PB2_RESPWAIT_M 0x0c
112 #define MSDC_PB2_RESPWAIT_S 2
115 #define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000
116 #define MSDC_PAD_TUNE_CMDRRDLY_S 22
117 #define MSDC_PAD_TUNE_CMD_SEL BIT(21)
118 #define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000
119 #define MSDC_PAD_TUNE_CMDRDLY_S 16
120 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15)
121 #define MSDC_PAD_TUNE_RD_SEL BIT(13)
122 #define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00
123 #define MSDC_PAD_TUNE_DATRRDLY_S 8
124 #define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
125 #define MSDC_PAD_TUNE_DATWRDLY_S 0
128 #define EMMC50_CFG_CFCSTS_SEL BIT(4)
131 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24)
132 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25)
134 /* SDC_CFG_BUSWIDTH */
135 #define MSDC_BUS_1BITS 0x0
136 #define MSDC_BUS_4BITS 0x1
137 #define MSDC_BUS_8BITS 0x2
139 #define MSDC_FIFO_SIZE 128
141 #define PAD_DELAY_MAX 32
143 #define DEFAULT_CD_DEBOUNCE 8
145 #define CMD_INTS_MASK \
146 (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
148 #define DATA_INTS_MASK \
149 (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
151 /* Register offset */
217 struct msdc_compatible {
227 struct msdc_delay_phase {
234 struct mmc_config cfg;
238 struct msdc_tune_para {
244 struct mtk_sd_regs *base;
247 struct msdc_compatible *dev_comp;
249 struct clk src_clk; /* for SD/MMC bus clock */
250 struct clk src_clk_cg; /* optional, MSDC source clock control gate */
251 struct clk h_clk; /* MSDC core clock */
253 u32 src_clk_freq; /* source clock */
254 u32 mclk; /* mmc framework required bus clock */
255 u32 sclk; /* actual calculated bus clock */
257 /* operation timeout clocks */
263 u32 hs200_cmd_int_delay;
264 u32 hs200_write_int_delay;
266 u32 r_smpl; /* sample edge */
269 /* whether to use gpio detection or built-in hw detection */
272 /* card detection / write protection GPIOs */
273 #if IS_ENABLED(DM_GPIO)
274 struct gpio_desc gpio_wp;
275 struct gpio_desc gpio_cd;
279 uint last_data_write;
281 enum bus_mode timing;
283 struct msdc_tune_para def_tune_para;
284 struct msdc_tune_para saved_tune_para;
287 static void msdc_reset_hw(struct msdc_host *host)
291 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
293 readl_poll_timeout(&host->base->msdc_cfg, reg,
294 !(reg & MSDC_CFG_RST), 1000000);
297 static void msdc_fifo_clr(struct msdc_host *host)
301 setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
303 readl_poll_timeout(&host->base->msdc_fifocs, reg,
304 !(reg & MSDC_FIFOCS_CLR), 1000000);
307 static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
309 return (readl(&host->base->msdc_fifocs) &
310 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
313 static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
315 return (readl(&host->base->msdc_fifocs) &
316 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
319 static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
323 switch (cmd->resp_type) {
324 /* Actually, R1, R5, R6, R7 are the same */
346 static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
348 struct mmc_data *data)
350 u32 opcode = cmd->cmdidx;
351 u32 resp_type = msdc_cmd_find_resp(host, cmd);
357 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
358 case MMC_CMD_READ_MULTIPLE_BLOCK:
361 case MMC_CMD_WRITE_SINGLE_BLOCK:
362 case MMC_CMD_READ_SINGLE_BLOCK:
363 case SD_CMD_APP_SEND_SCR:
366 case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
367 case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
368 case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
374 if (data->flags == MMC_DATA_WRITE)
375 rawcmd |= SDC_CMD_WR;
377 if (data->blocks > 1)
380 blocksize = data->blocksize;
383 rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
384 ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
385 ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
386 ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
388 if (opcode == MMC_CMD_STOP_TRANSMISSION)
389 rawcmd |= SDC_CMD_STOP;
394 static int msdc_cmd_done(struct msdc_host *host, int events,
397 u32 *rsp = cmd->response;
400 if (cmd->resp_type & MMC_RSP_PRESENT) {
401 if (cmd->resp_type & MMC_RSP_136) {
402 rsp[0] = readl(&host->base->sdc_resp[3]);
403 rsp[1] = readl(&host->base->sdc_resp[2]);
404 rsp[2] = readl(&host->base->sdc_resp[1]);
405 rsp[3] = readl(&host->base->sdc_resp[0]);
407 rsp[0] = readl(&host->base->sdc_resp[0]);
411 if (!(events & MSDC_INT_CMDRDY)) {
412 if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
413 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
415 * should not clear fifo/interrupt as the tune data
416 * may have alreay come.
420 if (events & MSDC_INT_CMDTMO)
429 static bool msdc_cmd_is_ready(struct msdc_host *host)
434 /* The max busy time we can endure is 20ms */
435 ret = readl_poll_timeout(&host->base->sdc_sts, reg,
436 !(reg & SDC_STS_CMDBUSY), 20000);
439 pr_err("CMD bus busy detected\n");
444 if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
445 ret = readl_poll_timeout(&host->base->msdc_ps, reg,
446 reg & MSDC_PS_DAT0, 1000000);
449 pr_err("Card stuck in programming state!\n");
458 static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
459 struct mmc_data *data)
466 if (!msdc_cmd_is_ready(host))
471 host->last_resp_type = cmd->resp_type;
472 host->last_data_write = 0;
474 rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
477 blocks = data->blocks;
479 writel(CMD_INTS_MASK, &host->base->msdc_int);
480 writel(blocks, &host->base->sdc_blk_num);
481 writel(cmd->cmdarg, &host->base->sdc_arg);
482 writel(rawcmd, &host->base->sdc_cmd);
484 ret = readl_poll_timeout(&host->base->msdc_int, status,
485 status & CMD_INTS_MASK, 1000000);
488 status = MSDC_INT_CMDTMO;
490 return msdc_cmd_done(host, status, cmd);
493 static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
497 while ((size_t)buf % 4) {
498 *buf++ = readb(&host->base->msdc_rxdata);
504 *wbuf++ = readl(&host->base->msdc_rxdata);
510 *buf++ = readb(&host->base->msdc_rxdata);
515 static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
519 while ((size_t)buf % 4) {
520 writeb(*buf++, &host->base->msdc_txdata);
524 wbuf = (const u32 *)buf;
526 writel(*wbuf++, &host->base->msdc_txdata);
530 buf = (const u8 *)wbuf;
532 writeb(*buf++, &host->base->msdc_txdata);
537 static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
544 status = readl(&host->base->msdc_int);
545 writel(status, &host->base->msdc_int);
546 status &= DATA_INTS_MASK;
548 if (status & MSDC_INT_DATCRCERR) {
553 if (status & MSDC_INT_DATTMO) {
558 chksz = min(size, (u32)MSDC_FIFO_SIZE);
560 if (msdc_fifo_rx_bytes(host) >= chksz) {
561 msdc_fifo_read(host, ptr, chksz);
566 if (status & MSDC_INT_XFER_COMPL) {
568 pr_err("data not fully read\n");
579 static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
586 status = readl(&host->base->msdc_int);
587 writel(status, &host->base->msdc_int);
588 status &= DATA_INTS_MASK;
590 if (status & MSDC_INT_DATCRCERR) {
595 if (status & MSDC_INT_DATTMO) {
600 if (status & MSDC_INT_XFER_COMPL) {
602 pr_err("data not fully written\n");
609 chksz = min(size, (u32)MSDC_FIFO_SIZE);
611 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
612 msdc_fifo_write(host, ptr, chksz);
621 static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
626 if (data->flags == MMC_DATA_WRITE)
627 host->last_data_write = 1;
629 writel(DATA_INTS_MASK, &host->base->msdc_int);
631 size = data->blocks * data->blocksize;
633 if (data->flags == MMC_DATA_WRITE)
634 ret = msdc_pio_write(host, (const u8 *)data->src, size);
636 ret = msdc_pio_read(host, (u8 *)data->dest, size);
646 static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
647 struct mmc_data *data)
649 struct msdc_host *host = dev_get_priv(dev);
652 ret = msdc_start_command(host, cmd, data);
657 return msdc_start_data(host, data);
662 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
667 host->timeout_ns = ns;
668 host->timeout_clks = clks;
670 if (host->sclk == 0) {
673 clk_ns = 1000000000UL / host->sclk;
674 timeout = (ns + clk_ns - 1) / clk_ns + clks;
675 /* unit is 1048576 sclk cycles */
676 timeout = (timeout + (0x1 << 20) - 1) >> 20;
677 if (host->dev_comp->clk_div_bits == 8)
678 mode = (readl(&host->base->msdc_cfg) &
679 MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
681 mode = (readl(&host->base->msdc_cfg) &
682 MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
683 /* DDR mode will double the clk cycles for data timeout */
684 timeout = mode >= 2 ? timeout * 2 : timeout;
685 timeout = timeout > 1 ? timeout - 1 : 0;
686 timeout = timeout > 255 ? 255 : timeout;
689 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
690 timeout << SDC_CFG_DTOC_S);
693 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
695 u32 val = readl(&host->base->sdc_cfg);
697 val &= ~SDC_CFG_BUSWIDTH_M;
702 val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
705 val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
708 val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
712 writel(val, &host->base->sdc_cfg);
715 static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz)
724 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
728 if (host->dev_comp->clk_div_bits == 8)
729 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
731 clrbits_le32(&host->base->msdc_cfg,
732 MSDC_CFG_HS400_CK_MODE_EXT);
734 if (timing == UHS_DDR50 || timing == MMC_DDR_52 ||
735 timing == MMC_HS_400) {
736 if (timing == MMC_HS_400)
739 mode = 0x2; /* ddr mode and use divisor */
741 if (hz >= (host->src_clk_freq >> 2)) {
742 div = 0; /* mean div = 1/4 */
743 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
745 div = (host->src_clk_freq + ((hz << 2) - 1)) /
747 sclk = (host->src_clk_freq >> 2) / div;
751 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
752 if (host->dev_comp->clk_div_bits == 8)
753 setbits_le32(&host->base->msdc_cfg,
754 MSDC_CFG_HS400_CK_MODE);
756 setbits_le32(&host->base->msdc_cfg,
757 MSDC_CFG_HS400_CK_MODE_EXT);
759 sclk = host->src_clk_freq >> 1;
760 div = 0; /* div is ignore when bit18 is set */
762 } else if (hz >= host->src_clk_freq) {
763 mode = 0x1; /* no divisor */
765 sclk = host->src_clk_freq;
767 mode = 0x0; /* use divisor */
768 if (hz >= (host->src_clk_freq >> 1)) {
769 div = 0; /* mean div = 1/2 */
770 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
772 div = (host->src_clk_freq + ((hz << 2) - 1)) /
774 sclk = (host->src_clk_freq >> 2) / div;
778 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
780 if (host->dev_comp->clk_div_bits == 8) {
781 div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
782 clrsetbits_le32(&host->base->msdc_cfg,
783 MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
784 (mode << MSDC_CFG_CKMOD_S) |
785 (div << MSDC_CFG_CKDIV_S));
787 div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
788 MSDC_CFG_CKDIV_EXT_S));
789 clrsetbits_le32(&host->base->msdc_cfg,
790 MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
791 (mode << MSDC_CFG_CKMOD_EXT_S) |
792 (div << MSDC_CFG_CKDIV_EXT_S));
795 readl_poll_timeout(&host->base->msdc_cfg, reg,
796 reg & MSDC_CFG_CKSTB, 1000000);
798 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
801 host->timing = timing;
803 /* needed because clk changed. */
804 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
807 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
808 * tune result of hs200/200Mhz is not suitable for 50Mhz
810 if (host->sclk <= 52000000) {
811 writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
812 writel(host->def_tune_para.pad_tune,
813 &host->base->pad_tune);
815 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
816 writel(host->saved_tune_para.pad_tune,
817 &host->base->pad_tune);
820 dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
823 static int msdc_ops_set_ios(struct udevice *dev)
825 struct msdc_plat *plat = dev_get_platdata(dev);
826 struct msdc_host *host = dev_get_priv(dev);
827 struct mmc *mmc = &plat->mmc;
828 uint clock = mmc->clock;
830 msdc_set_buswidth(host, mmc->bus_width);
832 if (mmc->clk_disable)
834 else if (clock < mmc->cfg->f_min)
835 clock = mmc->cfg->f_min;
837 if (host->mclk != clock || host->timing != mmc->selected_mode)
838 msdc_set_mclk(host, mmc->selected_mode, clock);
843 static int msdc_ops_get_cd(struct udevice *dev)
845 struct msdc_host *host = dev_get_priv(dev);
848 if (host->builtin_cd) {
849 val = readl(&host->base->msdc_ps);
850 return !(val & MSDC_PS_CDSTS);
853 #if IS_ENABLED(DM_GPIO)
854 if (!host->gpio_cd.dev)
857 return dm_gpio_get_value(&host->gpio_cd);
863 static int msdc_ops_get_wp(struct udevice *dev)
865 #if IS_ENABLED(DM_GPIO)
866 struct msdc_host *host = dev_get_priv(dev);
868 if (!host->gpio_wp.dev)
871 return !dm_gpio_get_value(&host->gpio_wp);
877 #ifdef MMC_SUPPORTS_TUNING
878 static u32 test_delay_bit(u32 delay, u32 bit)
880 bit %= PAD_DELAY_MAX;
881 return delay & (1 << bit);
884 static int get_delay_len(u32 delay, u32 start_bit)
888 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
889 if (test_delay_bit(delay, start_bit + i) == 0)
893 return PAD_DELAY_MAX - start_bit;
896 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
898 int start = 0, len = 0;
899 int start_final = 0, len_final = 0;
900 u8 final_phase = 0xff;
901 struct msdc_delay_phase delay_phase = { 0, };
904 dev_err(dev, "phase error: [map:%x]\n", delay);
905 delay_phase.final_phase = final_phase;
909 while (start < PAD_DELAY_MAX) {
910 len = get_delay_len(delay, start);
911 if (len_final < len) {
916 start += len ? len : 1;
917 if (len >= 12 && start_final < 4)
921 /* The rule is to find the smallest delay cell */
922 if (start_final == 0)
923 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
925 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
927 dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
928 delay, len_final, final_phase);
930 delay_phase.maxlen = len_final;
931 delay_phase.start = start_final;
932 delay_phase.final_phase = final_phase;
936 static int msdc_tune_response(struct udevice *dev, u32 opcode)
938 struct msdc_plat *plat = dev_get_platdata(dev);
939 struct msdc_host *host = dev_get_priv(dev);
940 struct mmc *mmc = &plat->mmc;
941 u32 rise_delay = 0, fall_delay = 0;
942 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
943 struct msdc_delay_phase internal_delay_phase;
944 u8 final_delay, final_maxlen;
945 u32 internal_delay = 0;
946 void __iomem *tune_reg = &host->base->pad_tune;
950 if (host->dev_comp->pad_tune0)
951 tune_reg = &host->base->pad_tune0;
953 if (mmc->selected_mode == MMC_HS_200 ||
954 mmc->selected_mode == UHS_SDR104)
955 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
956 host->hs200_cmd_int_delay <<
957 MSDC_PAD_TUNE_CMDRRDLY_S);
959 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
961 for (i = 0; i < PAD_DELAY_MAX; i++) {
962 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
963 i << MSDC_PAD_TUNE_CMDRDLY_S);
965 for (j = 0; j < 3; j++) {
966 mmc_send_tuning(mmc, opcode, &cmd_err);
968 rise_delay |= (1 << i);
970 rise_delay &= ~(1 << i);
976 final_rise_delay = get_best_delay(host, rise_delay);
977 /* if rising edge has enough margin, do not scan falling edge */
978 if (final_rise_delay.maxlen >= 12 ||
979 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
982 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
983 for (i = 0; i < PAD_DELAY_MAX; i++) {
984 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
985 i << MSDC_PAD_TUNE_CMDRDLY_S);
987 for (j = 0; j < 3; j++) {
988 mmc_send_tuning(mmc, opcode, &cmd_err);
990 fall_delay |= (1 << i);
992 fall_delay &= ~(1 << i);
998 final_fall_delay = get_best_delay(host, fall_delay);
1001 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1002 if (final_maxlen == final_rise_delay.maxlen) {
1003 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1004 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1005 final_rise_delay.final_phase <<
1006 MSDC_PAD_TUNE_CMDRDLY_S);
1007 final_delay = final_rise_delay.final_phase;
1009 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1010 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1011 final_fall_delay.final_phase <<
1012 MSDC_PAD_TUNE_CMDRDLY_S);
1013 final_delay = final_fall_delay.final_phase;
1016 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1019 for (i = 0; i < PAD_DELAY_MAX; i++) {
1020 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1021 i << MSDC_PAD_TUNE_CMDRRDLY_S);
1023 mmc_send_tuning(mmc, opcode, &cmd_err);
1025 internal_delay |= (1 << i);
1028 dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
1030 internal_delay_phase = get_best_delay(host, internal_delay);
1031 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1032 internal_delay_phase.final_phase <<
1033 MSDC_PAD_TUNE_CMDRRDLY_S);
1036 dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
1037 return final_delay == 0xff ? -EIO : 0;
1040 static int msdc_tune_data(struct udevice *dev, u32 opcode)
1042 struct msdc_plat *plat = dev_get_platdata(dev);
1043 struct msdc_host *host = dev_get_priv(dev);
1044 struct mmc *mmc = &plat->mmc;
1045 u32 rise_delay = 0, fall_delay = 0;
1046 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1047 u8 final_delay, final_maxlen;
1048 void __iomem *tune_reg = &host->base->pad_tune;
1052 if (host->dev_comp->pad_tune0)
1053 tune_reg = &host->base->pad_tune0;
1055 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1056 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1058 for (i = 0; i < PAD_DELAY_MAX; i++) {
1059 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1060 i << MSDC_PAD_TUNE_DATRRDLY_S);
1062 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1064 rise_delay |= (1 << i);
1065 } else if (cmd_err) {
1066 /* in this case, retune response is needed */
1067 ret = msdc_tune_response(dev, opcode);
1073 final_rise_delay = get_best_delay(host, rise_delay);
1074 if (final_rise_delay.maxlen >= 12 ||
1075 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1078 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1079 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1081 for (i = 0; i < PAD_DELAY_MAX; i++) {
1082 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1083 i << MSDC_PAD_TUNE_DATRRDLY_S);
1085 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1087 fall_delay |= (1 << i);
1088 } else if (cmd_err) {
1089 /* in this case, retune response is needed */
1090 ret = msdc_tune_response(dev, opcode);
1096 final_fall_delay = get_best_delay(host, fall_delay);
1099 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1100 if (final_maxlen == final_rise_delay.maxlen) {
1101 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1102 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1103 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1104 final_rise_delay.final_phase <<
1105 MSDC_PAD_TUNE_DATRRDLY_S);
1106 final_delay = final_rise_delay.final_phase;
1108 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1109 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1110 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1111 final_fall_delay.final_phase <<
1112 MSDC_PAD_TUNE_DATRRDLY_S);
1113 final_delay = final_fall_delay.final_phase;
1116 if (mmc->selected_mode == MMC_HS_200 ||
1117 mmc->selected_mode == UHS_SDR104)
1118 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
1119 host->hs200_write_int_delay <<
1120 MSDC_PAD_TUNE_DATWRDLY_S);
1122 dev_err(dev, "Final data pad delay: %x\n", final_delay);
1124 return final_delay == 0xff ? -EIO : 0;
1127 static int msdc_execute_tuning(struct udevice *dev, uint opcode)
1129 struct msdc_plat *plat = dev_get_platdata(dev);
1130 struct msdc_host *host = dev_get_priv(dev);
1131 struct mmc *mmc = &plat->mmc;
1134 if (mmc->selected_mode == MMC_HS_400) {
1135 writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
1136 /* for hs400 mode it must be set to 0 */
1137 clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGCRCSTS);
1138 host->hs400_mode = true;
1141 ret = msdc_tune_response(dev, opcode);
1143 dev_err(dev, "Tune response fail!\n");
1147 if (!host->hs400_mode) {
1148 ret = msdc_tune_data(dev, opcode);
1150 dev_err(dev, "Tune data fail!\n");
1153 host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
1154 host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
1160 static void msdc_init_hw(struct msdc_host *host)
1163 void __iomem *tune_reg = &host->base->pad_tune;
1165 if (host->dev_comp->pad_tune0)
1166 tune_reg = &host->base->pad_tune0;
1168 /* Configure to MMC/SD mode, clock free running */
1169 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
1172 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
1175 msdc_reset_hw(host);
1177 /* Enable/disable hw card detection according to fdt option */
1178 if (host->builtin_cd)
1179 clrsetbits_le32(&host->base->msdc_ps,
1181 (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
1184 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
1186 /* Clear all interrupts */
1187 val = readl(&host->base->msdc_int);
1188 writel(val, &host->base->msdc_int);
1190 /* Enable data & cmd interrupts */
1191 writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
1193 writel(0, tune_reg);
1194 writel(0, &host->base->msdc_iocon);
1197 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1199 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1201 writel(0x403c0046, &host->base->patch_bit0);
1202 writel(0xffff4089, &host->base->patch_bit1);
1204 if (host->dev_comp->stop_clk_fix)
1205 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
1206 3 << MSDC_PB1_STOP_DLY_S);
1208 if (host->dev_comp->busy_check)
1209 clrbits_le32(&host->base->patch_bit1, (1 << 7));
1211 setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
1213 if (host->dev_comp->async_fifo) {
1214 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
1215 3 << MSDC_PB2_RESPWAIT_S);
1217 if (host->dev_comp->enhance_rx) {
1218 setbits_le32(&host->base->sdc_adv_cfg0,
1221 clrsetbits_le32(&host->base->patch_bit2,
1222 MSDC_PB2_RESPSTSENSEL_M,
1223 2 << MSDC_PB2_RESPSTSENSEL_S);
1224 clrsetbits_le32(&host->base->patch_bit2,
1225 MSDC_PB2_CRCSTSENSEL_M,
1226 2 << MSDC_PB2_CRCSTSENSEL_S);
1229 /* use async fifo to avoid tune internal delay */
1230 clrbits_le32(&host->base->patch_bit2,
1232 clrbits_le32(&host->base->patch_bit2,
1233 MSDC_PB2_CFGCRCSTS);
1236 if (host->dev_comp->data_tune) {
1237 setbits_le32(tune_reg,
1238 MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
1239 clrsetbits_le32(&host->base->patch_bit0,
1240 MSDC_INT_DAT_LATCH_CK_SEL_M,
1242 MSDC_INT_DAT_LATCH_CK_SEL_S);
1244 /* choose clock tune */
1245 setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
1248 /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */
1249 setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
1251 /* disable detecting SDIO device interrupt function */
1252 clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
1254 /* Configure to default data timeout */
1255 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
1256 3 << SDC_CFG_DTOC_S);
1258 if (host->dev_comp->stop_clk_fix) {
1259 clrbits_le32(&host->base->sdc_fifo_cfg,
1260 SDC_FIFO_CFG_WRVALIDSEL);
1261 clrbits_le32(&host->base->sdc_fifo_cfg,
1262 SDC_FIFO_CFG_RDVALIDSEL);
1265 host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
1266 host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
1269 static void msdc_ungate_clock(struct msdc_host *host)
1271 clk_enable(&host->src_clk);
1272 clk_enable(&host->h_clk);
1273 if (host->src_clk_cg.dev)
1274 clk_enable(&host->src_clk_cg);
1277 static int msdc_drv_probe(struct udevice *dev)
1279 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1280 struct msdc_plat *plat = dev_get_platdata(dev);
1281 struct msdc_host *host = dev_get_priv(dev);
1282 struct mmc_config *cfg = &plat->cfg;
1284 cfg->name = dev->name;
1286 host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
1288 host->src_clk_freq = clk_get_rate(&host->src_clk);
1290 if (host->dev_comp->clk_div_bits == 8)
1291 cfg->f_min = host->src_clk_freq / (4 * 255);
1293 cfg->f_min = host->src_clk_freq / (4 * 4095);
1294 cfg->f_max = host->src_clk_freq / 2;
1297 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1299 host->mmc = &plat->mmc;
1300 host->timeout_ns = 100000000;
1301 host->timeout_clks = 3 * 1048576;
1303 #ifdef CONFIG_PINCTRL
1304 pinctrl_select_state(dev, "default");
1307 msdc_ungate_clock(host);
1310 upriv->mmc = &plat->mmc;
1315 static int msdc_ofdata_to_platdata(struct udevice *dev)
1317 struct msdc_plat *plat = dev_get_platdata(dev);
1318 struct msdc_host *host = dev_get_priv(dev);
1319 struct mmc_config *cfg = &plat->cfg;
1322 host->base = (void *)dev_read_addr(dev);
1326 ret = mmc_of_parse(dev, cfg);
1330 ret = clk_get_by_name(dev, "source", &host->src_clk);
1334 ret = clk_get_by_name(dev, "hclk", &host->h_clk);
1338 clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
1340 #if IS_ENABLED(DM_GPIO)
1341 gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
1342 gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
1345 host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
1346 host->hs200_cmd_int_delay =
1347 dev_read_u32_default(dev, "cmd_int_delay", 0);
1348 host->hs200_write_int_delay =
1349 dev_read_u32_default(dev, "write_int_delay", 0);
1350 host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
1351 host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
1352 host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
1357 static int msdc_drv_bind(struct udevice *dev)
1359 struct msdc_plat *plat = dev_get_platdata(dev);
1361 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1364 static const struct dm_mmc_ops msdc_ops = {
1365 .send_cmd = msdc_ops_send_cmd,
1366 .set_ios = msdc_ops_set_ios,
1367 .get_cd = msdc_ops_get_cd,
1368 .get_wp = msdc_ops_get_wp,
1369 #ifdef MMC_SUPPORTS_TUNING
1370 .execute_tuning = msdc_execute_tuning,
1374 static const struct msdc_compatible mt7623_compat = {
1379 .busy_check = false,
1380 .stop_clk_fix = false,
1384 static const struct msdc_compatible mt8516_compat = {
1390 .stop_clk_fix = true,
1393 static const struct udevice_id msdc_ids[] = {
1394 { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
1395 { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
1399 U_BOOT_DRIVER(mtk_sd_drv) = {
1402 .of_match = msdc_ids,
1403 .ofdata_to_platdata = msdc_ofdata_to_platdata,
1404 .bind = msdc_drv_bind,
1405 .probe = msdc_drv_probe,
1407 .platdata_auto_alloc_size = sizeof(struct msdc_plat),
1408 .priv_auto_alloc_size = sizeof(struct msdc_host),