1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek SD/MMC Card Interface driver
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
18 #include <dm/pinctrl.h>
19 #include <linux/bitops.h>
21 #include <linux/iopoll.h>
24 #define MSDC_CFG_HS400_CK_MODE_EXT BIT(22)
25 #define MSDC_CFG_CKMOD_EXT_M 0x300000
26 #define MSDC_CFG_CKMOD_EXT_S 20
27 #define MSDC_CFG_CKDIV_EXT_M 0xfff00
28 #define MSDC_CFG_CKDIV_EXT_S 8
29 #define MSDC_CFG_HS400_CK_MODE BIT(18)
30 #define MSDC_CFG_CKMOD_M 0x30000
31 #define MSDC_CFG_CKMOD_S 16
32 #define MSDC_CFG_CKDIV_M 0xff00
33 #define MSDC_CFG_CKDIV_S 8
34 #define MSDC_CFG_CKSTB BIT(7)
35 #define MSDC_CFG_PIO BIT(3)
36 #define MSDC_CFG_RST BIT(2)
37 #define MSDC_CFG_CKPDN BIT(1)
38 #define MSDC_CFG_MODE BIT(0)
41 #define MSDC_IOCON_W_DSPL BIT(8)
42 #define MSDC_IOCON_DSPL BIT(2)
43 #define MSDC_IOCON_RSPL BIT(1)
46 #define MSDC_PS_DAT0 BIT(16)
47 #define MSDC_PS_CDDBCE_M 0xf000
48 #define MSDC_PS_CDDBCE_S 12
49 #define MSDC_PS_CDSTS BIT(1)
50 #define MSDC_PS_CDEN BIT(0)
52 /* #define MSDC_INT(EN) */
53 #define MSDC_INT_ACMDRDY BIT(3)
54 #define MSDC_INT_ACMDTMO BIT(4)
55 #define MSDC_INT_ACMDCRCERR BIT(5)
56 #define MSDC_INT_CMDRDY BIT(8)
57 #define MSDC_INT_CMDTMO BIT(9)
58 #define MSDC_INT_RSPCRCERR BIT(10)
59 #define MSDC_INT_XFER_COMPL BIT(12)
60 #define MSDC_INT_DATTMO BIT(14)
61 #define MSDC_INT_DATCRCERR BIT(15)
64 #define MSDC_FIFOCS_CLR BIT(31)
65 #define MSDC_FIFOCS_TXCNT_M 0xff0000
66 #define MSDC_FIFOCS_TXCNT_S 16
67 #define MSDC_FIFOCS_RXCNT_M 0xff
68 #define MSDC_FIFOCS_RXCNT_S 0
71 #define SDC_CFG_DTOC_M 0xff000000
72 #define SDC_CFG_DTOC_S 24
73 #define SDC_CFG_SDIOIDE BIT(20)
74 #define SDC_CFG_SDIO BIT(19)
75 #define SDC_CFG_BUSWIDTH_M 0x30000
76 #define SDC_CFG_BUSWIDTH_S 16
79 #define SDC_CMD_BLK_LEN_M 0xfff0000
80 #define SDC_CMD_BLK_LEN_S 16
81 #define SDC_CMD_STOP BIT(14)
82 #define SDC_CMD_WR BIT(13)
83 #define SDC_CMD_DTYPE_M 0x1800
84 #define SDC_CMD_DTYPE_S 11
85 #define SDC_CMD_RSPTYP_M 0x380
86 #define SDC_CMD_RSPTYP_S 7
87 #define SDC_CMD_CMD_M 0x3f
88 #define SDC_CMD_CMD_S 0
91 #define SDC_STS_CMDBUSY BIT(1)
92 #define SDC_STS_SDCBUSY BIT(0)
95 #define SDC_RX_ENHANCE_EN BIT(20)
98 #define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380
99 #define MSDC_INT_DAT_LATCH_CK_SEL_S 7
102 #define MSDC_PB1_STOP_DLY_M 0xf00
103 #define MSDC_PB1_STOP_DLY_S 8
106 #define MSDC_PB2_CRCSTSENSEL_M 0xe0000000
107 #define MSDC_PB2_CRCSTSENSEL_S 29
108 #define MSDC_PB2_CFGCRCSTS BIT(28)
109 #define MSDC_PB2_RESPSTSENSEL_M 0x70000
110 #define MSDC_PB2_RESPSTSENSEL_S 16
111 #define MSDC_PB2_CFGRESP BIT(15)
112 #define MSDC_PB2_RESPWAIT_M 0x0c
113 #define MSDC_PB2_RESPWAIT_S 2
116 #define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000
117 #define MSDC_PAD_TUNE_CMDRRDLY_S 22
118 #define MSDC_PAD_TUNE_CMD_SEL BIT(21)
119 #define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000
120 #define MSDC_PAD_TUNE_CMDRDLY_S 16
121 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15)
122 #define MSDC_PAD_TUNE_RD_SEL BIT(13)
123 #define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00
124 #define MSDC_PAD_TUNE_DATRRDLY_S 8
125 #define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
126 #define MSDC_PAD_TUNE_DATWRDLY_S 0
129 #define EMMC50_CFG_CFCSTS_SEL BIT(4)
132 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24)
133 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25)
135 /* SDC_CFG_BUSWIDTH */
136 #define MSDC_BUS_1BITS 0x0
137 #define MSDC_BUS_4BITS 0x1
138 #define MSDC_BUS_8BITS 0x2
140 #define MSDC_FIFO_SIZE 128
142 #define PAD_DELAY_MAX 32
144 #define DEFAULT_CD_DEBOUNCE 8
146 #define CMD_INTS_MASK \
147 (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
149 #define DATA_INTS_MASK \
150 (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
152 /* Register offset */
218 struct msdc_compatible {
228 struct msdc_delay_phase {
235 struct mmc_config cfg;
239 struct msdc_tune_para {
245 struct mtk_sd_regs *base;
248 struct msdc_compatible *dev_comp;
250 struct clk src_clk; /* for SD/MMC bus clock */
251 struct clk src_clk_cg; /* optional, MSDC source clock control gate */
252 struct clk h_clk; /* MSDC core clock */
254 u32 src_clk_freq; /* source clock */
255 u32 mclk; /* mmc framework required bus clock */
256 u32 sclk; /* actual calculated bus clock */
258 /* operation timeout clocks */
264 u32 hs200_cmd_int_delay;
265 u32 hs200_write_int_delay;
267 u32 r_smpl; /* sample edge */
270 /* whether to use gpio detection or built-in hw detection */
273 /* card detection / write protection GPIOs */
274 #if CONFIG_IS_ENABLED(DM_GPIO)
275 struct gpio_desc gpio_wp;
276 struct gpio_desc gpio_cd;
280 uint last_data_write;
282 enum bus_mode timing;
284 struct msdc_tune_para def_tune_para;
285 struct msdc_tune_para saved_tune_para;
288 static void msdc_reset_hw(struct msdc_host *host)
292 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
294 readl_poll_timeout(&host->base->msdc_cfg, reg,
295 !(reg & MSDC_CFG_RST), 1000000);
298 static void msdc_fifo_clr(struct msdc_host *host)
302 setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
304 readl_poll_timeout(&host->base->msdc_fifocs, reg,
305 !(reg & MSDC_FIFOCS_CLR), 1000000);
308 static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
310 return (readl(&host->base->msdc_fifocs) &
311 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
314 static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
316 return (readl(&host->base->msdc_fifocs) &
317 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
320 static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
324 switch (cmd->resp_type) {
325 /* Actually, R1, R5, R6, R7 are the same */
347 static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
349 struct mmc_data *data)
351 u32 opcode = cmd->cmdidx;
352 u32 resp_type = msdc_cmd_find_resp(host, cmd);
358 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
359 case MMC_CMD_READ_MULTIPLE_BLOCK:
362 case MMC_CMD_WRITE_SINGLE_BLOCK:
363 case MMC_CMD_READ_SINGLE_BLOCK:
364 case SD_CMD_APP_SEND_SCR:
367 case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
368 case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
369 case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
375 if (data->flags == MMC_DATA_WRITE)
376 rawcmd |= SDC_CMD_WR;
378 if (data->blocks > 1)
381 blocksize = data->blocksize;
384 rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
385 ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
386 ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
387 ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
389 if (opcode == MMC_CMD_STOP_TRANSMISSION)
390 rawcmd |= SDC_CMD_STOP;
395 static int msdc_cmd_done(struct msdc_host *host, int events,
398 u32 *rsp = cmd->response;
401 if (cmd->resp_type & MMC_RSP_PRESENT) {
402 if (cmd->resp_type & MMC_RSP_136) {
403 rsp[0] = readl(&host->base->sdc_resp[3]);
404 rsp[1] = readl(&host->base->sdc_resp[2]);
405 rsp[2] = readl(&host->base->sdc_resp[1]);
406 rsp[3] = readl(&host->base->sdc_resp[0]);
408 rsp[0] = readl(&host->base->sdc_resp[0]);
412 if (!(events & MSDC_INT_CMDRDY)) {
413 if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
414 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
416 * should not clear fifo/interrupt as the tune data
417 * may have alreay come.
421 if (events & MSDC_INT_CMDTMO)
430 static bool msdc_cmd_is_ready(struct msdc_host *host)
435 /* The max busy time we can endure is 20ms */
436 ret = readl_poll_timeout(&host->base->sdc_sts, reg,
437 !(reg & SDC_STS_CMDBUSY), 20000);
440 pr_err("CMD bus busy detected\n");
445 if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
446 ret = readl_poll_timeout(&host->base->msdc_ps, reg,
447 reg & MSDC_PS_DAT0, 1000000);
450 pr_err("Card stuck in programming state!\n");
459 static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
460 struct mmc_data *data)
467 if (!msdc_cmd_is_ready(host))
472 host->last_resp_type = cmd->resp_type;
473 host->last_data_write = 0;
475 rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
478 blocks = data->blocks;
480 writel(CMD_INTS_MASK, &host->base->msdc_int);
481 writel(blocks, &host->base->sdc_blk_num);
482 writel(cmd->cmdarg, &host->base->sdc_arg);
483 writel(rawcmd, &host->base->sdc_cmd);
485 ret = readl_poll_timeout(&host->base->msdc_int, status,
486 status & CMD_INTS_MASK, 1000000);
489 status = MSDC_INT_CMDTMO;
491 return msdc_cmd_done(host, status, cmd);
494 static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
498 while ((size_t)buf % 4) {
499 *buf++ = readb(&host->base->msdc_rxdata);
505 *wbuf++ = readl(&host->base->msdc_rxdata);
511 *buf++ = readb(&host->base->msdc_rxdata);
516 static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
520 while ((size_t)buf % 4) {
521 writeb(*buf++, &host->base->msdc_txdata);
525 wbuf = (const u32 *)buf;
527 writel(*wbuf++, &host->base->msdc_txdata);
531 buf = (const u8 *)wbuf;
533 writeb(*buf++, &host->base->msdc_txdata);
538 static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
545 status = readl(&host->base->msdc_int);
546 writel(status, &host->base->msdc_int);
547 status &= DATA_INTS_MASK;
549 if (status & MSDC_INT_DATCRCERR) {
554 if (status & MSDC_INT_DATTMO) {
559 chksz = min(size, (u32)MSDC_FIFO_SIZE);
561 if (msdc_fifo_rx_bytes(host) >= chksz) {
562 msdc_fifo_read(host, ptr, chksz);
567 if (status & MSDC_INT_XFER_COMPL) {
569 pr_err("data not fully read\n");
580 static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
587 status = readl(&host->base->msdc_int);
588 writel(status, &host->base->msdc_int);
589 status &= DATA_INTS_MASK;
591 if (status & MSDC_INT_DATCRCERR) {
596 if (status & MSDC_INT_DATTMO) {
601 if (status & MSDC_INT_XFER_COMPL) {
603 pr_err("data not fully written\n");
610 chksz = min(size, (u32)MSDC_FIFO_SIZE);
612 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
613 msdc_fifo_write(host, ptr, chksz);
622 static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
629 if (data->flags == MMC_DATA_WRITE)
630 host->last_data_write = 1;
632 writel(DATA_INTS_MASK, &host->base->msdc_int);
634 size = data->blocks * data->blocksize;
636 if (data->flags == MMC_DATA_WRITE)
637 ret = msdc_pio_write(host, (const u8 *)data->src, size);
639 ret = msdc_pio_read(host, (u8 *)data->dest, size);
649 static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
650 struct mmc_data *data)
652 struct msdc_host *host = dev_get_priv(dev);
655 ret = msdc_start_command(host, cmd, data);
660 return msdc_start_data(host, data);
665 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
670 host->timeout_ns = ns;
671 host->timeout_clks = clks;
673 if (host->sclk == 0) {
676 clk_ns = 1000000000UL / host->sclk;
677 timeout = (ns + clk_ns - 1) / clk_ns + clks;
678 /* unit is 1048576 sclk cycles */
679 timeout = (timeout + (0x1 << 20) - 1) >> 20;
680 if (host->dev_comp->clk_div_bits == 8)
681 mode = (readl(&host->base->msdc_cfg) &
682 MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
684 mode = (readl(&host->base->msdc_cfg) &
685 MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
686 /* DDR mode will double the clk cycles for data timeout */
687 timeout = mode >= 2 ? timeout * 2 : timeout;
688 timeout = timeout > 1 ? timeout - 1 : 0;
689 timeout = timeout > 255 ? 255 : timeout;
692 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
693 timeout << SDC_CFG_DTOC_S);
696 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
698 u32 val = readl(&host->base->sdc_cfg);
700 val &= ~SDC_CFG_BUSWIDTH_M;
705 val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
708 val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
711 val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
715 writel(val, &host->base->sdc_cfg);
718 static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz)
727 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
731 if (host->dev_comp->clk_div_bits == 8)
732 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
734 clrbits_le32(&host->base->msdc_cfg,
735 MSDC_CFG_HS400_CK_MODE_EXT);
737 if (timing == UHS_DDR50 || timing == MMC_DDR_52 ||
738 timing == MMC_HS_400) {
739 if (timing == MMC_HS_400)
742 mode = 0x2; /* ddr mode and use divisor */
744 if (hz >= (host->src_clk_freq >> 2)) {
745 div = 0; /* mean div = 1/4 */
746 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
748 div = (host->src_clk_freq + ((hz << 2) - 1)) /
750 sclk = (host->src_clk_freq >> 2) / div;
754 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
755 if (host->dev_comp->clk_div_bits == 8)
756 setbits_le32(&host->base->msdc_cfg,
757 MSDC_CFG_HS400_CK_MODE);
759 setbits_le32(&host->base->msdc_cfg,
760 MSDC_CFG_HS400_CK_MODE_EXT);
762 sclk = host->src_clk_freq >> 1;
763 div = 0; /* div is ignore when bit18 is set */
765 } else if (hz >= host->src_clk_freq) {
766 mode = 0x1; /* no divisor */
768 sclk = host->src_clk_freq;
770 mode = 0x0; /* use divisor */
771 if (hz >= (host->src_clk_freq >> 1)) {
772 div = 0; /* mean div = 1/2 */
773 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
775 div = (host->src_clk_freq + ((hz << 2) - 1)) /
777 sclk = (host->src_clk_freq >> 2) / div;
781 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
783 if (host->dev_comp->clk_div_bits == 8) {
784 div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
785 clrsetbits_le32(&host->base->msdc_cfg,
786 MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
787 (mode << MSDC_CFG_CKMOD_S) |
788 (div << MSDC_CFG_CKDIV_S));
790 div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
791 MSDC_CFG_CKDIV_EXT_S));
792 clrsetbits_le32(&host->base->msdc_cfg,
793 MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
794 (mode << MSDC_CFG_CKMOD_EXT_S) |
795 (div << MSDC_CFG_CKDIV_EXT_S));
798 readl_poll_timeout(&host->base->msdc_cfg, reg,
799 reg & MSDC_CFG_CKSTB, 1000000);
801 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
804 host->timing = timing;
806 /* needed because clk changed. */
807 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
810 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
811 * tune result of hs200/200Mhz is not suitable for 50Mhz
813 if (host->sclk <= 52000000) {
814 writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
815 writel(host->def_tune_para.pad_tune,
816 &host->base->pad_tune);
818 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
819 writel(host->saved_tune_para.pad_tune,
820 &host->base->pad_tune);
823 dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
826 static int msdc_ops_set_ios(struct udevice *dev)
828 struct msdc_plat *plat = dev_get_platdata(dev);
829 struct msdc_host *host = dev_get_priv(dev);
830 struct mmc *mmc = &plat->mmc;
831 uint clock = mmc->clock;
833 msdc_set_buswidth(host, mmc->bus_width);
835 if (mmc->clk_disable)
837 else if (clock < mmc->cfg->f_min)
838 clock = mmc->cfg->f_min;
840 if (host->mclk != clock || host->timing != mmc->selected_mode)
841 msdc_set_mclk(host, mmc->selected_mode, clock);
846 static int msdc_ops_get_cd(struct udevice *dev)
848 struct msdc_host *host = dev_get_priv(dev);
851 if (host->builtin_cd) {
852 val = readl(&host->base->msdc_ps);
853 return !(val & MSDC_PS_CDSTS);
856 #if CONFIG_IS_ENABLED(DM_GPIO)
857 if (!host->gpio_cd.dev)
860 return dm_gpio_get_value(&host->gpio_cd);
866 static int msdc_ops_get_wp(struct udevice *dev)
868 #if CONFIG_IS_ENABLED(DM_GPIO)
869 struct msdc_host *host = dev_get_priv(dev);
871 if (!host->gpio_wp.dev)
874 return !dm_gpio_get_value(&host->gpio_wp);
880 #ifdef MMC_SUPPORTS_TUNING
881 static u32 test_delay_bit(u32 delay, u32 bit)
883 bit %= PAD_DELAY_MAX;
884 return delay & (1 << bit);
887 static int get_delay_len(u32 delay, u32 start_bit)
891 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
892 if (test_delay_bit(delay, start_bit + i) == 0)
896 return PAD_DELAY_MAX - start_bit;
899 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
901 int start = 0, len = 0;
902 int start_final = 0, len_final = 0;
903 u8 final_phase = 0xff;
904 struct msdc_delay_phase delay_phase = { 0, };
907 dev_err(dev, "phase error: [map:%x]\n", delay);
908 delay_phase.final_phase = final_phase;
912 while (start < PAD_DELAY_MAX) {
913 len = get_delay_len(delay, start);
914 if (len_final < len) {
919 start += len ? len : 1;
920 if (len >= 12 && start_final < 4)
924 /* The rule is to find the smallest delay cell */
925 if (start_final == 0)
926 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
928 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
930 dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
931 delay, len_final, final_phase);
933 delay_phase.maxlen = len_final;
934 delay_phase.start = start_final;
935 delay_phase.final_phase = final_phase;
939 static int msdc_tune_response(struct udevice *dev, u32 opcode)
941 struct msdc_plat *plat = dev_get_platdata(dev);
942 struct msdc_host *host = dev_get_priv(dev);
943 struct mmc *mmc = &plat->mmc;
944 u32 rise_delay = 0, fall_delay = 0;
945 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
946 struct msdc_delay_phase internal_delay_phase;
947 u8 final_delay, final_maxlen;
948 u32 internal_delay = 0;
949 void __iomem *tune_reg = &host->base->pad_tune;
953 if (host->dev_comp->pad_tune0)
954 tune_reg = &host->base->pad_tune0;
956 if (mmc->selected_mode == MMC_HS_200 ||
957 mmc->selected_mode == UHS_SDR104)
958 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
959 host->hs200_cmd_int_delay <<
960 MSDC_PAD_TUNE_CMDRRDLY_S);
962 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
964 for (i = 0; i < PAD_DELAY_MAX; i++) {
965 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
966 i << MSDC_PAD_TUNE_CMDRDLY_S);
968 for (j = 0; j < 3; j++) {
969 mmc_send_tuning(mmc, opcode, &cmd_err);
971 rise_delay |= (1 << i);
973 rise_delay &= ~(1 << i);
979 final_rise_delay = get_best_delay(host, rise_delay);
980 /* if rising edge has enough margin, do not scan falling edge */
981 if (final_rise_delay.maxlen >= 12 ||
982 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
985 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
986 for (i = 0; i < PAD_DELAY_MAX; i++) {
987 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
988 i << MSDC_PAD_TUNE_CMDRDLY_S);
990 for (j = 0; j < 3; j++) {
991 mmc_send_tuning(mmc, opcode, &cmd_err);
993 fall_delay |= (1 << i);
995 fall_delay &= ~(1 << i);
1001 final_fall_delay = get_best_delay(host, fall_delay);
1004 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1005 if (final_maxlen == final_rise_delay.maxlen) {
1006 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1007 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1008 final_rise_delay.final_phase <<
1009 MSDC_PAD_TUNE_CMDRDLY_S);
1010 final_delay = final_rise_delay.final_phase;
1012 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1013 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1014 final_fall_delay.final_phase <<
1015 MSDC_PAD_TUNE_CMDRDLY_S);
1016 final_delay = final_fall_delay.final_phase;
1019 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1022 for (i = 0; i < PAD_DELAY_MAX; i++) {
1023 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1024 i << MSDC_PAD_TUNE_CMDRRDLY_S);
1026 mmc_send_tuning(mmc, opcode, &cmd_err);
1028 internal_delay |= (1 << i);
1031 dev_err(dev, "Final internal delay: 0x%x\n", internal_delay);
1033 internal_delay_phase = get_best_delay(host, internal_delay);
1034 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1035 internal_delay_phase.final_phase <<
1036 MSDC_PAD_TUNE_CMDRRDLY_S);
1039 dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
1040 return final_delay == 0xff ? -EIO : 0;
1043 static int msdc_tune_data(struct udevice *dev, u32 opcode)
1045 struct msdc_plat *plat = dev_get_platdata(dev);
1046 struct msdc_host *host = dev_get_priv(dev);
1047 struct mmc *mmc = &plat->mmc;
1048 u32 rise_delay = 0, fall_delay = 0;
1049 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1050 u8 final_delay, final_maxlen;
1051 void __iomem *tune_reg = &host->base->pad_tune;
1055 if (host->dev_comp->pad_tune0)
1056 tune_reg = &host->base->pad_tune0;
1058 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1059 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1061 for (i = 0; i < PAD_DELAY_MAX; i++) {
1062 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1063 i << MSDC_PAD_TUNE_DATRRDLY_S);
1065 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1067 rise_delay |= (1 << i);
1068 } else if (cmd_err) {
1069 /* in this case, retune response is needed */
1070 ret = msdc_tune_response(dev, opcode);
1076 final_rise_delay = get_best_delay(host, rise_delay);
1077 if (final_rise_delay.maxlen >= 12 ||
1078 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1081 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1082 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1084 for (i = 0; i < PAD_DELAY_MAX; i++) {
1085 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1086 i << MSDC_PAD_TUNE_DATRRDLY_S);
1088 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1090 fall_delay |= (1 << i);
1091 } else if (cmd_err) {
1092 /* in this case, retune response is needed */
1093 ret = msdc_tune_response(dev, opcode);
1099 final_fall_delay = get_best_delay(host, fall_delay);
1102 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1103 if (final_maxlen == final_rise_delay.maxlen) {
1104 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1105 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1106 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1107 final_rise_delay.final_phase <<
1108 MSDC_PAD_TUNE_DATRRDLY_S);
1109 final_delay = final_rise_delay.final_phase;
1111 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1112 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1113 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1114 final_fall_delay.final_phase <<
1115 MSDC_PAD_TUNE_DATRRDLY_S);
1116 final_delay = final_fall_delay.final_phase;
1119 if (mmc->selected_mode == MMC_HS_200 ||
1120 mmc->selected_mode == UHS_SDR104)
1121 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
1122 host->hs200_write_int_delay <<
1123 MSDC_PAD_TUNE_DATWRDLY_S);
1125 dev_err(dev, "Final data pad delay: %x\n", final_delay);
1127 return final_delay == 0xff ? -EIO : 0;
1130 static int msdc_execute_tuning(struct udevice *dev, uint opcode)
1132 struct msdc_plat *plat = dev_get_platdata(dev);
1133 struct msdc_host *host = dev_get_priv(dev);
1134 struct mmc *mmc = &plat->mmc;
1137 if (mmc->selected_mode == MMC_HS_400) {
1138 writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
1139 /* for hs400 mode it must be set to 0 */
1140 clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGCRCSTS);
1141 host->hs400_mode = true;
1144 ret = msdc_tune_response(dev, opcode);
1146 dev_err(dev, "Tune response fail!\n");
1150 if (!host->hs400_mode) {
1151 ret = msdc_tune_data(dev, opcode);
1153 dev_err(dev, "Tune data fail!\n");
1156 host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
1157 host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
1163 static void msdc_init_hw(struct msdc_host *host)
1166 void __iomem *tune_reg = &host->base->pad_tune;
1168 if (host->dev_comp->pad_tune0)
1169 tune_reg = &host->base->pad_tune0;
1171 /* Configure to MMC/SD mode, clock free running */
1172 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
1175 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
1178 msdc_reset_hw(host);
1180 /* Enable/disable hw card detection according to fdt option */
1181 if (host->builtin_cd)
1182 clrsetbits_le32(&host->base->msdc_ps,
1184 (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
1187 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
1189 /* Clear all interrupts */
1190 val = readl(&host->base->msdc_int);
1191 writel(val, &host->base->msdc_int);
1193 /* Enable data & cmd interrupts */
1194 writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
1196 writel(0, tune_reg);
1197 writel(0, &host->base->msdc_iocon);
1200 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1202 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1204 writel(0x403c0046, &host->base->patch_bit0);
1205 writel(0xffff4089, &host->base->patch_bit1);
1207 if (host->dev_comp->stop_clk_fix)
1208 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
1209 3 << MSDC_PB1_STOP_DLY_S);
1211 if (host->dev_comp->busy_check)
1212 clrbits_le32(&host->base->patch_bit1, (1 << 7));
1214 setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
1216 if (host->dev_comp->async_fifo) {
1217 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
1218 3 << MSDC_PB2_RESPWAIT_S);
1220 if (host->dev_comp->enhance_rx) {
1221 setbits_le32(&host->base->sdc_adv_cfg0,
1224 clrsetbits_le32(&host->base->patch_bit2,
1225 MSDC_PB2_RESPSTSENSEL_M,
1226 2 << MSDC_PB2_RESPSTSENSEL_S);
1227 clrsetbits_le32(&host->base->patch_bit2,
1228 MSDC_PB2_CRCSTSENSEL_M,
1229 2 << MSDC_PB2_CRCSTSENSEL_S);
1232 /* use async fifo to avoid tune internal delay */
1233 clrbits_le32(&host->base->patch_bit2,
1235 clrbits_le32(&host->base->patch_bit2,
1236 MSDC_PB2_CFGCRCSTS);
1239 if (host->dev_comp->data_tune) {
1240 setbits_le32(tune_reg,
1241 MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
1242 clrsetbits_le32(&host->base->patch_bit0,
1243 MSDC_INT_DAT_LATCH_CK_SEL_M,
1245 MSDC_INT_DAT_LATCH_CK_SEL_S);
1247 /* choose clock tune */
1248 setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
1251 /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */
1252 setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
1254 /* disable detecting SDIO device interrupt function */
1255 clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
1257 /* Configure to default data timeout */
1258 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
1259 3 << SDC_CFG_DTOC_S);
1261 if (host->dev_comp->stop_clk_fix) {
1262 clrbits_le32(&host->base->sdc_fifo_cfg,
1263 SDC_FIFO_CFG_WRVALIDSEL);
1264 clrbits_le32(&host->base->sdc_fifo_cfg,
1265 SDC_FIFO_CFG_RDVALIDSEL);
1268 host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
1269 host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
1272 static void msdc_ungate_clock(struct msdc_host *host)
1274 clk_enable(&host->src_clk);
1275 clk_enable(&host->h_clk);
1276 if (host->src_clk_cg.dev)
1277 clk_enable(&host->src_clk_cg);
1280 static int msdc_drv_probe(struct udevice *dev)
1282 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1283 struct msdc_plat *plat = dev_get_platdata(dev);
1284 struct msdc_host *host = dev_get_priv(dev);
1285 struct mmc_config *cfg = &plat->cfg;
1287 cfg->name = dev->name;
1289 host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
1291 host->src_clk_freq = clk_get_rate(&host->src_clk);
1293 if (host->dev_comp->clk_div_bits == 8)
1294 cfg->f_min = host->src_clk_freq / (4 * 255);
1296 cfg->f_min = host->src_clk_freq / (4 * 4095);
1297 cfg->f_max = host->src_clk_freq / 2;
1300 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1302 host->mmc = &plat->mmc;
1303 host->timeout_ns = 100000000;
1304 host->timeout_clks = 3 * 1048576;
1306 #ifdef CONFIG_PINCTRL
1307 pinctrl_select_state(dev, "default");
1310 msdc_ungate_clock(host);
1313 upriv->mmc = &plat->mmc;
1318 static int msdc_ofdata_to_platdata(struct udevice *dev)
1320 struct msdc_plat *plat = dev_get_platdata(dev);
1321 struct msdc_host *host = dev_get_priv(dev);
1322 struct mmc_config *cfg = &plat->cfg;
1325 host->base = (void *)dev_read_addr(dev);
1329 ret = mmc_of_parse(dev, cfg);
1333 ret = clk_get_by_name(dev, "source", &host->src_clk);
1337 ret = clk_get_by_name(dev, "hclk", &host->h_clk);
1341 clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
1343 #if CONFIG_IS_ENABLED(DM_GPIO)
1344 gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
1345 gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
1348 host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
1349 host->hs200_cmd_int_delay =
1350 dev_read_u32_default(dev, "cmd_int_delay", 0);
1351 host->hs200_write_int_delay =
1352 dev_read_u32_default(dev, "write_int_delay", 0);
1353 host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
1354 host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
1355 host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
1360 static int msdc_drv_bind(struct udevice *dev)
1362 struct msdc_plat *plat = dev_get_platdata(dev);
1364 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1367 static const struct dm_mmc_ops msdc_ops = {
1368 .send_cmd = msdc_ops_send_cmd,
1369 .set_ios = msdc_ops_set_ios,
1370 .get_cd = msdc_ops_get_cd,
1371 .get_wp = msdc_ops_get_wp,
1372 #ifdef MMC_SUPPORTS_TUNING
1373 .execute_tuning = msdc_execute_tuning,
1377 static const struct msdc_compatible mt7623_compat = {
1382 .busy_check = false,
1383 .stop_clk_fix = false,
1387 static const struct msdc_compatible mt8516_compat = {
1393 .stop_clk_fix = true,
1396 static const struct msdc_compatible mt8183_compat = {
1402 .stop_clk_fix = true,
1405 static const struct udevice_id msdc_ids[] = {
1406 { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
1407 { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
1408 { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
1412 U_BOOT_DRIVER(mtk_sd_drv) = {
1415 .of_match = msdc_ids,
1416 .ofdata_to_platdata = msdc_ofdata_to_platdata,
1417 .bind = msdc_drv_bind,
1418 .probe = msdc_drv_probe,
1420 .platdata_auto_alloc_size = sizeof(struct msdc_plat),
1421 .priv_auto_alloc_size = sizeof(struct msdc_host),