2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
20 #include <linux/list.h>
22 #include "mmc_private.h"
24 __weak int board_mmc_getwp(struct mmc *mmc)
29 int mmc_getwp(struct mmc *mmc)
33 wp = board_mmc_getwp(mmc);
36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
45 __weak int board_mmc_getcd(struct mmc *mmc)
50 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
54 #ifdef CONFIG_MMC_TRACE
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
62 printf("\t\tRET\t\t\t %d\n", ret);
64 switch (cmd->resp_type) {
66 printf("\t\tMMC_RSP_NONE\n");
69 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
73 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
77 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
79 printf("\t\t \t\t 0x%08X \n",
81 printf("\t\t \t\t 0x%08X \n",
83 printf("\t\t \t\t 0x%08X \n",
86 printf("\t\t\t\t\tDUMPING DATA\n");
87 for (i = 0; i < 4; i++) {
89 printf("\t\t\t\t\t%03d - ", i*4);
90 ptr = (u8 *)&cmd->response[i];
92 for (j = 0; j < 4; j++)
93 printf("%02X ", *ptr--);
98 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
102 printf("\t\tERROR MMC rsp not supported\n");
107 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
112 int mmc_send_status(struct mmc *mmc, int timeout)
115 int err, retries = 5;
116 #ifdef CONFIG_MMC_TRACE
120 cmd.cmdidx = MMC_CMD_SEND_STATUS;
121 cmd.resp_type = MMC_RSP_R1;
122 if (!mmc_host_is_spi(mmc))
123 cmd.cmdarg = mmc->rca << 16;
126 err = mmc_send_cmd(mmc, &cmd, NULL);
128 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
129 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
132 else if (cmd.response[0] & MMC_STATUS_MASK) {
133 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
134 printf("Status Error: 0x%08X\n",
139 } else if (--retries < 0)
148 #ifdef CONFIG_MMC_TRACE
149 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
150 printf("CURR STATE:%d\n", status);
153 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
154 printf("Timeout waiting card ready\n");
158 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
164 int mmc_set_blocklen(struct mmc *mmc, int len)
171 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
172 cmd.resp_type = MMC_RSP_R1;
175 return mmc_send_cmd(mmc, &cmd, NULL);
178 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
182 struct mmc_data data;
185 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
187 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
189 if (mmc->high_capacity)
192 cmd.cmdarg = start * mmc->read_bl_len;
194 cmd.resp_type = MMC_RSP_R1;
197 data.blocks = blkcnt;
198 data.blocksize = mmc->read_bl_len;
199 data.flags = MMC_DATA_READ;
201 if (mmc_send_cmd(mmc, &cmd, &data))
205 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
207 cmd.resp_type = MMC_RSP_R1b;
208 if (mmc_send_cmd(mmc, &cmd, NULL)) {
209 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
210 printf("mmc fail to send stop cmd\n");
219 static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start,
220 lbaint_t blkcnt, void *dst)
222 int dev_num = block_dev->devnum;
224 lbaint_t cur, blocks_todo = blkcnt;
229 struct mmc *mmc = find_mmc_device(dev_num);
233 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
237 if ((start + blkcnt) > block_dev->lba) {
238 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
239 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
240 start + blkcnt, block_dev->lba);
245 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
246 debug("%s: Failed to set blocklen\n", __func__);
251 cur = (blocks_todo > mmc->cfg->b_max) ?
252 mmc->cfg->b_max : blocks_todo;
253 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
254 debug("%s: Failed to read blocks\n", __func__);
259 dst += cur * mmc->read_bl_len;
260 } while (blocks_todo > 0);
265 static int mmc_go_idle(struct mmc *mmc)
272 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
274 cmd.resp_type = MMC_RSP_NONE;
276 err = mmc_send_cmd(mmc, &cmd, NULL);
286 static int sd_send_op_cond(struct mmc *mmc)
293 cmd.cmdidx = MMC_CMD_APP_CMD;
294 cmd.resp_type = MMC_RSP_R1;
297 err = mmc_send_cmd(mmc, &cmd, NULL);
302 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
303 cmd.resp_type = MMC_RSP_R3;
306 * Most cards do not answer if some reserved bits
307 * in the ocr are set. However, Some controller
308 * can set bit 7 (reserved for low voltages), but
309 * how to manage low voltages SD card is not yet
312 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
313 (mmc->cfg->voltages & 0xff8000);
315 if (mmc->version == SD_VERSION_2)
316 cmd.cmdarg |= OCR_HCS;
318 err = mmc_send_cmd(mmc, &cmd, NULL);
323 if (cmd.response[0] & OCR_BUSY)
332 if (mmc->version != SD_VERSION_2)
333 mmc->version = SD_VERSION_1_0;
335 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
336 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
337 cmd.resp_type = MMC_RSP_R3;
340 err = mmc_send_cmd(mmc, &cmd, NULL);
346 mmc->ocr = cmd.response[0];
348 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
354 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
359 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
360 cmd.resp_type = MMC_RSP_R3;
362 if (use_arg && !mmc_host_is_spi(mmc))
363 cmd.cmdarg = OCR_HCS |
364 (mmc->cfg->voltages &
365 (mmc->ocr & OCR_VOLTAGE_MASK)) |
366 (mmc->ocr & OCR_ACCESS_MODE);
368 err = mmc_send_cmd(mmc, &cmd, NULL);
371 mmc->ocr = cmd.response[0];
375 static int mmc_send_op_cond(struct mmc *mmc)
379 /* Some cards seem to need this */
382 /* Asking to the card its capabilities */
383 for (i = 0; i < 2; i++) {
384 err = mmc_send_op_cond_iter(mmc, i != 0);
388 /* exit if not busy (flag seems to be inverted) */
389 if (mmc->ocr & OCR_BUSY)
392 mmc->op_cond_pending = 1;
396 static int mmc_complete_op_cond(struct mmc *mmc)
403 mmc->op_cond_pending = 0;
404 if (!(mmc->ocr & OCR_BUSY)) {
405 start = get_timer(0);
407 err = mmc_send_op_cond_iter(mmc, 1);
410 if (mmc->ocr & OCR_BUSY)
412 if (get_timer(start) > timeout)
418 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
419 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
420 cmd.resp_type = MMC_RSP_R3;
423 err = mmc_send_cmd(mmc, &cmd, NULL);
428 mmc->ocr = cmd.response[0];
431 mmc->version = MMC_VERSION_UNKNOWN;
433 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
440 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
443 struct mmc_data data;
446 /* Get the Card Status Register */
447 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
448 cmd.resp_type = MMC_RSP_R1;
451 data.dest = (char *)ext_csd;
453 data.blocksize = MMC_MAX_BLOCK_LEN;
454 data.flags = MMC_DATA_READ;
456 err = mmc_send_cmd(mmc, &cmd, &data);
462 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
468 cmd.cmdidx = MMC_CMD_SWITCH;
469 cmd.resp_type = MMC_RSP_R1b;
470 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
474 ret = mmc_send_cmd(mmc, &cmd, NULL);
476 /* Waiting for the ready status */
478 ret = mmc_send_status(mmc, timeout);
484 static int mmc_change_freq(struct mmc *mmc)
486 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
492 if (mmc_host_is_spi(mmc))
495 /* Only version 4 supports high-speed */
496 if (mmc->version < MMC_VERSION_4)
499 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
501 err = mmc_send_ext_csd(mmc, ext_csd);
506 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
508 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
511 return err == SWITCH_ERR ? 0 : err;
513 /* Now check to see that it worked */
514 err = mmc_send_ext_csd(mmc, ext_csd);
519 /* No high-speed support */
520 if (!ext_csd[EXT_CSD_HS_TIMING])
523 /* High Speed is set, there are two types: 52MHz and 26MHz */
524 if (cardtype & EXT_CSD_CARD_TYPE_52) {
525 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
526 mmc->card_caps |= MMC_MODE_DDR_52MHz;
527 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
529 mmc->card_caps |= MMC_MODE_HS;
535 static int mmc_set_capacity(struct mmc *mmc, int part_num)
539 mmc->capacity = mmc->capacity_user;
543 mmc->capacity = mmc->capacity_boot;
546 mmc->capacity = mmc->capacity_rpmb;
552 mmc->capacity = mmc->capacity_gp[part_num - 4];
558 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
563 int mmc_switch_part(int dev_num, unsigned int part_num)
565 struct mmc *mmc = find_mmc_device(dev_num);
571 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
572 (mmc->part_config & ~PART_ACCESS_MASK)
573 | (part_num & PART_ACCESS_MASK));
576 * Set the capacity if the switch succeeded or was intended
577 * to return to representing the raw device.
579 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
580 ret = mmc_set_capacity(mmc, part_num);
581 mmc->block_dev.hwpart = part_num;
587 static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
589 struct mmc *mmc = find_mmc_device(desc->devnum);
595 if (mmc->block_dev.hwpart == hwpart)
598 if (mmc->part_config == MMCPART_NOAVAILABLE)
601 ret = mmc_switch_part(desc->devnum, hwpart);
608 int mmc_select_hwpart(int dev_num, int hwpart)
610 struct mmc *mmc = find_mmc_device(dev_num);
616 if (mmc->block_dev.hwpart == hwpart)
619 if (mmc->part_config == MMCPART_NOAVAILABLE)
622 ret = mmc_switch_part(dev_num, hwpart);
629 int mmc_hwpart_config(struct mmc *mmc,
630 const struct mmc_hwpart_conf *conf,
631 enum mmc_hwpart_conf_mode mode)
637 u32 max_enh_size_mult;
638 u32 tot_enh_size_mult = 0;
641 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
643 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
646 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
647 printf("eMMC >= 4.4 required for enhanced user data area\n");
651 if (!(mmc->part_support & PART_SUPPORT)) {
652 printf("Card does not support partitioning\n");
656 if (!mmc->hc_wp_grp_size) {
657 printf("Card does not define HC WP group size\n");
661 /* check partition alignment and total enhanced size */
662 if (conf->user.enh_size) {
663 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
664 conf->user.enh_start % mmc->hc_wp_grp_size) {
665 printf("User data enhanced area not HC WP group "
669 part_attrs |= EXT_CSD_ENH_USR;
670 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
671 if (mmc->high_capacity) {
672 enh_start_addr = conf->user.enh_start;
674 enh_start_addr = (conf->user.enh_start << 9);
680 tot_enh_size_mult += enh_size_mult;
682 for (pidx = 0; pidx < 4; pidx++) {
683 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
684 printf("GP%i partition not HC WP group size "
685 "aligned\n", pidx+1);
688 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
689 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
690 part_attrs |= EXT_CSD_ENH_GP(pidx);
691 tot_enh_size_mult += gp_size_mult[pidx];
695 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
696 printf("Card does not support enhanced attribute\n");
700 err = mmc_send_ext_csd(mmc, ext_csd);
705 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
706 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
707 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
708 if (tot_enh_size_mult > max_enh_size_mult) {
709 printf("Total enhanced size exceeds maximum (%u > %u)\n",
710 tot_enh_size_mult, max_enh_size_mult);
714 /* The default value of EXT_CSD_WR_REL_SET is device
715 * dependent, the values can only be changed if the
716 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
717 * changed only once and before partitioning is completed. */
718 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
719 if (conf->user.wr_rel_change) {
720 if (conf->user.wr_rel_set)
721 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
723 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
725 for (pidx = 0; pidx < 4; pidx++) {
726 if (conf->gp_part[pidx].wr_rel_change) {
727 if (conf->gp_part[pidx].wr_rel_set)
728 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
730 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
734 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
735 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
736 puts("Card does not support host controlled partition write "
737 "reliability settings\n");
741 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
742 EXT_CSD_PARTITION_SETTING_COMPLETED) {
743 printf("Card already partitioned\n");
747 if (mode == MMC_HWPART_CONF_CHECK)
750 /* Partitioning requires high-capacity size definitions */
751 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
752 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
753 EXT_CSD_ERASE_GROUP_DEF, 1);
758 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
760 /* update erase group size to be high-capacity */
761 mmc->erase_grp_size =
762 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
766 /* all OK, write the configuration */
767 for (i = 0; i < 4; i++) {
768 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
769 EXT_CSD_ENH_START_ADDR+i,
770 (enh_start_addr >> (i*8)) & 0xFF);
774 for (i = 0; i < 3; i++) {
775 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
776 EXT_CSD_ENH_SIZE_MULT+i,
777 (enh_size_mult >> (i*8)) & 0xFF);
781 for (pidx = 0; pidx < 4; pidx++) {
782 for (i = 0; i < 3; i++) {
783 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
784 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
785 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
790 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
791 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
795 if (mode == MMC_HWPART_CONF_SET)
798 /* The WR_REL_SET is a write-once register but shall be
799 * written before setting PART_SETTING_COMPLETED. As it is
800 * write-once we can only write it when completing the
802 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
803 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
804 EXT_CSD_WR_REL_SET, wr_rel_set);
809 /* Setting PART_SETTING_COMPLETED confirms the partition
810 * configuration but it only becomes effective after power
811 * cycle, so we do not adjust the partition related settings
812 * in the mmc struct. */
814 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
815 EXT_CSD_PARTITION_SETTING,
816 EXT_CSD_PARTITION_SETTING_COMPLETED);
823 int mmc_getcd(struct mmc *mmc)
827 cd = board_mmc_getcd(mmc);
830 if (mmc->cfg->ops->getcd)
831 cd = mmc->cfg->ops->getcd(mmc);
839 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
842 struct mmc_data data;
844 /* Switch the frequency */
845 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
846 cmd.resp_type = MMC_RSP_R1;
847 cmd.cmdarg = (mode << 31) | 0xffffff;
848 cmd.cmdarg &= ~(0xf << (group * 4));
849 cmd.cmdarg |= value << (group * 4);
851 data.dest = (char *)resp;
854 data.flags = MMC_DATA_READ;
856 return mmc_send_cmd(mmc, &cmd, &data);
860 static int sd_change_freq(struct mmc *mmc)
864 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
865 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
866 struct mmc_data data;
871 if (mmc_host_is_spi(mmc))
874 /* Read the SCR to find out if this card supports higher speeds */
875 cmd.cmdidx = MMC_CMD_APP_CMD;
876 cmd.resp_type = MMC_RSP_R1;
877 cmd.cmdarg = mmc->rca << 16;
879 err = mmc_send_cmd(mmc, &cmd, NULL);
884 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
885 cmd.resp_type = MMC_RSP_R1;
891 data.dest = (char *)scr;
894 data.flags = MMC_DATA_READ;
896 err = mmc_send_cmd(mmc, &cmd, &data);
905 mmc->scr[0] = __be32_to_cpu(scr[0]);
906 mmc->scr[1] = __be32_to_cpu(scr[1]);
908 switch ((mmc->scr[0] >> 24) & 0xf) {
910 mmc->version = SD_VERSION_1_0;
913 mmc->version = SD_VERSION_1_10;
916 mmc->version = SD_VERSION_2;
917 if ((mmc->scr[0] >> 15) & 0x1)
918 mmc->version = SD_VERSION_3;
921 mmc->version = SD_VERSION_1_0;
925 if (mmc->scr[0] & SD_DATA_4BIT)
926 mmc->card_caps |= MMC_MODE_4BIT;
928 /* Version 1.0 doesn't support switching */
929 if (mmc->version == SD_VERSION_1_0)
934 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
935 (u8 *)switch_status);
940 /* The high-speed function is busy. Try again */
941 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
945 /* If high-speed isn't supported, we return */
946 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
950 * If the host doesn't support SD_HIGHSPEED, do not switch card to
951 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
952 * This can avoid furthur problem when the card runs in different
953 * mode between the host.
955 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
956 (mmc->cfg->host_caps & MMC_MODE_HS)))
959 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
964 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
965 mmc->card_caps |= MMC_MODE_HS;
970 /* frequency bases */
971 /* divided by 10 to be nice to platforms without floating point */
972 static const int fbase[] = {
979 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
980 * to platforms without floating point.
982 static const int multipliers[] = {
1001 static void mmc_set_ios(struct mmc *mmc)
1003 if (mmc->cfg->ops->set_ios)
1004 mmc->cfg->ops->set_ios(mmc);
1007 void mmc_set_clock(struct mmc *mmc, uint clock)
1009 if (clock > mmc->cfg->f_max)
1010 clock = mmc->cfg->f_max;
1012 if (clock < mmc->cfg->f_min)
1013 clock = mmc->cfg->f_min;
1020 static void mmc_set_bus_width(struct mmc *mmc, uint width)
1022 mmc->bus_width = width;
1027 static int mmc_startup(struct mmc *mmc)
1031 u64 cmult, csize, capacity;
1033 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1034 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1036 bool has_parts = false;
1037 bool part_completed;
1038 struct blk_desc *bdesc;
1040 #ifdef CONFIG_MMC_SPI_CRC_ON
1041 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1042 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1043 cmd.resp_type = MMC_RSP_R1;
1045 err = mmc_send_cmd(mmc, &cmd, NULL);
1052 /* Put the Card in Identify Mode */
1053 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1054 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1055 cmd.resp_type = MMC_RSP_R2;
1058 err = mmc_send_cmd(mmc, &cmd, NULL);
1063 memcpy(mmc->cid, cmd.response, 16);
1066 * For MMC cards, set the Relative Address.
1067 * For SD cards, get the Relatvie Address.
1068 * This also puts the cards into Standby State
1070 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1071 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1072 cmd.cmdarg = mmc->rca << 16;
1073 cmd.resp_type = MMC_RSP_R6;
1075 err = mmc_send_cmd(mmc, &cmd, NULL);
1081 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1084 /* Get the Card-Specific Data */
1085 cmd.cmdidx = MMC_CMD_SEND_CSD;
1086 cmd.resp_type = MMC_RSP_R2;
1087 cmd.cmdarg = mmc->rca << 16;
1089 err = mmc_send_cmd(mmc, &cmd, NULL);
1091 /* Waiting for the ready status */
1092 mmc_send_status(mmc, timeout);
1097 mmc->csd[0] = cmd.response[0];
1098 mmc->csd[1] = cmd.response[1];
1099 mmc->csd[2] = cmd.response[2];
1100 mmc->csd[3] = cmd.response[3];
1102 if (mmc->version == MMC_VERSION_UNKNOWN) {
1103 int version = (cmd.response[0] >> 26) & 0xf;
1107 mmc->version = MMC_VERSION_1_2;
1110 mmc->version = MMC_VERSION_1_4;
1113 mmc->version = MMC_VERSION_2_2;
1116 mmc->version = MMC_VERSION_3;
1119 mmc->version = MMC_VERSION_4;
1122 mmc->version = MMC_VERSION_1_2;
1127 /* divide frequency by 10, since the mults are 10x bigger */
1128 freq = fbase[(cmd.response[0] & 0x7)];
1129 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1131 mmc->tran_speed = freq * mult;
1133 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1134 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1137 mmc->write_bl_len = mmc->read_bl_len;
1139 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1141 if (mmc->high_capacity) {
1142 csize = (mmc->csd[1] & 0x3f) << 16
1143 | (mmc->csd[2] & 0xffff0000) >> 16;
1146 csize = (mmc->csd[1] & 0x3ff) << 2
1147 | (mmc->csd[2] & 0xc0000000) >> 30;
1148 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1151 mmc->capacity_user = (csize + 1) << (cmult + 2);
1152 mmc->capacity_user *= mmc->read_bl_len;
1153 mmc->capacity_boot = 0;
1154 mmc->capacity_rpmb = 0;
1155 for (i = 0; i < 4; i++)
1156 mmc->capacity_gp[i] = 0;
1158 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1159 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1161 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1162 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1164 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1165 cmd.cmdidx = MMC_CMD_SET_DSR;
1166 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1167 cmd.resp_type = MMC_RSP_NONE;
1168 if (mmc_send_cmd(mmc, &cmd, NULL))
1169 printf("MMC: SET_DSR failed\n");
1172 /* Select the card, and put it into Transfer Mode */
1173 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1174 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1175 cmd.resp_type = MMC_RSP_R1;
1176 cmd.cmdarg = mmc->rca << 16;
1177 err = mmc_send_cmd(mmc, &cmd, NULL);
1184 * For SD, its erase group is always one sector
1186 mmc->erase_grp_size = 1;
1187 mmc->part_config = MMCPART_NOAVAILABLE;
1188 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1189 /* check ext_csd version and capacity */
1190 err = mmc_send_ext_csd(mmc, ext_csd);
1193 if (ext_csd[EXT_CSD_REV] >= 2) {
1195 * According to the JEDEC Standard, the value of
1196 * ext_csd's capacity is valid if the value is more
1199 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1200 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1201 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1202 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1203 capacity *= MMC_MAX_BLOCK_LEN;
1204 if ((capacity >> 20) > 2 * 1024)
1205 mmc->capacity_user = capacity;
1208 switch (ext_csd[EXT_CSD_REV]) {
1210 mmc->version = MMC_VERSION_4_1;
1213 mmc->version = MMC_VERSION_4_2;
1216 mmc->version = MMC_VERSION_4_3;
1219 mmc->version = MMC_VERSION_4_41;
1222 mmc->version = MMC_VERSION_4_5;
1225 mmc->version = MMC_VERSION_5_0;
1229 /* The partition data may be non-zero but it is only
1230 * effective if PARTITION_SETTING_COMPLETED is set in
1231 * EXT_CSD, so ignore any data if this bit is not set,
1232 * except for enabling the high-capacity group size
1233 * definition (see below). */
1234 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1235 EXT_CSD_PARTITION_SETTING_COMPLETED);
1237 /* store the partition info of emmc */
1238 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1239 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1240 ext_csd[EXT_CSD_BOOT_MULT])
1241 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1242 if (part_completed &&
1243 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1244 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1246 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1248 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1250 for (i = 0; i < 4; i++) {
1251 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1252 uint mult = (ext_csd[idx + 2] << 16) +
1253 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1256 if (!part_completed)
1258 mmc->capacity_gp[i] = mult;
1259 mmc->capacity_gp[i] *=
1260 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1261 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1262 mmc->capacity_gp[i] <<= 19;
1265 if (part_completed) {
1266 mmc->enh_user_size =
1267 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1268 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1269 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1270 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1271 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1272 mmc->enh_user_size <<= 19;
1273 mmc->enh_user_start =
1274 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1275 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1276 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1277 ext_csd[EXT_CSD_ENH_START_ADDR];
1278 if (mmc->high_capacity)
1279 mmc->enh_user_start <<= 9;
1283 * Host needs to enable ERASE_GRP_DEF bit if device is
1284 * partitioned. This bit will be lost every time after a reset
1285 * or power off. This will affect erase size.
1289 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1290 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1293 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1294 EXT_CSD_ERASE_GROUP_DEF, 1);
1299 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1302 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1303 /* Read out group size from ext_csd */
1304 mmc->erase_grp_size =
1305 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1307 * if high capacity and partition setting completed
1308 * SEC_COUNT is valid even if it is smaller than 2 GiB
1309 * JEDEC Standard JESD84-B45, 6.2.4
1311 if (mmc->high_capacity && part_completed) {
1312 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1313 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1314 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1315 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1316 capacity *= MMC_MAX_BLOCK_LEN;
1317 mmc->capacity_user = capacity;
1320 /* Calculate the group size from the csd value. */
1321 int erase_gsz, erase_gmul;
1322 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1323 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1324 mmc->erase_grp_size = (erase_gsz + 1)
1328 mmc->hc_wp_grp_size = 1024
1329 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1330 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1332 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1335 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1340 err = sd_change_freq(mmc);
1342 err = mmc_change_freq(mmc);
1347 /* Restrict card's capabilities by what the host can do */
1348 mmc->card_caps &= mmc->cfg->host_caps;
1351 if (mmc->card_caps & MMC_MODE_4BIT) {
1352 cmd.cmdidx = MMC_CMD_APP_CMD;
1353 cmd.resp_type = MMC_RSP_R1;
1354 cmd.cmdarg = mmc->rca << 16;
1356 err = mmc_send_cmd(mmc, &cmd, NULL);
1360 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1361 cmd.resp_type = MMC_RSP_R1;
1363 err = mmc_send_cmd(mmc, &cmd, NULL);
1367 mmc_set_bus_width(mmc, 4);
1370 if (mmc->card_caps & MMC_MODE_HS)
1371 mmc->tran_speed = 50000000;
1373 mmc->tran_speed = 25000000;
1374 } else if (mmc->version >= MMC_VERSION_4) {
1375 /* Only version 4 of MMC supports wider bus widths */
1378 /* An array of possible bus widths in order of preference */
1379 static unsigned ext_csd_bits[] = {
1380 EXT_CSD_DDR_BUS_WIDTH_8,
1381 EXT_CSD_DDR_BUS_WIDTH_4,
1382 EXT_CSD_BUS_WIDTH_8,
1383 EXT_CSD_BUS_WIDTH_4,
1384 EXT_CSD_BUS_WIDTH_1,
1387 /* An array to map CSD bus widths to host cap bits */
1388 static unsigned ext_to_hostcaps[] = {
1389 [EXT_CSD_DDR_BUS_WIDTH_4] =
1390 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1391 [EXT_CSD_DDR_BUS_WIDTH_8] =
1392 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1393 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1394 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1397 /* An array to map chosen bus width to an integer */
1398 static unsigned widths[] = {
1402 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1403 unsigned int extw = ext_csd_bits[idx];
1404 unsigned int caps = ext_to_hostcaps[extw];
1407 * If the bus width is still not changed,
1408 * don't try to set the default again.
1409 * Otherwise, recover from switch attempts
1410 * by switching to 1-bit bus width.
1412 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1413 mmc->bus_width == 1) {
1419 * Check to make sure the card and controller support
1420 * these capabilities
1422 if ((mmc->card_caps & caps) != caps)
1425 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1426 EXT_CSD_BUS_WIDTH, extw);
1431 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1432 mmc_set_bus_width(mmc, widths[idx]);
1434 err = mmc_send_ext_csd(mmc, test_csd);
1439 /* Only compare read only fields */
1440 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1441 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1442 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1443 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1444 ext_csd[EXT_CSD_REV]
1445 == test_csd[EXT_CSD_REV] &&
1446 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1447 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1448 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1449 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1458 if (mmc->card_caps & MMC_MODE_HS) {
1459 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1460 mmc->tran_speed = 52000000;
1462 mmc->tran_speed = 26000000;
1466 mmc_set_clock(mmc, mmc->tran_speed);
1468 /* Fix the block length for DDR mode */
1469 if (mmc->ddr_mode) {
1470 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1471 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1474 /* fill in device description */
1475 bdesc = mmc_get_blk_desc(mmc);
1479 bdesc->blksz = mmc->read_bl_len;
1480 bdesc->log2blksz = LOG2(bdesc->blksz);
1481 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1482 #if !defined(CONFIG_SPL_BUILD) || \
1483 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1484 !defined(CONFIG_USE_TINY_PRINTF))
1485 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1486 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1487 (mmc->cid[3] >> 16) & 0xffff);
1488 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1489 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1490 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1491 (mmc->cid[2] >> 24) & 0xff);
1492 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1493 (mmc->cid[2] >> 16) & 0xf);
1495 bdesc->vendor[0] = 0;
1496 bdesc->product[0] = 0;
1497 bdesc->revision[0] = 0;
1499 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1506 static int mmc_send_if_cond(struct mmc *mmc)
1511 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1512 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1513 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1514 cmd.resp_type = MMC_RSP_R7;
1516 err = mmc_send_cmd(mmc, &cmd, NULL);
1521 if ((cmd.response[0] & 0xff) != 0xaa)
1522 return UNUSABLE_ERR;
1524 mmc->version = SD_VERSION_2;
1529 /* not used any more */
1530 int __deprecated mmc_register(struct mmc *mmc)
1532 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1533 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1538 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
1540 struct blk_desc *bdesc;
1543 /* quick validation */
1544 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1545 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1548 mmc = calloc(1, sizeof(*mmc));
1555 /* the following chunk was mmc_register() */
1557 /* Setup dsr related values */
1559 mmc->dsr = 0xffffffff;
1560 /* Setup the universal parts of the block interface just once */
1561 bdesc = mmc_get_blk_desc(mmc);
1562 bdesc->if_type = IF_TYPE_MMC;
1563 bdesc->removable = 1;
1564 bdesc->devnum = mmc_get_next_devnum();
1565 bdesc->block_read = mmc_bread;
1566 bdesc->block_write = mmc_bwrite;
1567 bdesc->block_erase = mmc_berase;
1569 /* setup initial part type */
1570 bdesc->part_type = mmc->cfg->part_type;
1576 void mmc_destroy(struct mmc *mmc)
1578 /* only freeing memory for now */
1582 static int mmc_get_dev(int dev, struct blk_desc **descp)
1584 struct mmc *mmc = find_mmc_device(dev);
1589 ret = mmc_init(mmc);
1593 *descp = &mmc->block_dev;
1598 /* board-specific MMC power initializations. */
1599 __weak void board_mmc_power_init(void)
1603 int mmc_start_init(struct mmc *mmc)
1607 /* we pretend there's no card when init is NULL */
1608 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
1610 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1611 printf("MMC: no card present\n");
1619 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1620 mmc_adapter_card_type_ident();
1622 board_mmc_power_init();
1624 /* made sure it's not NULL earlier */
1625 err = mmc->cfg->ops->init(mmc);
1631 mmc_set_bus_width(mmc, 1);
1632 mmc_set_clock(mmc, 1);
1634 /* Reset the Card */
1635 err = mmc_go_idle(mmc);
1640 /* The internal partition reset to user partition(0) at every CMD0*/
1641 mmc_get_blk_desc(mmc)->hwpart = 0;
1643 /* Test for SD version 2 */
1644 err = mmc_send_if_cond(mmc);
1646 /* Now try to get the SD card's operating condition */
1647 err = sd_send_op_cond(mmc);
1649 /* If the command timed out, we check for an MMC card */
1650 if (err == TIMEOUT) {
1651 err = mmc_send_op_cond(mmc);
1654 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1655 printf("Card did not respond to voltage select!\n");
1657 return UNUSABLE_ERR;
1662 mmc->init_in_progress = 1;
1667 static int mmc_complete_init(struct mmc *mmc)
1671 mmc->init_in_progress = 0;
1672 if (mmc->op_cond_pending)
1673 err = mmc_complete_op_cond(mmc);
1676 err = mmc_startup(mmc);
1684 int mmc_init(struct mmc *mmc)
1692 start = get_timer(0);
1694 if (!mmc->init_in_progress)
1695 err = mmc_start_init(mmc);
1698 err = mmc_complete_init(mmc);
1699 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
1703 int mmc_set_dsr(struct mmc *mmc, u16 val)
1709 /* CPU-specific MMC initializations */
1710 __weak int cpu_mmc_init(bd_t *bis)
1715 /* board-specific MMC initializations. */
1716 __weak int board_mmc_init(bd_t *bis)
1721 void mmc_set_preinit(struct mmc *mmc, int preinit)
1723 mmc->preinit = preinit;
1726 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
1727 static int mmc_probe(bd_t *bis)
1731 #elif defined(CONFIG_DM_MMC)
1732 static int mmc_probe(bd_t *bis)
1736 struct udevice *dev;
1738 ret = uclass_get(UCLASS_MMC, &uc);
1743 * Try to add them in sequence order. Really with driver model we
1744 * should allow holes, but the current MMC list does not allow that.
1745 * So if we request 0, 1, 3 we will get 0, 1, 2.
1747 for (i = 0; ; i++) {
1748 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1752 uclass_foreach_dev(dev, uc) {
1753 ret = device_probe(dev);
1755 printf("%s - probe failed: %d\n", dev->name, ret);
1761 static int mmc_probe(bd_t *bis)
1763 if (board_mmc_init(bis) < 0)
1770 int mmc_initialize(bd_t *bis)
1772 static int initialized = 0;
1774 if (initialized) /* Avoid initializing mmc multiple times */
1781 ret = mmc_probe(bis);
1785 #ifndef CONFIG_SPL_BUILD
1786 print_mmc_devices(',');
1793 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1795 * This function changes the size of boot partition and the size of rpmb
1796 * partition present on EMMC devices.
1799 * struct *mmc: pointer for the mmc device strcuture
1800 * bootsize: size of boot partition
1801 * rpmbsize: size of rpmb partition
1803 * Returns 0 on success.
1806 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1807 unsigned long rpmbsize)
1812 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1813 cmd.cmdidx = MMC_CMD_RES_MAN;
1814 cmd.resp_type = MMC_RSP_R1b;
1815 cmd.cmdarg = MMC_CMD62_ARG1;
1817 err = mmc_send_cmd(mmc, &cmd, NULL);
1819 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1823 /* Boot partition changing mode */
1824 cmd.cmdidx = MMC_CMD_RES_MAN;
1825 cmd.resp_type = MMC_RSP_R1b;
1826 cmd.cmdarg = MMC_CMD62_ARG2;
1828 err = mmc_send_cmd(mmc, &cmd, NULL);
1830 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1833 /* boot partition size is multiple of 128KB */
1834 bootsize = (bootsize * 1024) / 128;
1836 /* Arg: boot partition size */
1837 cmd.cmdidx = MMC_CMD_RES_MAN;
1838 cmd.resp_type = MMC_RSP_R1b;
1839 cmd.cmdarg = bootsize;
1841 err = mmc_send_cmd(mmc, &cmd, NULL);
1843 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1846 /* RPMB partition size is multiple of 128KB */
1847 rpmbsize = (rpmbsize * 1024) / 128;
1848 /* Arg: RPMB partition size */
1849 cmd.cmdidx = MMC_CMD_RES_MAN;
1850 cmd.resp_type = MMC_RSP_R1b;
1851 cmd.cmdarg = rpmbsize;
1853 err = mmc_send_cmd(mmc, &cmd, NULL);
1855 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1862 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1863 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1866 * Returns 0 on success.
1868 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1872 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1873 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1874 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1875 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1883 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1884 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1887 * Returns 0 on success.
1889 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1893 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1894 EXT_CSD_BOOT_ACK(ack) |
1895 EXT_CSD_BOOT_PART_NUM(part_num) |
1896 EXT_CSD_PARTITION_ACCESS(access));
1904 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1905 * for enable. Note that this is a write-once field for non-zero values.
1907 * Returns 0 on success.
1909 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1911 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
1916 U_BOOT_LEGACY_BLK(mmc) = {
1917 .if_typename = "mmc",
1918 .if_type = IF_TYPE_MMC,
1920 .get_dev = mmc_get_dev,
1921 .select_hwpart = mmc_select_hwpartp,