2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
18 #include <power/regulator.h>
21 #include <linux/list.h>
23 #include "mmc_private.h"
25 static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
33 #if CONFIG_IS_ENABLED(MMC_TINY)
34 static struct mmc mmc_static;
35 struct mmc *find_mmc_device(int dev_num)
40 void mmc_do_preinit(void)
42 struct mmc *m = &mmc_static;
43 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
44 mmc_set_preinit(m, 1);
50 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
52 return &mmc->block_dev;
56 #if !CONFIG_IS_ENABLED(DM_MMC)
57 __weak int board_mmc_getwp(struct mmc *mmc)
62 int mmc_getwp(struct mmc *mmc)
66 wp = board_mmc_getwp(mmc);
69 if (mmc->cfg->ops->getwp)
70 wp = mmc->cfg->ops->getwp(mmc);
78 __weak int board_mmc_getcd(struct mmc *mmc)
84 #ifdef CONFIG_MMC_TRACE
85 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
87 printf("CMD_SEND:%d\n", cmd->cmdidx);
88 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
91 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
97 printf("\t\tRET\t\t\t %d\n", ret);
99 switch (cmd->resp_type) {
101 printf("\t\tMMC_RSP_NONE\n");
104 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
108 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
112 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
114 printf("\t\t \t\t 0x%08X \n",
116 printf("\t\t \t\t 0x%08X \n",
118 printf("\t\t \t\t 0x%08X \n",
121 printf("\t\t\t\t\tDUMPING DATA\n");
122 for (i = 0; i < 4; i++) {
124 printf("\t\t\t\t\t%03d - ", i*4);
125 ptr = (u8 *)&cmd->response[i];
127 for (j = 0; j < 4; j++)
128 printf("%02X ", *ptr--);
133 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
137 printf("\t\tERROR MMC rsp not supported\n");
143 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
147 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
148 printf("CURR STATE:%d\n", status);
152 #if !CONFIG_IS_ENABLED(DM_MMC)
153 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
157 mmmc_trace_before_send(mmc, cmd);
158 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
159 mmmc_trace_after_send(mmc, cmd, ret);
165 int mmc_send_status(struct mmc *mmc, int timeout)
168 int err, retries = 5;
170 cmd.cmdidx = MMC_CMD_SEND_STATUS;
171 cmd.resp_type = MMC_RSP_R1;
172 if (!mmc_host_is_spi(mmc))
173 cmd.cmdarg = mmc->rca << 16;
176 err = mmc_send_cmd(mmc, &cmd, NULL);
178 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
179 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
182 else if (cmd.response[0] & MMC_STATUS_MASK) {
183 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
184 printf("Status Error: 0x%08X\n",
189 } else if (--retries < 0)
198 mmc_trace_state(mmc, &cmd);
200 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
201 printf("Timeout waiting card ready\n");
209 int mmc_set_blocklen(struct mmc *mmc, int len)
216 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
217 cmd.resp_type = MMC_RSP_R1;
220 return mmc_send_cmd(mmc, &cmd, NULL);
223 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
227 struct mmc_data data;
230 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
232 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
234 if (mmc->high_capacity)
237 cmd.cmdarg = start * mmc->read_bl_len;
239 cmd.resp_type = MMC_RSP_R1;
242 data.blocks = blkcnt;
243 data.blocksize = mmc->read_bl_len;
244 data.flags = MMC_DATA_READ;
246 if (mmc_send_cmd(mmc, &cmd, &data))
250 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
252 cmd.resp_type = MMC_RSP_R1b;
253 if (mmc_send_cmd(mmc, &cmd, NULL)) {
254 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
255 printf("mmc fail to send stop cmd\n");
264 #if CONFIG_IS_ENABLED(BLK)
265 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
267 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
271 #if CONFIG_IS_ENABLED(BLK)
272 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
274 int dev_num = block_dev->devnum;
276 lbaint_t cur, blocks_todo = blkcnt;
281 struct mmc *mmc = find_mmc_device(dev_num);
285 if (CONFIG_IS_ENABLED(MMC_TINY))
286 err = mmc_switch_part(mmc, block_dev->hwpart);
288 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
293 if ((start + blkcnt) > block_dev->lba) {
294 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
295 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
296 start + blkcnt, block_dev->lba);
301 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
302 debug("%s: Failed to set blocklen\n", __func__);
307 cur = (blocks_todo > mmc->cfg->b_max) ?
308 mmc->cfg->b_max : blocks_todo;
309 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
310 debug("%s: Failed to read blocks\n", __func__);
315 dst += cur * mmc->read_bl_len;
316 } while (blocks_todo > 0);
321 static int mmc_go_idle(struct mmc *mmc)
328 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
330 cmd.resp_type = MMC_RSP_NONE;
332 err = mmc_send_cmd(mmc, &cmd, NULL);
342 static int sd_send_op_cond(struct mmc *mmc)
349 cmd.cmdidx = MMC_CMD_APP_CMD;
350 cmd.resp_type = MMC_RSP_R1;
353 err = mmc_send_cmd(mmc, &cmd, NULL);
358 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
359 cmd.resp_type = MMC_RSP_R3;
362 * Most cards do not answer if some reserved bits
363 * in the ocr are set. However, Some controller
364 * can set bit 7 (reserved for low voltages), but
365 * how to manage low voltages SD card is not yet
368 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
369 (mmc->cfg->voltages & 0xff8000);
371 if (mmc->version == SD_VERSION_2)
372 cmd.cmdarg |= OCR_HCS;
374 err = mmc_send_cmd(mmc, &cmd, NULL);
379 if (cmd.response[0] & OCR_BUSY)
388 if (mmc->version != SD_VERSION_2)
389 mmc->version = SD_VERSION_1_0;
391 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
392 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
393 cmd.resp_type = MMC_RSP_R3;
396 err = mmc_send_cmd(mmc, &cmd, NULL);
402 mmc->ocr = cmd.response[0];
404 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
410 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
415 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
416 cmd.resp_type = MMC_RSP_R3;
418 if (use_arg && !mmc_host_is_spi(mmc))
419 cmd.cmdarg = OCR_HCS |
420 (mmc->cfg->voltages &
421 (mmc->ocr & OCR_VOLTAGE_MASK)) |
422 (mmc->ocr & OCR_ACCESS_MODE);
424 err = mmc_send_cmd(mmc, &cmd, NULL);
427 mmc->ocr = cmd.response[0];
431 static int mmc_send_op_cond(struct mmc *mmc)
435 /* Some cards seem to need this */
438 /* Asking to the card its capabilities */
439 for (i = 0; i < 2; i++) {
440 err = mmc_send_op_cond_iter(mmc, i != 0);
444 /* exit if not busy (flag seems to be inverted) */
445 if (mmc->ocr & OCR_BUSY)
448 mmc->op_cond_pending = 1;
452 static int mmc_complete_op_cond(struct mmc *mmc)
459 mmc->op_cond_pending = 0;
460 if (!(mmc->ocr & OCR_BUSY)) {
461 /* Some cards seem to need this */
464 start = get_timer(0);
466 err = mmc_send_op_cond_iter(mmc, 1);
469 if (mmc->ocr & OCR_BUSY)
471 if (get_timer(start) > timeout)
477 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
478 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
479 cmd.resp_type = MMC_RSP_R3;
482 err = mmc_send_cmd(mmc, &cmd, NULL);
487 mmc->ocr = cmd.response[0];
490 mmc->version = MMC_VERSION_UNKNOWN;
492 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
499 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
502 struct mmc_data data;
505 /* Get the Card Status Register */
506 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
507 cmd.resp_type = MMC_RSP_R1;
510 data.dest = (char *)ext_csd;
512 data.blocksize = MMC_MAX_BLOCK_LEN;
513 data.flags = MMC_DATA_READ;
515 err = mmc_send_cmd(mmc, &cmd, &data);
520 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
527 cmd.cmdidx = MMC_CMD_SWITCH;
528 cmd.resp_type = MMC_RSP_R1b;
529 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
533 while (retries > 0) {
534 ret = mmc_send_cmd(mmc, &cmd, NULL);
536 /* Waiting for the ready status */
538 ret = mmc_send_status(mmc, timeout);
549 static int mmc_change_freq(struct mmc *mmc)
551 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
557 if (mmc_host_is_spi(mmc))
560 /* Only version 4 supports high-speed */
561 if (mmc->version < MMC_VERSION_4)
564 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
566 err = mmc_send_ext_csd(mmc, ext_csd);
571 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
573 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
578 /* Now check to see that it worked */
579 err = mmc_send_ext_csd(mmc, ext_csd);
584 /* No high-speed support */
585 if (!ext_csd[EXT_CSD_HS_TIMING])
588 /* High Speed is set, there are two types: 52MHz and 26MHz */
589 if (cardtype & EXT_CSD_CARD_TYPE_52) {
590 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
591 mmc->card_caps |= MMC_MODE_DDR_52MHz;
592 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
594 mmc->card_caps |= MMC_MODE_HS;
600 static int mmc_set_capacity(struct mmc *mmc, int part_num)
604 mmc->capacity = mmc->capacity_user;
608 mmc->capacity = mmc->capacity_boot;
611 mmc->capacity = mmc->capacity_rpmb;
617 mmc->capacity = mmc->capacity_gp[part_num - 4];
623 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
628 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
632 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
633 (mmc->part_config & ~PART_ACCESS_MASK)
634 | (part_num & PART_ACCESS_MASK));
637 * Set the capacity if the switch succeeded or was intended
638 * to return to representing the raw device.
640 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
641 ret = mmc_set_capacity(mmc, part_num);
642 mmc_get_blk_desc(mmc)->hwpart = part_num;
648 int mmc_hwpart_config(struct mmc *mmc,
649 const struct mmc_hwpart_conf *conf,
650 enum mmc_hwpart_conf_mode mode)
656 u32 max_enh_size_mult;
657 u32 tot_enh_size_mult = 0;
660 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
662 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
665 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
666 printf("eMMC >= 4.4 required for enhanced user data area\n");
670 if (!(mmc->part_support & PART_SUPPORT)) {
671 printf("Card does not support partitioning\n");
675 if (!mmc->hc_wp_grp_size) {
676 printf("Card does not define HC WP group size\n");
680 /* check partition alignment and total enhanced size */
681 if (conf->user.enh_size) {
682 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
683 conf->user.enh_start % mmc->hc_wp_grp_size) {
684 printf("User data enhanced area not HC WP group "
688 part_attrs |= EXT_CSD_ENH_USR;
689 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
690 if (mmc->high_capacity) {
691 enh_start_addr = conf->user.enh_start;
693 enh_start_addr = (conf->user.enh_start << 9);
699 tot_enh_size_mult += enh_size_mult;
701 for (pidx = 0; pidx < 4; pidx++) {
702 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
703 printf("GP%i partition not HC WP group size "
704 "aligned\n", pidx+1);
707 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
708 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
709 part_attrs |= EXT_CSD_ENH_GP(pidx);
710 tot_enh_size_mult += gp_size_mult[pidx];
714 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
715 printf("Card does not support enhanced attribute\n");
719 err = mmc_send_ext_csd(mmc, ext_csd);
724 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
725 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
726 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
727 if (tot_enh_size_mult > max_enh_size_mult) {
728 printf("Total enhanced size exceeds maximum (%u > %u)\n",
729 tot_enh_size_mult, max_enh_size_mult);
733 /* The default value of EXT_CSD_WR_REL_SET is device
734 * dependent, the values can only be changed if the
735 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
736 * changed only once and before partitioning is completed. */
737 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
738 if (conf->user.wr_rel_change) {
739 if (conf->user.wr_rel_set)
740 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
742 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
744 for (pidx = 0; pidx < 4; pidx++) {
745 if (conf->gp_part[pidx].wr_rel_change) {
746 if (conf->gp_part[pidx].wr_rel_set)
747 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
749 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
753 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
754 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
755 puts("Card does not support host controlled partition write "
756 "reliability settings\n");
760 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
761 EXT_CSD_PARTITION_SETTING_COMPLETED) {
762 printf("Card already partitioned\n");
766 if (mode == MMC_HWPART_CONF_CHECK)
769 /* Partitioning requires high-capacity size definitions */
770 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
771 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
772 EXT_CSD_ERASE_GROUP_DEF, 1);
777 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
779 /* update erase group size to be high-capacity */
780 mmc->erase_grp_size =
781 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
785 /* all OK, write the configuration */
786 for (i = 0; i < 4; i++) {
787 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
788 EXT_CSD_ENH_START_ADDR+i,
789 (enh_start_addr >> (i*8)) & 0xFF);
793 for (i = 0; i < 3; i++) {
794 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
795 EXT_CSD_ENH_SIZE_MULT+i,
796 (enh_size_mult >> (i*8)) & 0xFF);
800 for (pidx = 0; pidx < 4; pidx++) {
801 for (i = 0; i < 3; i++) {
802 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
803 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
804 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
809 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
810 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
814 if (mode == MMC_HWPART_CONF_SET)
817 /* The WR_REL_SET is a write-once register but shall be
818 * written before setting PART_SETTING_COMPLETED. As it is
819 * write-once we can only write it when completing the
821 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
822 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
823 EXT_CSD_WR_REL_SET, wr_rel_set);
828 /* Setting PART_SETTING_COMPLETED confirms the partition
829 * configuration but it only becomes effective after power
830 * cycle, so we do not adjust the partition related settings
831 * in the mmc struct. */
833 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
834 EXT_CSD_PARTITION_SETTING,
835 EXT_CSD_PARTITION_SETTING_COMPLETED);
842 #if !CONFIG_IS_ENABLED(DM_MMC)
843 int mmc_getcd(struct mmc *mmc)
847 cd = board_mmc_getcd(mmc);
850 if (mmc->cfg->ops->getcd)
851 cd = mmc->cfg->ops->getcd(mmc);
860 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
863 struct mmc_data data;
865 /* Switch the frequency */
866 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
867 cmd.resp_type = MMC_RSP_R1;
868 cmd.cmdarg = (mode << 31) | 0xffffff;
869 cmd.cmdarg &= ~(0xf << (group * 4));
870 cmd.cmdarg |= value << (group * 4);
872 data.dest = (char *)resp;
875 data.flags = MMC_DATA_READ;
877 return mmc_send_cmd(mmc, &cmd, &data);
881 static int sd_change_freq(struct mmc *mmc)
885 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
886 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
887 struct mmc_data data;
892 if (mmc_host_is_spi(mmc))
895 /* Read the SCR to find out if this card supports higher speeds */
896 cmd.cmdidx = MMC_CMD_APP_CMD;
897 cmd.resp_type = MMC_RSP_R1;
898 cmd.cmdarg = mmc->rca << 16;
900 err = mmc_send_cmd(mmc, &cmd, NULL);
905 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
906 cmd.resp_type = MMC_RSP_R1;
912 data.dest = (char *)scr;
915 data.flags = MMC_DATA_READ;
917 err = mmc_send_cmd(mmc, &cmd, &data);
926 mmc->scr[0] = __be32_to_cpu(scr[0]);
927 mmc->scr[1] = __be32_to_cpu(scr[1]);
929 switch ((mmc->scr[0] >> 24) & 0xf) {
931 mmc->version = SD_VERSION_1_0;
934 mmc->version = SD_VERSION_1_10;
937 mmc->version = SD_VERSION_2;
938 if ((mmc->scr[0] >> 15) & 0x1)
939 mmc->version = SD_VERSION_3;
942 mmc->version = SD_VERSION_1_0;
946 if (mmc->scr[0] & SD_DATA_4BIT)
947 mmc->card_caps |= MMC_MODE_4BIT;
949 /* Version 1.0 doesn't support switching */
950 if (mmc->version == SD_VERSION_1_0)
955 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
956 (u8 *)switch_status);
961 /* The high-speed function is busy. Try again */
962 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
966 /* If high-speed isn't supported, we return */
967 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
971 * If the host doesn't support SD_HIGHSPEED, do not switch card to
972 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
973 * This can avoid furthur problem when the card runs in different
974 * mode between the host.
976 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
977 (mmc->cfg->host_caps & MMC_MODE_HS)))
980 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
985 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
986 mmc->card_caps |= MMC_MODE_HS;
991 static int sd_read_ssr(struct mmc *mmc)
995 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
996 struct mmc_data data;
998 unsigned int au, eo, et, es;
1000 cmd.cmdidx = MMC_CMD_APP_CMD;
1001 cmd.resp_type = MMC_RSP_R1;
1002 cmd.cmdarg = mmc->rca << 16;
1004 err = mmc_send_cmd(mmc, &cmd, NULL);
1008 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1009 cmd.resp_type = MMC_RSP_R1;
1013 data.dest = (char *)ssr;
1014 data.blocksize = 64;
1016 data.flags = MMC_DATA_READ;
1018 err = mmc_send_cmd(mmc, &cmd, &data);
1026 for (i = 0; i < 16; i++)
1027 ssr[i] = be32_to_cpu(ssr[i]);
1029 au = (ssr[2] >> 12) & 0xF;
1030 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1031 mmc->ssr.au = sd_au_size[au];
1032 es = (ssr[3] >> 24) & 0xFF;
1033 es |= (ssr[2] & 0xFF) << 8;
1034 et = (ssr[3] >> 18) & 0x3F;
1036 eo = (ssr[3] >> 16) & 0x3;
1037 mmc->ssr.erase_timeout = (et * 1000) / es;
1038 mmc->ssr.erase_offset = eo * 1000;
1041 debug("Invalid Allocation Unit Size.\n");
1047 /* frequency bases */
1048 /* divided by 10 to be nice to platforms without floating point */
1049 static const int fbase[] = {
1056 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1057 * to platforms without floating point.
1059 static const u8 multipliers[] = {
1078 #if !CONFIG_IS_ENABLED(DM_MMC)
1079 static void mmc_set_ios(struct mmc *mmc)
1081 if (mmc->cfg->ops->set_ios)
1082 mmc->cfg->ops->set_ios(mmc);
1086 void mmc_set_clock(struct mmc *mmc, uint clock)
1088 if (clock > mmc->cfg->f_max)
1089 clock = mmc->cfg->f_max;
1091 if (clock < mmc->cfg->f_min)
1092 clock = mmc->cfg->f_min;
1099 static void mmc_set_bus_width(struct mmc *mmc, uint width)
1101 mmc->bus_width = width;
1106 static int sd_select_bus_freq_width(struct mmc *mmc)
1111 err = sd_change_freq(mmc);
1115 /* Restrict card's capabilities by what the host can do */
1116 mmc->card_caps &= mmc->cfg->host_caps;
1118 if (mmc->card_caps & MMC_MODE_4BIT) {
1119 cmd.cmdidx = MMC_CMD_APP_CMD;
1120 cmd.resp_type = MMC_RSP_R1;
1121 cmd.cmdarg = mmc->rca << 16;
1123 err = mmc_send_cmd(mmc, &cmd, NULL);
1127 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1128 cmd.resp_type = MMC_RSP_R1;
1130 err = mmc_send_cmd(mmc, &cmd, NULL);
1134 mmc_set_bus_width(mmc, 4);
1137 err = sd_read_ssr(mmc);
1141 if (mmc->card_caps & MMC_MODE_HS)
1142 mmc->tran_speed = 50000000;
1144 mmc->tran_speed = 25000000;
1150 * read the compare the part of ext csd that is constant.
1151 * This can be used to check that the transfer is working
1154 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1157 const u8 *ext_csd = mmc->ext_csd;
1158 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1160 err = mmc_send_ext_csd(mmc, test_csd);
1164 /* Only compare read only fields */
1165 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1166 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1167 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1168 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1169 ext_csd[EXT_CSD_REV]
1170 == test_csd[EXT_CSD_REV] &&
1171 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1172 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1173 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1174 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1180 static int mmc_select_bus_freq_width(struct mmc *mmc)
1182 /* An array of possible bus widths in order of preference */
1183 static const unsigned int ext_csd_bits[] = {
1184 EXT_CSD_DDR_BUS_WIDTH_8,
1185 EXT_CSD_DDR_BUS_WIDTH_4,
1186 EXT_CSD_BUS_WIDTH_8,
1187 EXT_CSD_BUS_WIDTH_4,
1188 EXT_CSD_BUS_WIDTH_1,
1190 /* An array to map CSD bus widths to host cap bits */
1191 static const unsigned int ext_to_hostcaps[] = {
1192 [EXT_CSD_DDR_BUS_WIDTH_4] =
1193 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1194 [EXT_CSD_DDR_BUS_WIDTH_8] =
1195 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1196 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1197 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1199 /* An array to map chosen bus width to an integer */
1200 static const unsigned int widths[] = {
1206 err = mmc_change_freq(mmc);
1210 /* Restrict card's capabilities by what the host can do */
1211 mmc->card_caps &= mmc->cfg->host_caps;
1213 /* Only version 4 of MMC supports wider bus widths */
1214 if (mmc->version < MMC_VERSION_4)
1217 if (!mmc->ext_csd) {
1218 debug("No ext_csd found!\n"); /* this should enver happen */
1222 for (idx = 0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1223 unsigned int extw = ext_csd_bits[idx];
1224 unsigned int caps = ext_to_hostcaps[extw];
1226 * If the bus width is still not changed,
1227 * don't try to set the default again.
1228 * Otherwise, recover from switch attempts
1229 * by switching to 1-bit bus width.
1231 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1232 mmc->bus_width == 1) {
1238 * Check to make sure the card and controller support
1239 * these capabilities
1241 if ((mmc->card_caps & caps) != caps)
1244 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1245 EXT_CSD_BUS_WIDTH, extw);
1250 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1251 mmc_set_bus_width(mmc, widths[idx]);
1253 err = mmc_read_and_compare_ext_csd(mmc);
1261 if (mmc->card_caps & MMC_MODE_HS) {
1262 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1263 mmc->tran_speed = 52000000;
1265 mmc->tran_speed = 26000000;
1271 static int mmc_startup_v4(struct mmc *mmc)
1275 bool has_parts = false;
1276 bool part_completed;
1279 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1282 ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN);
1286 mmc->ext_csd = ext_csd;
1288 /* check ext_csd version and capacity */
1289 err = mmc_send_ext_csd(mmc, ext_csd);
1292 if (ext_csd[EXT_CSD_REV] >= 2) {
1294 * According to the JEDEC Standard, the value of
1295 * ext_csd's capacity is valid if the value is more
1298 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1299 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1300 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1301 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1302 capacity *= MMC_MAX_BLOCK_LEN;
1303 if ((capacity >> 20) > 2 * 1024)
1304 mmc->capacity_user = capacity;
1307 switch (ext_csd[EXT_CSD_REV]) {
1309 mmc->version = MMC_VERSION_4_1;
1312 mmc->version = MMC_VERSION_4_2;
1315 mmc->version = MMC_VERSION_4_3;
1318 mmc->version = MMC_VERSION_4_41;
1321 mmc->version = MMC_VERSION_4_5;
1324 mmc->version = MMC_VERSION_5_0;
1327 mmc->version = MMC_VERSION_5_1;
1331 /* The partition data may be non-zero but it is only
1332 * effective if PARTITION_SETTING_COMPLETED is set in
1333 * EXT_CSD, so ignore any data if this bit is not set,
1334 * except for enabling the high-capacity group size
1335 * definition (see below).
1337 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1338 EXT_CSD_PARTITION_SETTING_COMPLETED);
1340 /* store the partition info of emmc */
1341 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1342 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1343 ext_csd[EXT_CSD_BOOT_MULT])
1344 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1345 if (part_completed &&
1346 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1347 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1349 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1351 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1353 for (i = 0; i < 4; i++) {
1354 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1355 uint mult = (ext_csd[idx + 2] << 16) +
1356 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1359 if (!part_completed)
1361 mmc->capacity_gp[i] = mult;
1362 mmc->capacity_gp[i] *=
1363 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1364 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1365 mmc->capacity_gp[i] <<= 19;
1368 if (part_completed) {
1369 mmc->enh_user_size =
1370 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1371 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1372 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1373 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1374 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1375 mmc->enh_user_size <<= 19;
1376 mmc->enh_user_start =
1377 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1378 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1379 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1380 ext_csd[EXT_CSD_ENH_START_ADDR];
1381 if (mmc->high_capacity)
1382 mmc->enh_user_start <<= 9;
1386 * Host needs to enable ERASE_GRP_DEF bit if device is
1387 * partitioned. This bit will be lost every time after a reset
1388 * or power off. This will affect erase size.
1392 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1393 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1396 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1397 EXT_CSD_ERASE_GROUP_DEF, 1);
1402 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1405 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1406 /* Read out group size from ext_csd */
1407 mmc->erase_grp_size =
1408 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1410 * if high capacity and partition setting completed
1411 * SEC_COUNT is valid even if it is smaller than 2 GiB
1412 * JEDEC Standard JESD84-B45, 6.2.4
1414 if (mmc->high_capacity && part_completed) {
1415 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1416 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1417 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1418 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1419 capacity *= MMC_MAX_BLOCK_LEN;
1420 mmc->capacity_user = capacity;
1423 /* Calculate the group size from the csd value. */
1424 int erase_gsz, erase_gmul;
1426 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1427 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1428 mmc->erase_grp_size = (erase_gsz + 1)
1432 mmc->hc_wp_grp_size = 1024
1433 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1434 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1436 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1441 static int mmc_startup(struct mmc *mmc)
1447 struct blk_desc *bdesc;
1449 #ifdef CONFIG_MMC_SPI_CRC_ON
1450 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1451 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1452 cmd.resp_type = MMC_RSP_R1;
1454 err = mmc_send_cmd(mmc, &cmd, NULL);
1461 /* Put the Card in Identify Mode */
1462 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1463 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1464 cmd.resp_type = MMC_RSP_R2;
1467 err = mmc_send_cmd(mmc, &cmd, NULL);
1472 memcpy(mmc->cid, cmd.response, 16);
1475 * For MMC cards, set the Relative Address.
1476 * For SD cards, get the Relatvie Address.
1477 * This also puts the cards into Standby State
1479 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1480 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1481 cmd.cmdarg = mmc->rca << 16;
1482 cmd.resp_type = MMC_RSP_R6;
1484 err = mmc_send_cmd(mmc, &cmd, NULL);
1490 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1493 /* Get the Card-Specific Data */
1494 cmd.cmdidx = MMC_CMD_SEND_CSD;
1495 cmd.resp_type = MMC_RSP_R2;
1496 cmd.cmdarg = mmc->rca << 16;
1498 err = mmc_send_cmd(mmc, &cmd, NULL);
1503 mmc->csd[0] = cmd.response[0];
1504 mmc->csd[1] = cmd.response[1];
1505 mmc->csd[2] = cmd.response[2];
1506 mmc->csd[3] = cmd.response[3];
1508 if (mmc->version == MMC_VERSION_UNKNOWN) {
1509 int version = (cmd.response[0] >> 26) & 0xf;
1513 mmc->version = MMC_VERSION_1_2;
1516 mmc->version = MMC_VERSION_1_4;
1519 mmc->version = MMC_VERSION_2_2;
1522 mmc->version = MMC_VERSION_3;
1525 mmc->version = MMC_VERSION_4;
1528 mmc->version = MMC_VERSION_1_2;
1533 /* divide frequency by 10, since the mults are 10x bigger */
1534 freq = fbase[(cmd.response[0] & 0x7)];
1535 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1537 mmc->tran_speed = freq * mult;
1539 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1540 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1543 mmc->write_bl_len = mmc->read_bl_len;
1545 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1547 if (mmc->high_capacity) {
1548 csize = (mmc->csd[1] & 0x3f) << 16
1549 | (mmc->csd[2] & 0xffff0000) >> 16;
1552 csize = (mmc->csd[1] & 0x3ff) << 2
1553 | (mmc->csd[2] & 0xc0000000) >> 30;
1554 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1557 mmc->capacity_user = (csize + 1) << (cmult + 2);
1558 mmc->capacity_user *= mmc->read_bl_len;
1559 mmc->capacity_boot = 0;
1560 mmc->capacity_rpmb = 0;
1561 for (i = 0; i < 4; i++)
1562 mmc->capacity_gp[i] = 0;
1564 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1565 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1567 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1568 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1570 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1571 cmd.cmdidx = MMC_CMD_SET_DSR;
1572 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1573 cmd.resp_type = MMC_RSP_NONE;
1574 if (mmc_send_cmd(mmc, &cmd, NULL))
1575 printf("MMC: SET_DSR failed\n");
1578 /* Select the card, and put it into Transfer Mode */
1579 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1580 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1581 cmd.resp_type = MMC_RSP_R1;
1582 cmd.cmdarg = mmc->rca << 16;
1583 err = mmc_send_cmd(mmc, &cmd, NULL);
1590 * For SD, its erase group is always one sector
1592 mmc->erase_grp_size = 1;
1593 mmc->part_config = MMCPART_NOAVAILABLE;
1595 err = mmc_startup_v4(mmc);
1599 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1604 err = sd_select_bus_freq_width(mmc);
1606 err = mmc_select_bus_freq_width(mmc);
1611 mmc_set_clock(mmc, mmc->tran_speed);
1613 /* Fix the block length for DDR mode */
1614 if (mmc->ddr_mode) {
1615 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1616 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1619 /* fill in device description */
1620 bdesc = mmc_get_blk_desc(mmc);
1624 bdesc->blksz = mmc->read_bl_len;
1625 bdesc->log2blksz = LOG2(bdesc->blksz);
1626 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1627 #if !defined(CONFIG_SPL_BUILD) || \
1628 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1629 !defined(CONFIG_USE_TINY_PRINTF))
1630 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1631 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1632 (mmc->cid[3] >> 16) & 0xffff);
1633 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1634 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1635 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1636 (mmc->cid[2] >> 24) & 0xff);
1637 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1638 (mmc->cid[2] >> 16) & 0xf);
1640 bdesc->vendor[0] = 0;
1641 bdesc->product[0] = 0;
1642 bdesc->revision[0] = 0;
1644 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1651 static int mmc_send_if_cond(struct mmc *mmc)
1656 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1657 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1658 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1659 cmd.resp_type = MMC_RSP_R7;
1661 err = mmc_send_cmd(mmc, &cmd, NULL);
1666 if ((cmd.response[0] & 0xff) != 0xaa)
1669 mmc->version = SD_VERSION_2;
1674 #if !CONFIG_IS_ENABLED(DM_MMC)
1675 /* board-specific MMC power initializations. */
1676 __weak void board_mmc_power_init(void)
1681 static int mmc_power_init(struct mmc *mmc)
1683 #if CONFIG_IS_ENABLED(DM_MMC)
1684 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1687 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
1690 debug("%s: No vmmc supply\n", mmc->dev->name);
1692 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
1693 &mmc->vqmmc_supply);
1695 debug("%s: No vqmmc supply\n", mmc->dev->name);
1697 if (mmc->vmmc_supply) {
1698 ret = regulator_set_enable(mmc->vmmc_supply, true);
1700 puts("Error enabling VMMC supply\n");
1705 #else /* !CONFIG_DM_MMC */
1707 * Driver model should use a regulator, as above, rather than calling
1708 * out to board code.
1710 board_mmc_power_init();
1715 int mmc_start_init(struct mmc *mmc)
1720 /* we pretend there's no card when init is NULL */
1721 no_card = mmc_getcd(mmc) == 0;
1722 #if !CONFIG_IS_ENABLED(DM_MMC)
1723 no_card = no_card || (mmc->cfg->ops->init == NULL);
1727 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1728 printf("MMC: no card present\n");
1736 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1737 mmc_adapter_card_type_ident();
1739 err = mmc_power_init(mmc);
1743 #if CONFIG_IS_ENABLED(DM_MMC)
1744 /* The device has already been probed ready for use */
1746 /* made sure it's not NULL earlier */
1747 err = mmc->cfg->ops->init(mmc);
1752 mmc_set_bus_width(mmc, 1);
1753 mmc_set_clock(mmc, 1);
1755 /* Reset the Card */
1756 err = mmc_go_idle(mmc);
1761 /* The internal partition reset to user partition(0) at every CMD0*/
1762 mmc_get_blk_desc(mmc)->hwpart = 0;
1764 /* Test for SD version 2 */
1765 err = mmc_send_if_cond(mmc);
1767 /* Now try to get the SD card's operating condition */
1768 err = sd_send_op_cond(mmc);
1770 /* If the command timed out, we check for an MMC card */
1771 if (err == -ETIMEDOUT) {
1772 err = mmc_send_op_cond(mmc);
1775 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1776 printf("Card did not respond to voltage select!\n");
1783 mmc->init_in_progress = 1;
1788 static int mmc_complete_init(struct mmc *mmc)
1792 mmc->init_in_progress = 0;
1793 if (mmc->op_cond_pending)
1794 err = mmc_complete_op_cond(mmc);
1797 err = mmc_startup(mmc);
1805 int mmc_init(struct mmc *mmc)
1808 __maybe_unused unsigned start;
1809 #if CONFIG_IS_ENABLED(DM_MMC)
1810 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
1817 start = get_timer(0);
1819 if (!mmc->init_in_progress)
1820 err = mmc_start_init(mmc);
1823 err = mmc_complete_init(mmc);
1825 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
1830 int mmc_set_dsr(struct mmc *mmc, u16 val)
1836 /* CPU-specific MMC initializations */
1837 __weak int cpu_mmc_init(bd_t *bis)
1842 /* board-specific MMC initializations. */
1843 __weak int board_mmc_init(bd_t *bis)
1848 void mmc_set_preinit(struct mmc *mmc, int preinit)
1850 mmc->preinit = preinit;
1853 #if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
1854 static int mmc_probe(bd_t *bis)
1858 #elif CONFIG_IS_ENABLED(DM_MMC)
1859 static int mmc_probe(bd_t *bis)
1863 struct udevice *dev;
1865 ret = uclass_get(UCLASS_MMC, &uc);
1870 * Try to add them in sequence order. Really with driver model we
1871 * should allow holes, but the current MMC list does not allow that.
1872 * So if we request 0, 1, 3 we will get 0, 1, 2.
1874 for (i = 0; ; i++) {
1875 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1879 uclass_foreach_dev(dev, uc) {
1880 ret = device_probe(dev);
1882 printf("%s - probe failed: %d\n", dev->name, ret);
1888 static int mmc_probe(bd_t *bis)
1890 if (board_mmc_init(bis) < 0)
1897 int mmc_initialize(bd_t *bis)
1899 static int initialized = 0;
1901 if (initialized) /* Avoid initializing mmc multiple times */
1905 #if !CONFIG_IS_ENABLED(BLK)
1906 #if !CONFIG_IS_ENABLED(MMC_TINY)
1910 ret = mmc_probe(bis);
1914 #ifndef CONFIG_SPL_BUILD
1915 print_mmc_devices(',');
1922 #ifdef CONFIG_CMD_BKOPS_ENABLE
1923 int mmc_set_bkops_enable(struct mmc *mmc)
1926 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1928 err = mmc_send_ext_csd(mmc, ext_csd);
1930 puts("Could not get ext_csd register values\n");
1934 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
1935 puts("Background operations not supported on device\n");
1936 return -EMEDIUMTYPE;
1939 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
1940 puts("Background operations already enabled\n");
1944 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
1946 puts("Failed to enable manual background operations\n");
1950 puts("Enabled manual background operations\n");