2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/list.h>
19 #include "mmc_private.h"
21 static struct list_head mmc_devices;
22 static int cur_dev_num = -1;
24 __weak int board_mmc_getwp(struct mmc *mmc)
29 int mmc_getwp(struct mmc *mmc)
33 wp = board_mmc_getwp(mmc);
36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
45 __weak int board_mmc_getcd(struct mmc *mmc)
50 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
54 #ifdef CONFIG_MMC_TRACE
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
61 switch (cmd->resp_type) {
63 printf("\t\tMMC_RSP_NONE\n");
66 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
70 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
74 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
76 printf("\t\t \t\t 0x%08X \n",
78 printf("\t\t \t\t 0x%08X \n",
80 printf("\t\t \t\t 0x%08X \n",
83 printf("\t\t\t\t\tDUMPING DATA\n");
84 for (i = 0; i < 4; i++) {
86 printf("\t\t\t\t\t%03d - ", i*4);
87 ptr = (u8 *)&cmd->response[i];
89 for (j = 0; j < 4; j++)
90 printf("%02X ", *ptr--);
95 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
99 printf("\t\tERROR MMC rsp not supported\n");
103 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
108 int mmc_send_status(struct mmc *mmc, int timeout)
111 int err, retries = 5;
112 #ifdef CONFIG_MMC_TRACE
116 cmd.cmdidx = MMC_CMD_SEND_STATUS;
117 cmd.resp_type = MMC_RSP_R1;
118 if (!mmc_host_is_spi(mmc))
119 cmd.cmdarg = mmc->rca << 16;
122 err = mmc_send_cmd(mmc, &cmd, NULL);
124 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
125 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
128 else if (cmd.response[0] & MMC_STATUS_MASK) {
129 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
130 printf("Status Error: 0x%08X\n",
135 } else if (--retries < 0)
144 #ifdef CONFIG_MMC_TRACE
145 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
146 printf("CURR STATE:%d\n", status);
149 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
150 printf("Timeout waiting card ready\n");
154 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
160 int mmc_set_blocklen(struct mmc *mmc, int len)
167 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
168 cmd.resp_type = MMC_RSP_R1;
171 return mmc_send_cmd(mmc, &cmd, NULL);
174 struct mmc *find_mmc_device(int dev_num)
177 struct list_head *entry;
179 list_for_each(entry, &mmc_devices) {
180 m = list_entry(entry, struct mmc, link);
182 if (m->block_dev.dev == dev_num)
186 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
187 printf("MMC Device %d not found\n", dev_num);
193 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
197 struct mmc_data data;
200 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
202 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
204 if (mmc->high_capacity)
207 cmd.cmdarg = start * mmc->read_bl_len;
209 cmd.resp_type = MMC_RSP_R1;
212 data.blocks = blkcnt;
213 data.blocksize = mmc->read_bl_len;
214 data.flags = MMC_DATA_READ;
216 if (mmc_send_cmd(mmc, &cmd, &data))
220 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
222 cmd.resp_type = MMC_RSP_R1b;
223 if (mmc_send_cmd(mmc, &cmd, NULL)) {
224 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
225 printf("mmc fail to send stop cmd\n");
234 static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
236 lbaint_t cur, blocks_todo = blkcnt;
241 struct mmc *mmc = find_mmc_device(dev_num);
245 if ((start + blkcnt) > mmc->block_dev.lba) {
246 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
247 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
248 start + blkcnt, mmc->block_dev.lba);
253 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
254 debug("%s: Failed to set blocklen\n", __func__);
259 cur = (blocks_todo > mmc->cfg->b_max) ?
260 mmc->cfg->b_max : blocks_todo;
261 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
262 debug("%s: Failed to read blocks\n", __func__);
267 dst += cur * mmc->read_bl_len;
268 } while (blocks_todo > 0);
273 static int mmc_go_idle(struct mmc *mmc)
280 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
282 cmd.resp_type = MMC_RSP_NONE;
284 err = mmc_send_cmd(mmc, &cmd, NULL);
294 static int sd_send_op_cond(struct mmc *mmc)
301 cmd.cmdidx = MMC_CMD_APP_CMD;
302 cmd.resp_type = MMC_RSP_R1;
305 err = mmc_send_cmd(mmc, &cmd, NULL);
310 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
311 cmd.resp_type = MMC_RSP_R3;
314 * Most cards do not answer if some reserved bits
315 * in the ocr are set. However, Some controller
316 * can set bit 7 (reserved for low voltages), but
317 * how to manage low voltages SD card is not yet
320 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
321 (mmc->cfg->voltages & 0xff8000);
323 if (mmc->version == SD_VERSION_2)
324 cmd.cmdarg |= OCR_HCS;
326 err = mmc_send_cmd(mmc, &cmd, NULL);
331 if (cmd.response[0] & OCR_BUSY)
340 if (mmc->version != SD_VERSION_2)
341 mmc->version = SD_VERSION_1_0;
343 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
344 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
345 cmd.resp_type = MMC_RSP_R3;
348 err = mmc_send_cmd(mmc, &cmd, NULL);
354 mmc->ocr = cmd.response[0];
356 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
362 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
367 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
368 cmd.resp_type = MMC_RSP_R3;
370 if (use_arg && !mmc_host_is_spi(mmc))
371 cmd.cmdarg = OCR_HCS |
372 (mmc->cfg->voltages &
373 (mmc->ocr & OCR_VOLTAGE_MASK)) |
374 (mmc->ocr & OCR_ACCESS_MODE);
376 err = mmc_send_cmd(mmc, &cmd, NULL);
379 mmc->ocr = cmd.response[0];
383 static int mmc_send_op_cond(struct mmc *mmc)
387 /* Some cards seem to need this */
390 /* Asking to the card its capabilities */
391 for (i = 0; i < 2; i++) {
392 err = mmc_send_op_cond_iter(mmc, i != 0);
396 /* exit if not busy (flag seems to be inverted) */
397 if (mmc->ocr & OCR_BUSY)
400 mmc->op_cond_pending = 1;
404 static int mmc_complete_op_cond(struct mmc *mmc)
411 mmc->op_cond_pending = 0;
412 if (!(mmc->ocr & OCR_BUSY)) {
413 start = get_timer(0);
415 err = mmc_send_op_cond_iter(mmc, 1);
418 if (mmc->ocr & OCR_BUSY)
420 if (get_timer(start) > timeout)
426 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
427 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
428 cmd.resp_type = MMC_RSP_R3;
431 err = mmc_send_cmd(mmc, &cmd, NULL);
436 mmc->ocr = cmd.response[0];
439 mmc->version = MMC_VERSION_UNKNOWN;
441 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
448 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
451 struct mmc_data data;
454 /* Get the Card Status Register */
455 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
456 cmd.resp_type = MMC_RSP_R1;
459 data.dest = (char *)ext_csd;
461 data.blocksize = MMC_MAX_BLOCK_LEN;
462 data.flags = MMC_DATA_READ;
464 err = mmc_send_cmd(mmc, &cmd, &data);
470 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
476 cmd.cmdidx = MMC_CMD_SWITCH;
477 cmd.resp_type = MMC_RSP_R1b;
478 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
482 ret = mmc_send_cmd(mmc, &cmd, NULL);
484 /* Waiting for the ready status */
486 ret = mmc_send_status(mmc, timeout);
492 static int mmc_change_freq(struct mmc *mmc)
494 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
500 if (mmc_host_is_spi(mmc))
503 /* Only version 4 supports high-speed */
504 if (mmc->version < MMC_VERSION_4)
507 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
509 err = mmc_send_ext_csd(mmc, ext_csd);
514 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
516 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
519 return err == SWITCH_ERR ? 0 : err;
521 /* Now check to see that it worked */
522 err = mmc_send_ext_csd(mmc, ext_csd);
527 /* No high-speed support */
528 if (!ext_csd[EXT_CSD_HS_TIMING])
531 /* High Speed is set, there are two types: 52MHz and 26MHz */
532 if (cardtype & EXT_CSD_CARD_TYPE_52) {
533 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
534 mmc->card_caps |= MMC_MODE_DDR_52MHz;
535 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
537 mmc->card_caps |= MMC_MODE_HS;
543 static int mmc_set_capacity(struct mmc *mmc, int part_num)
547 mmc->capacity = mmc->capacity_user;
551 mmc->capacity = mmc->capacity_boot;
554 mmc->capacity = mmc->capacity_rpmb;
560 mmc->capacity = mmc->capacity_gp[part_num - 4];
566 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
571 int mmc_select_hwpart(int dev_num, int hwpart)
573 struct mmc *mmc = find_mmc_device(dev_num);
579 if (mmc->part_num == hwpart)
582 if (mmc->part_config == MMCPART_NOAVAILABLE) {
583 printf("Card doesn't support part_switch\n");
587 ret = mmc_switch_part(dev_num, hwpart);
591 mmc->part_num = hwpart;
597 int mmc_switch_part(int dev_num, unsigned int part_num)
599 struct mmc *mmc = find_mmc_device(dev_num);
605 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
606 (mmc->part_config & ~PART_ACCESS_MASK)
607 | (part_num & PART_ACCESS_MASK));
610 * Set the capacity if the switch succeeded or was intended
611 * to return to representing the raw device.
613 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
614 ret = mmc_set_capacity(mmc, part_num);
619 int mmc_hwpart_config(struct mmc *mmc,
620 const struct mmc_hwpart_conf *conf,
621 enum mmc_hwpart_conf_mode mode)
627 u32 max_enh_size_mult;
628 u32 tot_enh_size_mult = 0;
631 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
633 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
636 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
637 printf("eMMC >= 4.4 required for enhanced user data area\n");
641 if (!(mmc->part_support & PART_SUPPORT)) {
642 printf("Card does not support partitioning\n");
646 if (!mmc->hc_wp_grp_size) {
647 printf("Card does not define HC WP group size\n");
651 /* check partition alignment and total enhanced size */
652 if (conf->user.enh_size) {
653 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
654 conf->user.enh_start % mmc->hc_wp_grp_size) {
655 printf("User data enhanced area not HC WP group "
659 part_attrs |= EXT_CSD_ENH_USR;
660 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
661 if (mmc->high_capacity) {
662 enh_start_addr = conf->user.enh_start;
664 enh_start_addr = (conf->user.enh_start << 9);
670 tot_enh_size_mult += enh_size_mult;
672 for (pidx = 0; pidx < 4; pidx++) {
673 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
674 printf("GP%i partition not HC WP group size "
675 "aligned\n", pidx+1);
678 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
679 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
680 part_attrs |= EXT_CSD_ENH_GP(pidx);
681 tot_enh_size_mult += gp_size_mult[pidx];
685 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
686 printf("Card does not support enhanced attribute\n");
690 err = mmc_send_ext_csd(mmc, ext_csd);
695 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
696 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
697 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
698 if (tot_enh_size_mult > max_enh_size_mult) {
699 printf("Total enhanced size exceeds maximum (%u > %u)\n",
700 tot_enh_size_mult, max_enh_size_mult);
704 /* The default value of EXT_CSD_WR_REL_SET is device
705 * dependent, the values can only be changed if the
706 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
707 * changed only once and before partitioning is completed. */
708 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
709 if (conf->user.wr_rel_change) {
710 if (conf->user.wr_rel_set)
711 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
713 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
715 for (pidx = 0; pidx < 4; pidx++) {
716 if (conf->gp_part[pidx].wr_rel_change) {
717 if (conf->gp_part[pidx].wr_rel_set)
718 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
720 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
724 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
725 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
726 puts("Card does not support host controlled partition write "
727 "reliability settings\n");
731 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
732 EXT_CSD_PARTITION_SETTING_COMPLETED) {
733 printf("Card already partitioned\n");
737 if (mode == MMC_HWPART_CONF_CHECK)
740 /* Partitioning requires high-capacity size definitions */
741 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
742 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
743 EXT_CSD_ERASE_GROUP_DEF, 1);
748 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
750 /* update erase group size to be high-capacity */
751 mmc->erase_grp_size =
752 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
756 /* all OK, write the configuration */
757 for (i = 0; i < 4; i++) {
758 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
759 EXT_CSD_ENH_START_ADDR+i,
760 (enh_start_addr >> (i*8)) & 0xFF);
764 for (i = 0; i < 3; i++) {
765 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
766 EXT_CSD_ENH_SIZE_MULT+i,
767 (enh_size_mult >> (i*8)) & 0xFF);
771 for (pidx = 0; pidx < 4; pidx++) {
772 for (i = 0; i < 3; i++) {
773 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
774 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
775 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
780 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
781 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
785 if (mode == MMC_HWPART_CONF_SET)
788 /* The WR_REL_SET is a write-once register but shall be
789 * written before setting PART_SETTING_COMPLETED. As it is
790 * write-once we can only write it when completing the
792 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
793 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
794 EXT_CSD_WR_REL_SET, wr_rel_set);
799 /* Setting PART_SETTING_COMPLETED confirms the partition
800 * configuration but it only becomes effective after power
801 * cycle, so we do not adjust the partition related settings
802 * in the mmc struct. */
804 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
805 EXT_CSD_PARTITION_SETTING,
806 EXT_CSD_PARTITION_SETTING_COMPLETED);
813 int mmc_getcd(struct mmc *mmc)
817 cd = board_mmc_getcd(mmc);
820 if (mmc->cfg->ops->getcd)
821 cd = mmc->cfg->ops->getcd(mmc);
829 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
832 struct mmc_data data;
834 /* Switch the frequency */
835 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
836 cmd.resp_type = MMC_RSP_R1;
837 cmd.cmdarg = (mode << 31) | 0xffffff;
838 cmd.cmdarg &= ~(0xf << (group * 4));
839 cmd.cmdarg |= value << (group * 4);
841 data.dest = (char *)resp;
844 data.flags = MMC_DATA_READ;
846 return mmc_send_cmd(mmc, &cmd, &data);
850 static int sd_change_freq(struct mmc *mmc)
854 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
855 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
856 struct mmc_data data;
861 if (mmc_host_is_spi(mmc))
864 /* Read the SCR to find out if this card supports higher speeds */
865 cmd.cmdidx = MMC_CMD_APP_CMD;
866 cmd.resp_type = MMC_RSP_R1;
867 cmd.cmdarg = mmc->rca << 16;
869 err = mmc_send_cmd(mmc, &cmd, NULL);
874 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
875 cmd.resp_type = MMC_RSP_R1;
881 data.dest = (char *)scr;
884 data.flags = MMC_DATA_READ;
886 err = mmc_send_cmd(mmc, &cmd, &data);
895 mmc->scr[0] = __be32_to_cpu(scr[0]);
896 mmc->scr[1] = __be32_to_cpu(scr[1]);
898 switch ((mmc->scr[0] >> 24) & 0xf) {
900 mmc->version = SD_VERSION_1_0;
903 mmc->version = SD_VERSION_1_10;
906 mmc->version = SD_VERSION_2;
907 if ((mmc->scr[0] >> 15) & 0x1)
908 mmc->version = SD_VERSION_3;
911 mmc->version = SD_VERSION_1_0;
915 if (mmc->scr[0] & SD_DATA_4BIT)
916 mmc->card_caps |= MMC_MODE_4BIT;
918 /* Version 1.0 doesn't support switching */
919 if (mmc->version == SD_VERSION_1_0)
924 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
925 (u8 *)switch_status);
930 /* The high-speed function is busy. Try again */
931 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
935 /* If high-speed isn't supported, we return */
936 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
940 * If the host doesn't support SD_HIGHSPEED, do not switch card to
941 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
942 * This can avoid furthur problem when the card runs in different
943 * mode between the host.
945 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
946 (mmc->cfg->host_caps & MMC_MODE_HS)))
949 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
954 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
955 mmc->card_caps |= MMC_MODE_HS;
960 /* frequency bases */
961 /* divided by 10 to be nice to platforms without floating point */
962 static const int fbase[] = {
969 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
970 * to platforms without floating point.
972 static const int multipliers[] = {
991 static void mmc_set_ios(struct mmc *mmc)
993 if (mmc->cfg->ops->set_ios)
994 mmc->cfg->ops->set_ios(mmc);
997 void mmc_set_clock(struct mmc *mmc, uint clock)
999 if (clock > mmc->cfg->f_max)
1000 clock = mmc->cfg->f_max;
1002 if (clock < mmc->cfg->f_min)
1003 clock = mmc->cfg->f_min;
1010 static void mmc_set_bus_width(struct mmc *mmc, uint width)
1012 mmc->bus_width = width;
1017 static int mmc_startup(struct mmc *mmc)
1021 u64 cmult, csize, capacity;
1023 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1024 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1026 bool has_parts = false;
1027 bool part_completed;
1029 #ifdef CONFIG_MMC_SPI_CRC_ON
1030 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1031 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1032 cmd.resp_type = MMC_RSP_R1;
1034 err = mmc_send_cmd(mmc, &cmd, NULL);
1041 /* Put the Card in Identify Mode */
1042 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1043 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1044 cmd.resp_type = MMC_RSP_R2;
1047 err = mmc_send_cmd(mmc, &cmd, NULL);
1052 memcpy(mmc->cid, cmd.response, 16);
1055 * For MMC cards, set the Relative Address.
1056 * For SD cards, get the Relatvie Address.
1057 * This also puts the cards into Standby State
1059 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1060 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1061 cmd.cmdarg = mmc->rca << 16;
1062 cmd.resp_type = MMC_RSP_R6;
1064 err = mmc_send_cmd(mmc, &cmd, NULL);
1070 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1073 /* Get the Card-Specific Data */
1074 cmd.cmdidx = MMC_CMD_SEND_CSD;
1075 cmd.resp_type = MMC_RSP_R2;
1076 cmd.cmdarg = mmc->rca << 16;
1078 err = mmc_send_cmd(mmc, &cmd, NULL);
1080 /* Waiting for the ready status */
1081 mmc_send_status(mmc, timeout);
1086 mmc->csd[0] = cmd.response[0];
1087 mmc->csd[1] = cmd.response[1];
1088 mmc->csd[2] = cmd.response[2];
1089 mmc->csd[3] = cmd.response[3];
1091 if (mmc->version == MMC_VERSION_UNKNOWN) {
1092 int version = (cmd.response[0] >> 26) & 0xf;
1096 mmc->version = MMC_VERSION_1_2;
1099 mmc->version = MMC_VERSION_1_4;
1102 mmc->version = MMC_VERSION_2_2;
1105 mmc->version = MMC_VERSION_3;
1108 mmc->version = MMC_VERSION_4;
1111 mmc->version = MMC_VERSION_1_2;
1116 /* divide frequency by 10, since the mults are 10x bigger */
1117 freq = fbase[(cmd.response[0] & 0x7)];
1118 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1120 mmc->tran_speed = freq * mult;
1122 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1123 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1126 mmc->write_bl_len = mmc->read_bl_len;
1128 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1130 if (mmc->high_capacity) {
1131 csize = (mmc->csd[1] & 0x3f) << 16
1132 | (mmc->csd[2] & 0xffff0000) >> 16;
1135 csize = (mmc->csd[1] & 0x3ff) << 2
1136 | (mmc->csd[2] & 0xc0000000) >> 30;
1137 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1140 mmc->capacity_user = (csize + 1) << (cmult + 2);
1141 mmc->capacity_user *= mmc->read_bl_len;
1142 mmc->capacity_boot = 0;
1143 mmc->capacity_rpmb = 0;
1144 for (i = 0; i < 4; i++)
1145 mmc->capacity_gp[i] = 0;
1147 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1148 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1150 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1151 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1153 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1154 cmd.cmdidx = MMC_CMD_SET_DSR;
1155 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1156 cmd.resp_type = MMC_RSP_NONE;
1157 if (mmc_send_cmd(mmc, &cmd, NULL))
1158 printf("MMC: SET_DSR failed\n");
1161 /* Select the card, and put it into Transfer Mode */
1162 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1163 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1164 cmd.resp_type = MMC_RSP_R1;
1165 cmd.cmdarg = mmc->rca << 16;
1166 err = mmc_send_cmd(mmc, &cmd, NULL);
1173 * For SD, its erase group is always one sector
1175 mmc->erase_grp_size = 1;
1176 mmc->part_config = MMCPART_NOAVAILABLE;
1177 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1178 /* check ext_csd version and capacity */
1179 err = mmc_send_ext_csd(mmc, ext_csd);
1182 if (ext_csd[EXT_CSD_REV] >= 2) {
1184 * According to the JEDEC Standard, the value of
1185 * ext_csd's capacity is valid if the value is more
1188 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1189 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1190 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1191 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1192 capacity *= MMC_MAX_BLOCK_LEN;
1193 if ((capacity >> 20) > 2 * 1024)
1194 mmc->capacity_user = capacity;
1197 switch (ext_csd[EXT_CSD_REV]) {
1199 mmc->version = MMC_VERSION_4_1;
1202 mmc->version = MMC_VERSION_4_2;
1205 mmc->version = MMC_VERSION_4_3;
1208 mmc->version = MMC_VERSION_4_41;
1211 mmc->version = MMC_VERSION_4_5;
1214 mmc->version = MMC_VERSION_5_0;
1218 /* The partition data may be non-zero but it is only
1219 * effective if PARTITION_SETTING_COMPLETED is set in
1220 * EXT_CSD, so ignore any data if this bit is not set,
1221 * except for enabling the high-capacity group size
1222 * definition (see below). */
1223 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1224 EXT_CSD_PARTITION_SETTING_COMPLETED);
1226 /* store the partition info of emmc */
1227 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1228 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1229 ext_csd[EXT_CSD_BOOT_MULT])
1230 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1231 if (part_completed &&
1232 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1233 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1235 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1237 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1239 for (i = 0; i < 4; i++) {
1240 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1241 uint mult = (ext_csd[idx + 2] << 16) +
1242 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1245 if (!part_completed)
1247 mmc->capacity_gp[i] = mult;
1248 mmc->capacity_gp[i] *=
1249 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1250 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1251 mmc->capacity_gp[i] <<= 19;
1254 if (part_completed) {
1255 mmc->enh_user_size =
1256 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1257 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1258 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1259 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1260 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1261 mmc->enh_user_size <<= 19;
1262 mmc->enh_user_start =
1263 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1264 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1265 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1266 ext_csd[EXT_CSD_ENH_START_ADDR];
1267 if (mmc->high_capacity)
1268 mmc->enh_user_start <<= 9;
1272 * Host needs to enable ERASE_GRP_DEF bit if device is
1273 * partitioned. This bit will be lost every time after a reset
1274 * or power off. This will affect erase size.
1278 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1279 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1282 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1283 EXT_CSD_ERASE_GROUP_DEF, 1);
1288 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1291 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1292 /* Read out group size from ext_csd */
1293 mmc->erase_grp_size =
1294 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1296 * if high capacity and partition setting completed
1297 * SEC_COUNT is valid even if it is smaller than 2 GiB
1298 * JEDEC Standard JESD84-B45, 6.2.4
1300 if (mmc->high_capacity && part_completed) {
1301 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1302 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1303 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1304 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1305 capacity *= MMC_MAX_BLOCK_LEN;
1306 mmc->capacity_user = capacity;
1309 /* Calculate the group size from the csd value. */
1310 int erase_gsz, erase_gmul;
1311 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1312 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1313 mmc->erase_grp_size = (erase_gsz + 1)
1317 mmc->hc_wp_grp_size = 1024
1318 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1319 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1321 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1324 err = mmc_set_capacity(mmc, mmc->part_num);
1329 err = sd_change_freq(mmc);
1331 err = mmc_change_freq(mmc);
1336 /* Restrict card's capabilities by what the host can do */
1337 mmc->card_caps &= mmc->cfg->host_caps;
1340 if (mmc->card_caps & MMC_MODE_4BIT) {
1341 cmd.cmdidx = MMC_CMD_APP_CMD;
1342 cmd.resp_type = MMC_RSP_R1;
1343 cmd.cmdarg = mmc->rca << 16;
1345 err = mmc_send_cmd(mmc, &cmd, NULL);
1349 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1350 cmd.resp_type = MMC_RSP_R1;
1352 err = mmc_send_cmd(mmc, &cmd, NULL);
1356 mmc_set_bus_width(mmc, 4);
1359 if (mmc->card_caps & MMC_MODE_HS)
1360 mmc->tran_speed = 50000000;
1362 mmc->tran_speed = 25000000;
1363 } else if (mmc->version >= MMC_VERSION_4) {
1364 /* Only version 4 of MMC supports wider bus widths */
1367 /* An array of possible bus widths in order of preference */
1368 static unsigned ext_csd_bits[] = {
1369 EXT_CSD_DDR_BUS_WIDTH_8,
1370 EXT_CSD_DDR_BUS_WIDTH_4,
1371 EXT_CSD_BUS_WIDTH_8,
1372 EXT_CSD_BUS_WIDTH_4,
1373 EXT_CSD_BUS_WIDTH_1,
1376 /* An array to map CSD bus widths to host cap bits */
1377 static unsigned ext_to_hostcaps[] = {
1378 [EXT_CSD_DDR_BUS_WIDTH_4] =
1379 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1380 [EXT_CSD_DDR_BUS_WIDTH_8] =
1381 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1382 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1383 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1386 /* An array to map chosen bus width to an integer */
1387 static unsigned widths[] = {
1391 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1392 unsigned int extw = ext_csd_bits[idx];
1393 unsigned int caps = ext_to_hostcaps[extw];
1396 * If the bus width is still not changed,
1397 * don't try to set the default again.
1398 * Otherwise, recover from switch attempts
1399 * by switching to 1-bit bus width.
1401 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1402 mmc->bus_width == 1) {
1408 * Check to make sure the card and controller support
1409 * these capabilities
1411 if ((mmc->card_caps & caps) != caps)
1414 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1415 EXT_CSD_BUS_WIDTH, extw);
1420 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1421 mmc_set_bus_width(mmc, widths[idx]);
1423 err = mmc_send_ext_csd(mmc, test_csd);
1428 /* Only compare read only fields */
1429 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1430 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1431 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1432 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1433 ext_csd[EXT_CSD_REV]
1434 == test_csd[EXT_CSD_REV] &&
1435 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1436 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1437 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1438 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1447 if (mmc->card_caps & MMC_MODE_HS) {
1448 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1449 mmc->tran_speed = 52000000;
1451 mmc->tran_speed = 26000000;
1455 mmc_set_clock(mmc, mmc->tran_speed);
1457 /* Fix the block length for DDR mode */
1458 if (mmc->ddr_mode) {
1459 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1460 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1463 /* fill in device description */
1464 mmc->block_dev.lun = 0;
1465 mmc->block_dev.type = 0;
1466 mmc->block_dev.blksz = mmc->read_bl_len;
1467 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
1468 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
1469 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1470 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1471 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1472 (mmc->cid[3] >> 16) & 0xffff);
1473 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1474 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1475 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1476 (mmc->cid[2] >> 24) & 0xff);
1477 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1478 (mmc->cid[2] >> 16) & 0xf);
1480 mmc->block_dev.vendor[0] = 0;
1481 mmc->block_dev.product[0] = 0;
1482 mmc->block_dev.revision[0] = 0;
1484 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1485 init_part(&mmc->block_dev);
1491 static int mmc_send_if_cond(struct mmc *mmc)
1496 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1497 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1498 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1499 cmd.resp_type = MMC_RSP_R7;
1501 err = mmc_send_cmd(mmc, &cmd, NULL);
1506 if ((cmd.response[0] & 0xff) != 0xaa)
1507 return UNUSABLE_ERR;
1509 mmc->version = SD_VERSION_2;
1514 /* not used any more */
1515 int __deprecated mmc_register(struct mmc *mmc)
1517 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1518 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1523 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
1527 /* quick validation */
1528 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1529 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1532 mmc = calloc(1, sizeof(*mmc));
1539 /* the following chunk was mmc_register() */
1541 /* Setup dsr related values */
1543 mmc->dsr = 0xffffffff;
1544 /* Setup the universal parts of the block interface just once */
1545 mmc->block_dev.if_type = IF_TYPE_MMC;
1546 mmc->block_dev.dev = cur_dev_num++;
1547 mmc->block_dev.removable = 1;
1548 mmc->block_dev.block_read = mmc_bread;
1549 mmc->block_dev.block_write = mmc_bwrite;
1550 mmc->block_dev.block_erase = mmc_berase;
1552 /* setup initial part type */
1553 mmc->block_dev.part_type = mmc->cfg->part_type;
1555 INIT_LIST_HEAD(&mmc->link);
1557 list_add_tail(&mmc->link, &mmc_devices);
1562 void mmc_destroy(struct mmc *mmc)
1564 /* only freeing memory for now */
1568 #ifdef CONFIG_PARTITIONS
1569 block_dev_desc_t *mmc_get_dev(int dev)
1571 struct mmc *mmc = find_mmc_device(dev);
1572 if (!mmc || mmc_init(mmc))
1575 return &mmc->block_dev;
1579 /* board-specific MMC power initializations. */
1580 __weak void board_mmc_power_init(void)
1584 int mmc_start_init(struct mmc *mmc)
1588 /* we pretend there's no card when init is NULL */
1589 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
1591 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1592 printf("MMC: no card present\n");
1600 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1601 mmc_adapter_card_type_ident();
1603 board_mmc_power_init();
1605 /* made sure it's not NULL earlier */
1606 err = mmc->cfg->ops->init(mmc);
1612 mmc_set_bus_width(mmc, 1);
1613 mmc_set_clock(mmc, 1);
1615 /* Reset the Card */
1616 err = mmc_go_idle(mmc);
1621 /* The internal partition reset to user partition(0) at every CMD0*/
1624 /* Test for SD version 2 */
1625 err = mmc_send_if_cond(mmc);
1627 /* Now try to get the SD card's operating condition */
1628 err = sd_send_op_cond(mmc);
1630 /* If the command timed out, we check for an MMC card */
1631 if (err == TIMEOUT) {
1632 err = mmc_send_op_cond(mmc);
1635 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1636 printf("Card did not respond to voltage select!\n");
1638 return UNUSABLE_ERR;
1643 mmc->init_in_progress = 1;
1648 static int mmc_complete_init(struct mmc *mmc)
1652 mmc->init_in_progress = 0;
1653 if (mmc->op_cond_pending)
1654 err = mmc_complete_op_cond(mmc);
1657 err = mmc_startup(mmc);
1665 int mmc_init(struct mmc *mmc)
1673 start = get_timer(0);
1675 if (!mmc->init_in_progress)
1676 err = mmc_start_init(mmc);
1679 err = mmc_complete_init(mmc);
1680 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
1684 int mmc_set_dsr(struct mmc *mmc, u16 val)
1690 /* CPU-specific MMC initializations */
1691 __weak int cpu_mmc_init(bd_t *bis)
1696 /* board-specific MMC initializations. */
1697 __weak int board_mmc_init(bd_t *bis)
1702 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1704 void print_mmc_devices(char separator)
1707 struct list_head *entry;
1710 list_for_each(entry, &mmc_devices) {
1711 m = list_entry(entry, struct mmc, link);
1714 mmc_type = IS_SD(m) ? "SD" : "eMMC";
1718 printf("%s: %d", m->cfg->name, m->block_dev.dev);
1720 printf(" (%s)", mmc_type);
1722 if (entry->next != &mmc_devices) {
1723 printf("%c", separator);
1724 if (separator != '\n')
1733 void print_mmc_devices(char separator) { }
1736 int get_mmc_num(void)
1741 void mmc_set_preinit(struct mmc *mmc, int preinit)
1743 mmc->preinit = preinit;
1746 static void do_preinit(void)
1749 struct list_head *entry;
1751 list_for_each(entry, &mmc_devices) {
1752 m = list_entry(entry, struct mmc, link);
1754 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1755 mmc_set_preinit(m, 1);
1763 int mmc_initialize(bd_t *bis)
1765 static int initialized = 0;
1766 if (initialized) /* Avoid initializing mmc multiple times */
1770 INIT_LIST_HEAD (&mmc_devices);
1773 #ifndef CONFIG_DM_MMC
1774 if (board_mmc_init(bis) < 0)
1778 #ifndef CONFIG_SPL_BUILD
1779 print_mmc_devices(',');
1786 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1788 * This function changes the size of boot partition and the size of rpmb
1789 * partition present on EMMC devices.
1792 * struct *mmc: pointer for the mmc device strcuture
1793 * bootsize: size of boot partition
1794 * rpmbsize: size of rpmb partition
1796 * Returns 0 on success.
1799 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1800 unsigned long rpmbsize)
1805 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1806 cmd.cmdidx = MMC_CMD_RES_MAN;
1807 cmd.resp_type = MMC_RSP_R1b;
1808 cmd.cmdarg = MMC_CMD62_ARG1;
1810 err = mmc_send_cmd(mmc, &cmd, NULL);
1812 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1816 /* Boot partition changing mode */
1817 cmd.cmdidx = MMC_CMD_RES_MAN;
1818 cmd.resp_type = MMC_RSP_R1b;
1819 cmd.cmdarg = MMC_CMD62_ARG2;
1821 err = mmc_send_cmd(mmc, &cmd, NULL);
1823 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1826 /* boot partition size is multiple of 128KB */
1827 bootsize = (bootsize * 1024) / 128;
1829 /* Arg: boot partition size */
1830 cmd.cmdidx = MMC_CMD_RES_MAN;
1831 cmd.resp_type = MMC_RSP_R1b;
1832 cmd.cmdarg = bootsize;
1834 err = mmc_send_cmd(mmc, &cmd, NULL);
1836 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1839 /* RPMB partition size is multiple of 128KB */
1840 rpmbsize = (rpmbsize * 1024) / 128;
1841 /* Arg: RPMB partition size */
1842 cmd.cmdidx = MMC_CMD_RES_MAN;
1843 cmd.resp_type = MMC_RSP_R1b;
1844 cmd.cmdarg = rpmbsize;
1846 err = mmc_send_cmd(mmc, &cmd, NULL);
1848 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1855 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1856 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1859 * Returns 0 on success.
1861 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1865 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1866 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1867 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1868 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1876 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1877 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1880 * Returns 0 on success.
1882 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1886 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1887 EXT_CSD_BOOT_ACK(ack) |
1888 EXT_CSD_BOOT_PART_NUM(part_num) |
1889 EXT_CSD_PARTITION_ACCESS(access));
1897 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1898 * for enable. Note that this is a write-once field for non-zero values.
1900 * Returns 0 on success.
1902 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1904 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,