2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
20 #include <linux/list.h>
22 #include "mmc_private.h"
24 __weak int board_mmc_getwp(struct mmc *mmc)
29 int mmc_getwp(struct mmc *mmc)
33 wp = board_mmc_getwp(mmc);
36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
45 __weak int board_mmc_getcd(struct mmc *mmc)
50 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
54 #ifdef CONFIG_MMC_TRACE
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
62 printf("\t\tRET\t\t\t %d\n", ret);
64 switch (cmd->resp_type) {
66 printf("\t\tMMC_RSP_NONE\n");
69 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
73 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
77 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
79 printf("\t\t \t\t 0x%08X \n",
81 printf("\t\t \t\t 0x%08X \n",
83 printf("\t\t \t\t 0x%08X \n",
86 printf("\t\t\t\t\tDUMPING DATA\n");
87 for (i = 0; i < 4; i++) {
89 printf("\t\t\t\t\t%03d - ", i*4);
90 ptr = (u8 *)&cmd->response[i];
92 for (j = 0; j < 4; j++)
93 printf("%02X ", *ptr--);
98 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
102 printf("\t\tERROR MMC rsp not supported\n");
107 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
112 int mmc_send_status(struct mmc *mmc, int timeout)
115 int err, retries = 5;
116 #ifdef CONFIG_MMC_TRACE
120 cmd.cmdidx = MMC_CMD_SEND_STATUS;
121 cmd.resp_type = MMC_RSP_R1;
122 if (!mmc_host_is_spi(mmc))
123 cmd.cmdarg = mmc->rca << 16;
126 err = mmc_send_cmd(mmc, &cmd, NULL);
128 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
129 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
132 else if (cmd.response[0] & MMC_STATUS_MASK) {
133 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
134 printf("Status Error: 0x%08X\n",
139 } else if (--retries < 0)
148 #ifdef CONFIG_MMC_TRACE
149 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
150 printf("CURR STATE:%d\n", status);
153 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
154 printf("Timeout waiting card ready\n");
162 int mmc_set_blocklen(struct mmc *mmc, int len)
169 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
170 cmd.resp_type = MMC_RSP_R1;
173 return mmc_send_cmd(mmc, &cmd, NULL);
176 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
180 struct mmc_data data;
183 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
185 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
187 if (mmc->high_capacity)
190 cmd.cmdarg = start * mmc->read_bl_len;
192 cmd.resp_type = MMC_RSP_R1;
195 data.blocks = blkcnt;
196 data.blocksize = mmc->read_bl_len;
197 data.flags = MMC_DATA_READ;
199 if (mmc_send_cmd(mmc, &cmd, &data))
203 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
205 cmd.resp_type = MMC_RSP_R1b;
206 if (mmc_send_cmd(mmc, &cmd, NULL)) {
207 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
208 printf("mmc fail to send stop cmd\n");
218 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
220 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
225 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
227 int dev_num = block_dev->devnum;
229 lbaint_t cur, blocks_todo = blkcnt;
234 struct mmc *mmc = find_mmc_device(dev_num);
238 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
242 if ((start + blkcnt) > block_dev->lba) {
243 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
244 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
245 start + blkcnt, block_dev->lba);
250 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
251 debug("%s: Failed to set blocklen\n", __func__);
256 cur = (blocks_todo > mmc->cfg->b_max) ?
257 mmc->cfg->b_max : blocks_todo;
258 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
259 debug("%s: Failed to read blocks\n", __func__);
264 dst += cur * mmc->read_bl_len;
265 } while (blocks_todo > 0);
270 static int mmc_go_idle(struct mmc *mmc)
277 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
279 cmd.resp_type = MMC_RSP_NONE;
281 err = mmc_send_cmd(mmc, &cmd, NULL);
291 static int sd_send_op_cond(struct mmc *mmc)
298 cmd.cmdidx = MMC_CMD_APP_CMD;
299 cmd.resp_type = MMC_RSP_R1;
302 err = mmc_send_cmd(mmc, &cmd, NULL);
307 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
308 cmd.resp_type = MMC_RSP_R3;
311 * Most cards do not answer if some reserved bits
312 * in the ocr are set. However, Some controller
313 * can set bit 7 (reserved for low voltages), but
314 * how to manage low voltages SD card is not yet
317 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
318 (mmc->cfg->voltages & 0xff8000);
320 if (mmc->version == SD_VERSION_2)
321 cmd.cmdarg |= OCR_HCS;
323 err = mmc_send_cmd(mmc, &cmd, NULL);
328 if (cmd.response[0] & OCR_BUSY)
337 if (mmc->version != SD_VERSION_2)
338 mmc->version = SD_VERSION_1_0;
340 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
341 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
342 cmd.resp_type = MMC_RSP_R3;
345 err = mmc_send_cmd(mmc, &cmd, NULL);
351 mmc->ocr = cmd.response[0];
353 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
359 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
364 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
365 cmd.resp_type = MMC_RSP_R3;
367 if (use_arg && !mmc_host_is_spi(mmc))
368 cmd.cmdarg = OCR_HCS |
369 (mmc->cfg->voltages &
370 (mmc->ocr & OCR_VOLTAGE_MASK)) |
371 (mmc->ocr & OCR_ACCESS_MODE);
373 err = mmc_send_cmd(mmc, &cmd, NULL);
376 mmc->ocr = cmd.response[0];
380 static int mmc_send_op_cond(struct mmc *mmc)
384 /* Some cards seem to need this */
387 /* Asking to the card its capabilities */
388 for (i = 0; i < 2; i++) {
389 err = mmc_send_op_cond_iter(mmc, i != 0);
393 /* exit if not busy (flag seems to be inverted) */
394 if (mmc->ocr & OCR_BUSY)
397 mmc->op_cond_pending = 1;
401 static int mmc_complete_op_cond(struct mmc *mmc)
408 mmc->op_cond_pending = 0;
409 if (!(mmc->ocr & OCR_BUSY)) {
410 start = get_timer(0);
412 err = mmc_send_op_cond_iter(mmc, 1);
415 if (mmc->ocr & OCR_BUSY)
417 if (get_timer(start) > timeout)
423 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
424 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
425 cmd.resp_type = MMC_RSP_R3;
428 err = mmc_send_cmd(mmc, &cmd, NULL);
433 mmc->ocr = cmd.response[0];
436 mmc->version = MMC_VERSION_UNKNOWN;
438 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
445 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
448 struct mmc_data data;
451 /* Get the Card Status Register */
452 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
453 cmd.resp_type = MMC_RSP_R1;
456 data.dest = (char *)ext_csd;
458 data.blocksize = MMC_MAX_BLOCK_LEN;
459 data.flags = MMC_DATA_READ;
461 err = mmc_send_cmd(mmc, &cmd, &data);
466 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
472 cmd.cmdidx = MMC_CMD_SWITCH;
473 cmd.resp_type = MMC_RSP_R1b;
474 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
478 ret = mmc_send_cmd(mmc, &cmd, NULL);
480 /* Waiting for the ready status */
482 ret = mmc_send_status(mmc, timeout);
488 static int mmc_change_freq(struct mmc *mmc)
490 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
496 if (mmc_host_is_spi(mmc))
499 /* Only version 4 supports high-speed */
500 if (mmc->version < MMC_VERSION_4)
503 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
505 err = mmc_send_ext_csd(mmc, ext_csd);
510 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
512 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
517 /* Now check to see that it worked */
518 err = mmc_send_ext_csd(mmc, ext_csd);
523 /* No high-speed support */
524 if (!ext_csd[EXT_CSD_HS_TIMING])
527 /* High Speed is set, there are two types: 52MHz and 26MHz */
528 if (cardtype & EXT_CSD_CARD_TYPE_52) {
529 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
530 mmc->card_caps |= MMC_MODE_DDR_52MHz;
531 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
533 mmc->card_caps |= MMC_MODE_HS;
539 static int mmc_set_capacity(struct mmc *mmc, int part_num)
543 mmc->capacity = mmc->capacity_user;
547 mmc->capacity = mmc->capacity_boot;
550 mmc->capacity = mmc->capacity_rpmb;
556 mmc->capacity = mmc->capacity_gp[part_num - 4];
562 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
567 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
571 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
572 (mmc->part_config & ~PART_ACCESS_MASK)
573 | (part_num & PART_ACCESS_MASK));
576 * Set the capacity if the switch succeeded or was intended
577 * to return to representing the raw device.
579 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
580 ret = mmc_set_capacity(mmc, part_num);
581 mmc_get_blk_desc(mmc)->hwpart = part_num;
587 int mmc_hwpart_config(struct mmc *mmc,
588 const struct mmc_hwpart_conf *conf,
589 enum mmc_hwpart_conf_mode mode)
595 u32 max_enh_size_mult;
596 u32 tot_enh_size_mult = 0;
599 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
601 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
604 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
605 printf("eMMC >= 4.4 required for enhanced user data area\n");
609 if (!(mmc->part_support & PART_SUPPORT)) {
610 printf("Card does not support partitioning\n");
614 if (!mmc->hc_wp_grp_size) {
615 printf("Card does not define HC WP group size\n");
619 /* check partition alignment and total enhanced size */
620 if (conf->user.enh_size) {
621 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
622 conf->user.enh_start % mmc->hc_wp_grp_size) {
623 printf("User data enhanced area not HC WP group "
627 part_attrs |= EXT_CSD_ENH_USR;
628 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
629 if (mmc->high_capacity) {
630 enh_start_addr = conf->user.enh_start;
632 enh_start_addr = (conf->user.enh_start << 9);
638 tot_enh_size_mult += enh_size_mult;
640 for (pidx = 0; pidx < 4; pidx++) {
641 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
642 printf("GP%i partition not HC WP group size "
643 "aligned\n", pidx+1);
646 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
647 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
648 part_attrs |= EXT_CSD_ENH_GP(pidx);
649 tot_enh_size_mult += gp_size_mult[pidx];
653 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
654 printf("Card does not support enhanced attribute\n");
658 err = mmc_send_ext_csd(mmc, ext_csd);
663 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
664 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
665 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
666 if (tot_enh_size_mult > max_enh_size_mult) {
667 printf("Total enhanced size exceeds maximum (%u > %u)\n",
668 tot_enh_size_mult, max_enh_size_mult);
672 /* The default value of EXT_CSD_WR_REL_SET is device
673 * dependent, the values can only be changed if the
674 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
675 * changed only once and before partitioning is completed. */
676 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
677 if (conf->user.wr_rel_change) {
678 if (conf->user.wr_rel_set)
679 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
681 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
683 for (pidx = 0; pidx < 4; pidx++) {
684 if (conf->gp_part[pidx].wr_rel_change) {
685 if (conf->gp_part[pidx].wr_rel_set)
686 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
688 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
692 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
693 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
694 puts("Card does not support host controlled partition write "
695 "reliability settings\n");
699 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
700 EXT_CSD_PARTITION_SETTING_COMPLETED) {
701 printf("Card already partitioned\n");
705 if (mode == MMC_HWPART_CONF_CHECK)
708 /* Partitioning requires high-capacity size definitions */
709 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
710 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
711 EXT_CSD_ERASE_GROUP_DEF, 1);
716 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
718 /* update erase group size to be high-capacity */
719 mmc->erase_grp_size =
720 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
724 /* all OK, write the configuration */
725 for (i = 0; i < 4; i++) {
726 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
727 EXT_CSD_ENH_START_ADDR+i,
728 (enh_start_addr >> (i*8)) & 0xFF);
732 for (i = 0; i < 3; i++) {
733 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
734 EXT_CSD_ENH_SIZE_MULT+i,
735 (enh_size_mult >> (i*8)) & 0xFF);
739 for (pidx = 0; pidx < 4; pidx++) {
740 for (i = 0; i < 3; i++) {
741 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
742 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
743 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
748 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
749 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
753 if (mode == MMC_HWPART_CONF_SET)
756 /* The WR_REL_SET is a write-once register but shall be
757 * written before setting PART_SETTING_COMPLETED. As it is
758 * write-once we can only write it when completing the
760 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
761 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
762 EXT_CSD_WR_REL_SET, wr_rel_set);
767 /* Setting PART_SETTING_COMPLETED confirms the partition
768 * configuration but it only becomes effective after power
769 * cycle, so we do not adjust the partition related settings
770 * in the mmc struct. */
772 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
773 EXT_CSD_PARTITION_SETTING,
774 EXT_CSD_PARTITION_SETTING_COMPLETED);
781 int mmc_getcd(struct mmc *mmc)
785 cd = board_mmc_getcd(mmc);
788 if (mmc->cfg->ops->getcd)
789 cd = mmc->cfg->ops->getcd(mmc);
797 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
800 struct mmc_data data;
802 /* Switch the frequency */
803 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
804 cmd.resp_type = MMC_RSP_R1;
805 cmd.cmdarg = (mode << 31) | 0xffffff;
806 cmd.cmdarg &= ~(0xf << (group * 4));
807 cmd.cmdarg |= value << (group * 4);
809 data.dest = (char *)resp;
812 data.flags = MMC_DATA_READ;
814 return mmc_send_cmd(mmc, &cmd, &data);
818 static int sd_change_freq(struct mmc *mmc)
822 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
823 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
824 struct mmc_data data;
829 if (mmc_host_is_spi(mmc))
832 /* Read the SCR to find out if this card supports higher speeds */
833 cmd.cmdidx = MMC_CMD_APP_CMD;
834 cmd.resp_type = MMC_RSP_R1;
835 cmd.cmdarg = mmc->rca << 16;
837 err = mmc_send_cmd(mmc, &cmd, NULL);
842 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
843 cmd.resp_type = MMC_RSP_R1;
849 data.dest = (char *)scr;
852 data.flags = MMC_DATA_READ;
854 err = mmc_send_cmd(mmc, &cmd, &data);
863 mmc->scr[0] = __be32_to_cpu(scr[0]);
864 mmc->scr[1] = __be32_to_cpu(scr[1]);
866 switch ((mmc->scr[0] >> 24) & 0xf) {
868 mmc->version = SD_VERSION_1_0;
871 mmc->version = SD_VERSION_1_10;
874 mmc->version = SD_VERSION_2;
875 if ((mmc->scr[0] >> 15) & 0x1)
876 mmc->version = SD_VERSION_3;
879 mmc->version = SD_VERSION_1_0;
883 if (mmc->scr[0] & SD_DATA_4BIT)
884 mmc->card_caps |= MMC_MODE_4BIT;
886 /* Version 1.0 doesn't support switching */
887 if (mmc->version == SD_VERSION_1_0)
892 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
893 (u8 *)switch_status);
898 /* The high-speed function is busy. Try again */
899 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
903 /* If high-speed isn't supported, we return */
904 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
908 * If the host doesn't support SD_HIGHSPEED, do not switch card to
909 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
910 * This can avoid furthur problem when the card runs in different
911 * mode between the host.
913 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
914 (mmc->cfg->host_caps & MMC_MODE_HS)))
917 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
922 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
923 mmc->card_caps |= MMC_MODE_HS;
928 /* frequency bases */
929 /* divided by 10 to be nice to platforms without floating point */
930 static const int fbase[] = {
937 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
938 * to platforms without floating point.
940 static const u8 multipliers[] = {
959 static void mmc_set_ios(struct mmc *mmc)
961 if (mmc->cfg->ops->set_ios)
962 mmc->cfg->ops->set_ios(mmc);
965 void mmc_set_clock(struct mmc *mmc, uint clock)
967 if (clock > mmc->cfg->f_max)
968 clock = mmc->cfg->f_max;
970 if (clock < mmc->cfg->f_min)
971 clock = mmc->cfg->f_min;
978 static void mmc_set_bus_width(struct mmc *mmc, uint width)
980 mmc->bus_width = width;
985 static int mmc_startup(struct mmc *mmc)
989 u64 cmult, csize, capacity;
991 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
992 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
994 bool has_parts = false;
996 struct blk_desc *bdesc;
998 #ifdef CONFIG_MMC_SPI_CRC_ON
999 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1000 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1001 cmd.resp_type = MMC_RSP_R1;
1003 err = mmc_send_cmd(mmc, &cmd, NULL);
1010 /* Put the Card in Identify Mode */
1011 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1012 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1013 cmd.resp_type = MMC_RSP_R2;
1016 err = mmc_send_cmd(mmc, &cmd, NULL);
1021 memcpy(mmc->cid, cmd.response, 16);
1024 * For MMC cards, set the Relative Address.
1025 * For SD cards, get the Relatvie Address.
1026 * This also puts the cards into Standby State
1028 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1029 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1030 cmd.cmdarg = mmc->rca << 16;
1031 cmd.resp_type = MMC_RSP_R6;
1033 err = mmc_send_cmd(mmc, &cmd, NULL);
1039 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1042 /* Get the Card-Specific Data */
1043 cmd.cmdidx = MMC_CMD_SEND_CSD;
1044 cmd.resp_type = MMC_RSP_R2;
1045 cmd.cmdarg = mmc->rca << 16;
1047 err = mmc_send_cmd(mmc, &cmd, NULL);
1049 /* Waiting for the ready status */
1050 mmc_send_status(mmc, timeout);
1055 mmc->csd[0] = cmd.response[0];
1056 mmc->csd[1] = cmd.response[1];
1057 mmc->csd[2] = cmd.response[2];
1058 mmc->csd[3] = cmd.response[3];
1060 if (mmc->version == MMC_VERSION_UNKNOWN) {
1061 int version = (cmd.response[0] >> 26) & 0xf;
1065 mmc->version = MMC_VERSION_1_2;
1068 mmc->version = MMC_VERSION_1_4;
1071 mmc->version = MMC_VERSION_2_2;
1074 mmc->version = MMC_VERSION_3;
1077 mmc->version = MMC_VERSION_4;
1080 mmc->version = MMC_VERSION_1_2;
1085 /* divide frequency by 10, since the mults are 10x bigger */
1086 freq = fbase[(cmd.response[0] & 0x7)];
1087 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1089 mmc->tran_speed = freq * mult;
1091 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1092 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1095 mmc->write_bl_len = mmc->read_bl_len;
1097 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1099 if (mmc->high_capacity) {
1100 csize = (mmc->csd[1] & 0x3f) << 16
1101 | (mmc->csd[2] & 0xffff0000) >> 16;
1104 csize = (mmc->csd[1] & 0x3ff) << 2
1105 | (mmc->csd[2] & 0xc0000000) >> 30;
1106 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1109 mmc->capacity_user = (csize + 1) << (cmult + 2);
1110 mmc->capacity_user *= mmc->read_bl_len;
1111 mmc->capacity_boot = 0;
1112 mmc->capacity_rpmb = 0;
1113 for (i = 0; i < 4; i++)
1114 mmc->capacity_gp[i] = 0;
1116 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1117 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1119 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1120 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1122 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1123 cmd.cmdidx = MMC_CMD_SET_DSR;
1124 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1125 cmd.resp_type = MMC_RSP_NONE;
1126 if (mmc_send_cmd(mmc, &cmd, NULL))
1127 printf("MMC: SET_DSR failed\n");
1130 /* Select the card, and put it into Transfer Mode */
1131 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1132 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1133 cmd.resp_type = MMC_RSP_R1;
1134 cmd.cmdarg = mmc->rca << 16;
1135 err = mmc_send_cmd(mmc, &cmd, NULL);
1142 * For SD, its erase group is always one sector
1144 mmc->erase_grp_size = 1;
1145 mmc->part_config = MMCPART_NOAVAILABLE;
1146 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1147 /* check ext_csd version and capacity */
1148 err = mmc_send_ext_csd(mmc, ext_csd);
1151 if (ext_csd[EXT_CSD_REV] >= 2) {
1153 * According to the JEDEC Standard, the value of
1154 * ext_csd's capacity is valid if the value is more
1157 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1158 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1159 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1160 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1161 capacity *= MMC_MAX_BLOCK_LEN;
1162 if ((capacity >> 20) > 2 * 1024)
1163 mmc->capacity_user = capacity;
1166 switch (ext_csd[EXT_CSD_REV]) {
1168 mmc->version = MMC_VERSION_4_1;
1171 mmc->version = MMC_VERSION_4_2;
1174 mmc->version = MMC_VERSION_4_3;
1177 mmc->version = MMC_VERSION_4_41;
1180 mmc->version = MMC_VERSION_4_5;
1183 mmc->version = MMC_VERSION_5_0;
1186 mmc->version = MMC_VERSION_5_1;
1190 /* The partition data may be non-zero but it is only
1191 * effective if PARTITION_SETTING_COMPLETED is set in
1192 * EXT_CSD, so ignore any data if this bit is not set,
1193 * except for enabling the high-capacity group size
1194 * definition (see below). */
1195 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1196 EXT_CSD_PARTITION_SETTING_COMPLETED);
1198 /* store the partition info of emmc */
1199 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1200 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1201 ext_csd[EXT_CSD_BOOT_MULT])
1202 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1203 if (part_completed &&
1204 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1205 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1207 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1209 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1211 for (i = 0; i < 4; i++) {
1212 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1213 uint mult = (ext_csd[idx + 2] << 16) +
1214 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1217 if (!part_completed)
1219 mmc->capacity_gp[i] = mult;
1220 mmc->capacity_gp[i] *=
1221 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1222 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1223 mmc->capacity_gp[i] <<= 19;
1226 if (part_completed) {
1227 mmc->enh_user_size =
1228 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1229 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1230 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1231 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1232 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1233 mmc->enh_user_size <<= 19;
1234 mmc->enh_user_start =
1235 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1236 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1237 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1238 ext_csd[EXT_CSD_ENH_START_ADDR];
1239 if (mmc->high_capacity)
1240 mmc->enh_user_start <<= 9;
1244 * Host needs to enable ERASE_GRP_DEF bit if device is
1245 * partitioned. This bit will be lost every time after a reset
1246 * or power off. This will affect erase size.
1250 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1251 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1254 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1255 EXT_CSD_ERASE_GROUP_DEF, 1);
1260 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1263 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1264 /* Read out group size from ext_csd */
1265 mmc->erase_grp_size =
1266 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1268 * if high capacity and partition setting completed
1269 * SEC_COUNT is valid even if it is smaller than 2 GiB
1270 * JEDEC Standard JESD84-B45, 6.2.4
1272 if (mmc->high_capacity && part_completed) {
1273 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1274 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1275 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1276 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1277 capacity *= MMC_MAX_BLOCK_LEN;
1278 mmc->capacity_user = capacity;
1281 /* Calculate the group size from the csd value. */
1282 int erase_gsz, erase_gmul;
1283 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1284 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1285 mmc->erase_grp_size = (erase_gsz + 1)
1289 mmc->hc_wp_grp_size = 1024
1290 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1291 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1293 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1296 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1301 err = sd_change_freq(mmc);
1303 err = mmc_change_freq(mmc);
1308 /* Restrict card's capabilities by what the host can do */
1309 mmc->card_caps &= mmc->cfg->host_caps;
1312 if (mmc->card_caps & MMC_MODE_4BIT) {
1313 cmd.cmdidx = MMC_CMD_APP_CMD;
1314 cmd.resp_type = MMC_RSP_R1;
1315 cmd.cmdarg = mmc->rca << 16;
1317 err = mmc_send_cmd(mmc, &cmd, NULL);
1321 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1322 cmd.resp_type = MMC_RSP_R1;
1324 err = mmc_send_cmd(mmc, &cmd, NULL);
1328 mmc_set_bus_width(mmc, 4);
1331 if (mmc->card_caps & MMC_MODE_HS)
1332 mmc->tran_speed = 50000000;
1334 mmc->tran_speed = 25000000;
1335 } else if (mmc->version >= MMC_VERSION_4) {
1336 /* Only version 4 of MMC supports wider bus widths */
1339 /* An array of possible bus widths in order of preference */
1340 static unsigned ext_csd_bits[] = {
1341 EXT_CSD_DDR_BUS_WIDTH_8,
1342 EXT_CSD_DDR_BUS_WIDTH_4,
1343 EXT_CSD_BUS_WIDTH_8,
1344 EXT_CSD_BUS_WIDTH_4,
1345 EXT_CSD_BUS_WIDTH_1,
1348 /* An array to map CSD bus widths to host cap bits */
1349 static unsigned ext_to_hostcaps[] = {
1350 [EXT_CSD_DDR_BUS_WIDTH_4] =
1351 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1352 [EXT_CSD_DDR_BUS_WIDTH_8] =
1353 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1354 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1355 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1358 /* An array to map chosen bus width to an integer */
1359 static unsigned widths[] = {
1363 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1364 unsigned int extw = ext_csd_bits[idx];
1365 unsigned int caps = ext_to_hostcaps[extw];
1368 * If the bus width is still not changed,
1369 * don't try to set the default again.
1370 * Otherwise, recover from switch attempts
1371 * by switching to 1-bit bus width.
1373 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1374 mmc->bus_width == 1) {
1380 * Check to make sure the card and controller support
1381 * these capabilities
1383 if ((mmc->card_caps & caps) != caps)
1386 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1387 EXT_CSD_BUS_WIDTH, extw);
1392 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1393 mmc_set_bus_width(mmc, widths[idx]);
1395 err = mmc_send_ext_csd(mmc, test_csd);
1400 /* Only compare read only fields */
1401 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1402 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1403 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1404 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1405 ext_csd[EXT_CSD_REV]
1406 == test_csd[EXT_CSD_REV] &&
1407 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1408 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1409 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1410 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1419 if (mmc->card_caps & MMC_MODE_HS) {
1420 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1421 mmc->tran_speed = 52000000;
1423 mmc->tran_speed = 26000000;
1427 mmc_set_clock(mmc, mmc->tran_speed);
1429 /* Fix the block length for DDR mode */
1430 if (mmc->ddr_mode) {
1431 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1432 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1435 /* fill in device description */
1436 bdesc = mmc_get_blk_desc(mmc);
1440 bdesc->blksz = mmc->read_bl_len;
1441 bdesc->log2blksz = LOG2(bdesc->blksz);
1442 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1443 #if !defined(CONFIG_SPL_BUILD) || \
1444 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1445 !defined(CONFIG_USE_TINY_PRINTF))
1446 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1447 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1448 (mmc->cid[3] >> 16) & 0xffff);
1449 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1450 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1451 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1452 (mmc->cid[2] >> 24) & 0xff);
1453 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1454 (mmc->cid[2] >> 16) & 0xf);
1456 bdesc->vendor[0] = 0;
1457 bdesc->product[0] = 0;
1458 bdesc->revision[0] = 0;
1460 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1467 static int mmc_send_if_cond(struct mmc *mmc)
1472 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1473 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1474 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1475 cmd.resp_type = MMC_RSP_R7;
1477 err = mmc_send_cmd(mmc, &cmd, NULL);
1482 if ((cmd.response[0] & 0xff) != 0xaa)
1483 return UNUSABLE_ERR;
1485 mmc->version = SD_VERSION_2;
1490 /* board-specific MMC power initializations. */
1491 __weak void board_mmc_power_init(void)
1495 int mmc_start_init(struct mmc *mmc)
1499 /* we pretend there's no card when init is NULL */
1500 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
1502 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1503 printf("MMC: no card present\n");
1511 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1512 mmc_adapter_card_type_ident();
1514 board_mmc_power_init();
1516 /* made sure it's not NULL earlier */
1517 err = mmc->cfg->ops->init(mmc);
1523 mmc_set_bus_width(mmc, 1);
1524 mmc_set_clock(mmc, 1);
1526 /* Reset the Card */
1527 err = mmc_go_idle(mmc);
1532 /* The internal partition reset to user partition(0) at every CMD0*/
1533 mmc_get_blk_desc(mmc)->hwpart = 0;
1535 /* Test for SD version 2 */
1536 err = mmc_send_if_cond(mmc);
1538 /* Now try to get the SD card's operating condition */
1539 err = sd_send_op_cond(mmc);
1541 /* If the command timed out, we check for an MMC card */
1542 if (err == TIMEOUT) {
1543 err = mmc_send_op_cond(mmc);
1546 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1547 printf("Card did not respond to voltage select!\n");
1549 return UNUSABLE_ERR;
1554 mmc->init_in_progress = 1;
1559 static int mmc_complete_init(struct mmc *mmc)
1563 mmc->init_in_progress = 0;
1564 if (mmc->op_cond_pending)
1565 err = mmc_complete_op_cond(mmc);
1568 err = mmc_startup(mmc);
1576 int mmc_init(struct mmc *mmc)
1580 #ifdef CONFIG_DM_MMC
1581 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
1588 start = get_timer(0);
1590 if (!mmc->init_in_progress)
1591 err = mmc_start_init(mmc);
1594 err = mmc_complete_init(mmc);
1595 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
1599 int mmc_set_dsr(struct mmc *mmc, u16 val)
1605 /* CPU-specific MMC initializations */
1606 __weak int cpu_mmc_init(bd_t *bis)
1611 /* board-specific MMC initializations. */
1612 __weak int board_mmc_init(bd_t *bis)
1617 void mmc_set_preinit(struct mmc *mmc, int preinit)
1619 mmc->preinit = preinit;
1622 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
1623 static int mmc_probe(bd_t *bis)
1627 #elif defined(CONFIG_DM_MMC)
1628 static int mmc_probe(bd_t *bis)
1632 struct udevice *dev;
1634 ret = uclass_get(UCLASS_MMC, &uc);
1639 * Try to add them in sequence order. Really with driver model we
1640 * should allow holes, but the current MMC list does not allow that.
1641 * So if we request 0, 1, 3 we will get 0, 1, 2.
1643 for (i = 0; ; i++) {
1644 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1648 uclass_foreach_dev(dev, uc) {
1649 ret = device_probe(dev);
1651 printf("%s - probe failed: %d\n", dev->name, ret);
1657 static int mmc_probe(bd_t *bis)
1659 if (board_mmc_init(bis) < 0)
1666 int mmc_initialize(bd_t *bis)
1668 static int initialized = 0;
1670 if (initialized) /* Avoid initializing mmc multiple times */
1677 ret = mmc_probe(bis);
1681 #ifndef CONFIG_SPL_BUILD
1682 print_mmc_devices(',');