2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
18 #include <power/regulator.h>
21 #include <linux/list.h>
23 #include "mmc_private.h"
25 static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
33 #if CONFIG_IS_ENABLED(MMC_TINY)
34 static struct mmc mmc_static;
35 struct mmc *find_mmc_device(int dev_num)
40 void mmc_do_preinit(void)
42 struct mmc *m = &mmc_static;
43 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
44 mmc_set_preinit(m, 1);
50 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
52 return &mmc->block_dev;
56 #ifndef CONFIG_DM_MMC_OPS
57 __weak int board_mmc_getwp(struct mmc *mmc)
62 int mmc_getwp(struct mmc *mmc)
66 wp = board_mmc_getwp(mmc);
69 if (mmc->cfg->ops->getwp)
70 wp = mmc->cfg->ops->getwp(mmc);
78 __weak int board_mmc_getcd(struct mmc *mmc)
84 #ifdef CONFIG_MMC_TRACE
85 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
87 printf("CMD_SEND:%d\n", cmd->cmdidx);
88 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
91 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
97 printf("\t\tRET\t\t\t %d\n", ret);
99 switch (cmd->resp_type) {
101 printf("\t\tMMC_RSP_NONE\n");
104 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
108 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
112 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
114 printf("\t\t \t\t 0x%08X \n",
116 printf("\t\t \t\t 0x%08X \n",
118 printf("\t\t \t\t 0x%08X \n",
121 printf("\t\t\t\t\tDUMPING DATA\n");
122 for (i = 0; i < 4; i++) {
124 printf("\t\t\t\t\t%03d - ", i*4);
125 ptr = (u8 *)&cmd->response[i];
127 for (j = 0; j < 4; j++)
128 printf("%02X ", *ptr--);
133 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
137 printf("\t\tERROR MMC rsp not supported\n");
143 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
147 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
148 printf("CURR STATE:%d\n", status);
152 #ifndef CONFIG_DM_MMC_OPS
153 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
157 mmmc_trace_before_send(mmc, cmd);
158 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
159 mmmc_trace_after_send(mmc, cmd, ret);
165 int mmc_send_status(struct mmc *mmc, int timeout)
168 int err, retries = 5;
170 cmd.cmdidx = MMC_CMD_SEND_STATUS;
171 cmd.resp_type = MMC_RSP_R1;
172 if (!mmc_host_is_spi(mmc))
173 cmd.cmdarg = mmc->rca << 16;
176 err = mmc_send_cmd(mmc, &cmd, NULL);
178 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
179 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
182 else if (cmd.response[0] & MMC_STATUS_MASK) {
183 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
184 printf("Status Error: 0x%08X\n",
189 } else if (--retries < 0)
198 mmc_trace_state(mmc, &cmd);
200 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
201 printf("Timeout waiting card ready\n");
209 int mmc_set_blocklen(struct mmc *mmc, int len)
216 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
217 cmd.resp_type = MMC_RSP_R1;
220 return mmc_send_cmd(mmc, &cmd, NULL);
223 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
227 struct mmc_data data;
230 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
232 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
234 if (mmc->high_capacity)
237 cmd.cmdarg = start * mmc->read_bl_len;
239 cmd.resp_type = MMC_RSP_R1;
242 data.blocks = blkcnt;
243 data.blocksize = mmc->read_bl_len;
244 data.flags = MMC_DATA_READ;
246 if (mmc_send_cmd(mmc, &cmd, &data))
250 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
252 cmd.resp_type = MMC_RSP_R1b;
253 if (mmc_send_cmd(mmc, &cmd, NULL)) {
254 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
255 printf("mmc fail to send stop cmd\n");
265 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
267 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
272 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
274 int dev_num = block_dev->devnum;
276 lbaint_t cur, blocks_todo = blkcnt;
281 struct mmc *mmc = find_mmc_device(dev_num);
285 if (CONFIG_IS_ENABLED(MMC_TINY))
286 err = mmc_switch_part(mmc, block_dev->hwpart);
288 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
293 if ((start + blkcnt) > block_dev->lba) {
294 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
295 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
296 start + blkcnt, block_dev->lba);
301 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
302 debug("%s: Failed to set blocklen\n", __func__);
307 cur = (blocks_todo > mmc->cfg->b_max) ?
308 mmc->cfg->b_max : blocks_todo;
309 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
310 debug("%s: Failed to read blocks\n", __func__);
315 dst += cur * mmc->read_bl_len;
316 } while (blocks_todo > 0);
321 static int mmc_go_idle(struct mmc *mmc)
328 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
330 cmd.resp_type = MMC_RSP_NONE;
332 err = mmc_send_cmd(mmc, &cmd, NULL);
342 static int sd_send_op_cond(struct mmc *mmc)
349 cmd.cmdidx = MMC_CMD_APP_CMD;
350 cmd.resp_type = MMC_RSP_R1;
353 err = mmc_send_cmd(mmc, &cmd, NULL);
358 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
359 cmd.resp_type = MMC_RSP_R3;
362 * Most cards do not answer if some reserved bits
363 * in the ocr are set. However, Some controller
364 * can set bit 7 (reserved for low voltages), but
365 * how to manage low voltages SD card is not yet
368 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
369 (mmc->cfg->voltages & 0xff8000);
371 if (mmc->version == SD_VERSION_2)
372 cmd.cmdarg |= OCR_HCS;
374 err = mmc_send_cmd(mmc, &cmd, NULL);
379 if (cmd.response[0] & OCR_BUSY)
388 if (mmc->version != SD_VERSION_2)
389 mmc->version = SD_VERSION_1_0;
391 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
392 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
393 cmd.resp_type = MMC_RSP_R3;
396 err = mmc_send_cmd(mmc, &cmd, NULL);
402 mmc->ocr = cmd.response[0];
404 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
410 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
415 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
416 cmd.resp_type = MMC_RSP_R3;
418 if (use_arg && !mmc_host_is_spi(mmc))
419 cmd.cmdarg = OCR_HCS |
420 (mmc->cfg->voltages &
421 (mmc->ocr & OCR_VOLTAGE_MASK)) |
422 (mmc->ocr & OCR_ACCESS_MODE);
424 err = mmc_send_cmd(mmc, &cmd, NULL);
427 mmc->ocr = cmd.response[0];
431 static int mmc_send_op_cond(struct mmc *mmc)
435 /* Some cards seem to need this */
438 /* Asking to the card its capabilities */
439 for (i = 0; i < 2; i++) {
440 err = mmc_send_op_cond_iter(mmc, i != 0);
444 /* exit if not busy (flag seems to be inverted) */
445 if (mmc->ocr & OCR_BUSY)
448 mmc->op_cond_pending = 1;
452 static int mmc_complete_op_cond(struct mmc *mmc)
459 mmc->op_cond_pending = 0;
460 if (!(mmc->ocr & OCR_BUSY)) {
461 /* Some cards seem to need this */
464 start = get_timer(0);
466 err = mmc_send_op_cond_iter(mmc, 1);
469 if (mmc->ocr & OCR_BUSY)
471 if (get_timer(start) > timeout)
477 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
478 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
479 cmd.resp_type = MMC_RSP_R3;
482 err = mmc_send_cmd(mmc, &cmd, NULL);
487 mmc->ocr = cmd.response[0];
490 mmc->version = MMC_VERSION_UNKNOWN;
492 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
499 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
502 struct mmc_data data;
505 /* Get the Card Status Register */
506 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
507 cmd.resp_type = MMC_RSP_R1;
510 data.dest = (char *)ext_csd;
512 data.blocksize = MMC_MAX_BLOCK_LEN;
513 data.flags = MMC_DATA_READ;
515 err = mmc_send_cmd(mmc, &cmd, &data);
520 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
527 cmd.cmdidx = MMC_CMD_SWITCH;
528 cmd.resp_type = MMC_RSP_R1b;
529 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
533 while (retries > 0) {
534 ret = mmc_send_cmd(mmc, &cmd, NULL);
536 /* Waiting for the ready status */
538 ret = mmc_send_status(mmc, timeout);
549 static int mmc_change_freq(struct mmc *mmc)
551 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
557 if (mmc_host_is_spi(mmc))
560 /* Only version 4 supports high-speed */
561 if (mmc->version < MMC_VERSION_4)
564 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
566 err = mmc_send_ext_csd(mmc, ext_csd);
571 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
573 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
578 /* Now check to see that it worked */
579 err = mmc_send_ext_csd(mmc, ext_csd);
584 /* No high-speed support */
585 if (!ext_csd[EXT_CSD_HS_TIMING])
588 /* High Speed is set, there are two types: 52MHz and 26MHz */
589 if (cardtype & EXT_CSD_CARD_TYPE_52) {
590 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
591 mmc->card_caps |= MMC_MODE_DDR_52MHz;
592 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
594 mmc->card_caps |= MMC_MODE_HS;
600 static int mmc_set_capacity(struct mmc *mmc, int part_num)
604 mmc->capacity = mmc->capacity_user;
608 mmc->capacity = mmc->capacity_boot;
611 mmc->capacity = mmc->capacity_rpmb;
617 mmc->capacity = mmc->capacity_gp[part_num - 4];
623 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
628 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
632 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
633 (mmc->part_config & ~PART_ACCESS_MASK)
634 | (part_num & PART_ACCESS_MASK));
637 * Set the capacity if the switch succeeded or was intended
638 * to return to representing the raw device.
640 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
641 ret = mmc_set_capacity(mmc, part_num);
642 mmc_get_blk_desc(mmc)->hwpart = part_num;
648 int mmc_hwpart_config(struct mmc *mmc,
649 const struct mmc_hwpart_conf *conf,
650 enum mmc_hwpart_conf_mode mode)
656 u32 max_enh_size_mult;
657 u32 tot_enh_size_mult = 0;
660 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
662 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
665 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
666 printf("eMMC >= 4.4 required for enhanced user data area\n");
670 if (!(mmc->part_support & PART_SUPPORT)) {
671 printf("Card does not support partitioning\n");
675 if (!mmc->hc_wp_grp_size) {
676 printf("Card does not define HC WP group size\n");
680 /* check partition alignment and total enhanced size */
681 if (conf->user.enh_size) {
682 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
683 conf->user.enh_start % mmc->hc_wp_grp_size) {
684 printf("User data enhanced area not HC WP group "
688 part_attrs |= EXT_CSD_ENH_USR;
689 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
690 if (mmc->high_capacity) {
691 enh_start_addr = conf->user.enh_start;
693 enh_start_addr = (conf->user.enh_start << 9);
699 tot_enh_size_mult += enh_size_mult;
701 for (pidx = 0; pidx < 4; pidx++) {
702 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
703 printf("GP%i partition not HC WP group size "
704 "aligned\n", pidx+1);
707 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
708 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
709 part_attrs |= EXT_CSD_ENH_GP(pidx);
710 tot_enh_size_mult += gp_size_mult[pidx];
714 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
715 printf("Card does not support enhanced attribute\n");
719 err = mmc_send_ext_csd(mmc, ext_csd);
724 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
725 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
726 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
727 if (tot_enh_size_mult > max_enh_size_mult) {
728 printf("Total enhanced size exceeds maximum (%u > %u)\n",
729 tot_enh_size_mult, max_enh_size_mult);
733 /* The default value of EXT_CSD_WR_REL_SET is device
734 * dependent, the values can only be changed if the
735 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
736 * changed only once and before partitioning is completed. */
737 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
738 if (conf->user.wr_rel_change) {
739 if (conf->user.wr_rel_set)
740 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
742 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
744 for (pidx = 0; pidx < 4; pidx++) {
745 if (conf->gp_part[pidx].wr_rel_change) {
746 if (conf->gp_part[pidx].wr_rel_set)
747 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
749 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
753 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
754 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
755 puts("Card does not support host controlled partition write "
756 "reliability settings\n");
760 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
761 EXT_CSD_PARTITION_SETTING_COMPLETED) {
762 printf("Card already partitioned\n");
766 if (mode == MMC_HWPART_CONF_CHECK)
769 /* Partitioning requires high-capacity size definitions */
770 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
771 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
772 EXT_CSD_ERASE_GROUP_DEF, 1);
777 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
779 /* update erase group size to be high-capacity */
780 mmc->erase_grp_size =
781 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
785 /* all OK, write the configuration */
786 for (i = 0; i < 4; i++) {
787 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
788 EXT_CSD_ENH_START_ADDR+i,
789 (enh_start_addr >> (i*8)) & 0xFF);
793 for (i = 0; i < 3; i++) {
794 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
795 EXT_CSD_ENH_SIZE_MULT+i,
796 (enh_size_mult >> (i*8)) & 0xFF);
800 for (pidx = 0; pidx < 4; pidx++) {
801 for (i = 0; i < 3; i++) {
802 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
803 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
804 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
809 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
810 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
814 if (mode == MMC_HWPART_CONF_SET)
817 /* The WR_REL_SET is a write-once register but shall be
818 * written before setting PART_SETTING_COMPLETED. As it is
819 * write-once we can only write it when completing the
821 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
822 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
823 EXT_CSD_WR_REL_SET, wr_rel_set);
828 /* Setting PART_SETTING_COMPLETED confirms the partition
829 * configuration but it only becomes effective after power
830 * cycle, so we do not adjust the partition related settings
831 * in the mmc struct. */
833 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
834 EXT_CSD_PARTITION_SETTING,
835 EXT_CSD_PARTITION_SETTING_COMPLETED);
842 #ifndef CONFIG_DM_MMC_OPS
843 int mmc_getcd(struct mmc *mmc)
847 cd = board_mmc_getcd(mmc);
850 if (mmc->cfg->ops->getcd)
851 cd = mmc->cfg->ops->getcd(mmc);
860 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
863 struct mmc_data data;
865 /* Switch the frequency */
866 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
867 cmd.resp_type = MMC_RSP_R1;
868 cmd.cmdarg = (mode << 31) | 0xffffff;
869 cmd.cmdarg &= ~(0xf << (group * 4));
870 cmd.cmdarg |= value << (group * 4);
872 data.dest = (char *)resp;
875 data.flags = MMC_DATA_READ;
877 return mmc_send_cmd(mmc, &cmd, &data);
881 static int sd_change_freq(struct mmc *mmc)
885 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
886 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
887 struct mmc_data data;
892 if (mmc_host_is_spi(mmc))
895 /* Read the SCR to find out if this card supports higher speeds */
896 cmd.cmdidx = MMC_CMD_APP_CMD;
897 cmd.resp_type = MMC_RSP_R1;
898 cmd.cmdarg = mmc->rca << 16;
900 err = mmc_send_cmd(mmc, &cmd, NULL);
905 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
906 cmd.resp_type = MMC_RSP_R1;
912 data.dest = (char *)scr;
915 data.flags = MMC_DATA_READ;
917 err = mmc_send_cmd(mmc, &cmd, &data);
926 mmc->scr[0] = __be32_to_cpu(scr[0]);
927 mmc->scr[1] = __be32_to_cpu(scr[1]);
929 switch ((mmc->scr[0] >> 24) & 0xf) {
931 mmc->version = SD_VERSION_1_0;
934 mmc->version = SD_VERSION_1_10;
937 mmc->version = SD_VERSION_2;
938 if ((mmc->scr[0] >> 15) & 0x1)
939 mmc->version = SD_VERSION_3;
942 mmc->version = SD_VERSION_1_0;
946 if (mmc->scr[0] & SD_DATA_4BIT)
947 mmc->card_caps |= MMC_MODE_4BIT;
949 /* Version 1.0 doesn't support switching */
950 if (mmc->version == SD_VERSION_1_0)
955 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
956 (u8 *)switch_status);
961 /* The high-speed function is busy. Try again */
962 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
966 /* If high-speed isn't supported, we return */
967 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
971 * If the host doesn't support SD_HIGHSPEED, do not switch card to
972 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
973 * This can avoid furthur problem when the card runs in different
974 * mode between the host.
976 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
977 (mmc->cfg->host_caps & MMC_MODE_HS)))
980 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
985 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
986 mmc->card_caps |= MMC_MODE_HS;
991 static int sd_read_ssr(struct mmc *mmc)
995 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
996 struct mmc_data data;
998 unsigned int au, eo, et, es;
1000 cmd.cmdidx = MMC_CMD_APP_CMD;
1001 cmd.resp_type = MMC_RSP_R1;
1002 cmd.cmdarg = mmc->rca << 16;
1004 err = mmc_send_cmd(mmc, &cmd, NULL);
1008 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1009 cmd.resp_type = MMC_RSP_R1;
1013 data.dest = (char *)ssr;
1014 data.blocksize = 64;
1016 data.flags = MMC_DATA_READ;
1018 err = mmc_send_cmd(mmc, &cmd, &data);
1026 for (i = 0; i < 16; i++)
1027 ssr[i] = be32_to_cpu(ssr[i]);
1029 au = (ssr[2] >> 12) & 0xF;
1030 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1031 mmc->ssr.au = sd_au_size[au];
1032 es = (ssr[3] >> 24) & 0xFF;
1033 es |= (ssr[2] & 0xFF) << 8;
1034 et = (ssr[3] >> 18) & 0x3F;
1036 eo = (ssr[3] >> 16) & 0x3;
1037 mmc->ssr.erase_timeout = (et * 1000) / es;
1038 mmc->ssr.erase_offset = eo * 1000;
1041 debug("Invalid Allocation Unit Size.\n");
1047 /* frequency bases */
1048 /* divided by 10 to be nice to platforms without floating point */
1049 static const int fbase[] = {
1056 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1057 * to platforms without floating point.
1059 static const u8 multipliers[] = {
1078 #ifndef CONFIG_DM_MMC_OPS
1079 static void mmc_set_ios(struct mmc *mmc)
1081 if (mmc->cfg->ops->set_ios)
1082 mmc->cfg->ops->set_ios(mmc);
1086 void mmc_set_clock(struct mmc *mmc, uint clock)
1088 if (clock > mmc->cfg->f_max)
1089 clock = mmc->cfg->f_max;
1091 if (clock < mmc->cfg->f_min)
1092 clock = mmc->cfg->f_min;
1099 static void mmc_set_bus_width(struct mmc *mmc, uint width)
1101 mmc->bus_width = width;
1106 static int mmc_startup(struct mmc *mmc)
1110 u64 cmult, csize, capacity;
1112 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1113 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1115 bool has_parts = false;
1116 bool part_completed;
1117 struct blk_desc *bdesc;
1119 #ifdef CONFIG_MMC_SPI_CRC_ON
1120 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1121 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1122 cmd.resp_type = MMC_RSP_R1;
1124 err = mmc_send_cmd(mmc, &cmd, NULL);
1131 /* Put the Card in Identify Mode */
1132 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1133 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1134 cmd.resp_type = MMC_RSP_R2;
1137 err = mmc_send_cmd(mmc, &cmd, NULL);
1142 memcpy(mmc->cid, cmd.response, 16);
1145 * For MMC cards, set the Relative Address.
1146 * For SD cards, get the Relatvie Address.
1147 * This also puts the cards into Standby State
1149 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1150 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1151 cmd.cmdarg = mmc->rca << 16;
1152 cmd.resp_type = MMC_RSP_R6;
1154 err = mmc_send_cmd(mmc, &cmd, NULL);
1160 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1163 /* Get the Card-Specific Data */
1164 cmd.cmdidx = MMC_CMD_SEND_CSD;
1165 cmd.resp_type = MMC_RSP_R2;
1166 cmd.cmdarg = mmc->rca << 16;
1168 err = mmc_send_cmd(mmc, &cmd, NULL);
1170 /* Waiting for the ready status */
1171 mmc_send_status(mmc, timeout);
1176 mmc->csd[0] = cmd.response[0];
1177 mmc->csd[1] = cmd.response[1];
1178 mmc->csd[2] = cmd.response[2];
1179 mmc->csd[3] = cmd.response[3];
1181 if (mmc->version == MMC_VERSION_UNKNOWN) {
1182 int version = (cmd.response[0] >> 26) & 0xf;
1186 mmc->version = MMC_VERSION_1_2;
1189 mmc->version = MMC_VERSION_1_4;
1192 mmc->version = MMC_VERSION_2_2;
1195 mmc->version = MMC_VERSION_3;
1198 mmc->version = MMC_VERSION_4;
1201 mmc->version = MMC_VERSION_1_2;
1206 /* divide frequency by 10, since the mults are 10x bigger */
1207 freq = fbase[(cmd.response[0] & 0x7)];
1208 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1210 mmc->tran_speed = freq * mult;
1212 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1213 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1216 mmc->write_bl_len = mmc->read_bl_len;
1218 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1220 if (mmc->high_capacity) {
1221 csize = (mmc->csd[1] & 0x3f) << 16
1222 | (mmc->csd[2] & 0xffff0000) >> 16;
1225 csize = (mmc->csd[1] & 0x3ff) << 2
1226 | (mmc->csd[2] & 0xc0000000) >> 30;
1227 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1230 mmc->capacity_user = (csize + 1) << (cmult + 2);
1231 mmc->capacity_user *= mmc->read_bl_len;
1232 mmc->capacity_boot = 0;
1233 mmc->capacity_rpmb = 0;
1234 for (i = 0; i < 4; i++)
1235 mmc->capacity_gp[i] = 0;
1237 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1238 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1240 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1241 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1243 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1244 cmd.cmdidx = MMC_CMD_SET_DSR;
1245 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1246 cmd.resp_type = MMC_RSP_NONE;
1247 if (mmc_send_cmd(mmc, &cmd, NULL))
1248 printf("MMC: SET_DSR failed\n");
1251 /* Select the card, and put it into Transfer Mode */
1252 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1253 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1254 cmd.resp_type = MMC_RSP_R1;
1255 cmd.cmdarg = mmc->rca << 16;
1256 err = mmc_send_cmd(mmc, &cmd, NULL);
1263 * For SD, its erase group is always one sector
1265 mmc->erase_grp_size = 1;
1266 mmc->part_config = MMCPART_NOAVAILABLE;
1267 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1268 /* check ext_csd version and capacity */
1269 err = mmc_send_ext_csd(mmc, ext_csd);
1272 if (ext_csd[EXT_CSD_REV] >= 2) {
1274 * According to the JEDEC Standard, the value of
1275 * ext_csd's capacity is valid if the value is more
1278 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1279 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1280 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1281 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1282 capacity *= MMC_MAX_BLOCK_LEN;
1283 if ((capacity >> 20) > 2 * 1024)
1284 mmc->capacity_user = capacity;
1287 switch (ext_csd[EXT_CSD_REV]) {
1289 mmc->version = MMC_VERSION_4_1;
1292 mmc->version = MMC_VERSION_4_2;
1295 mmc->version = MMC_VERSION_4_3;
1298 mmc->version = MMC_VERSION_4_41;
1301 mmc->version = MMC_VERSION_4_5;
1304 mmc->version = MMC_VERSION_5_0;
1307 mmc->version = MMC_VERSION_5_1;
1311 /* The partition data may be non-zero but it is only
1312 * effective if PARTITION_SETTING_COMPLETED is set in
1313 * EXT_CSD, so ignore any data if this bit is not set,
1314 * except for enabling the high-capacity group size
1315 * definition (see below). */
1316 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1317 EXT_CSD_PARTITION_SETTING_COMPLETED);
1319 /* store the partition info of emmc */
1320 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1321 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1322 ext_csd[EXT_CSD_BOOT_MULT])
1323 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1324 if (part_completed &&
1325 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1326 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1328 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1330 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1332 for (i = 0; i < 4; i++) {
1333 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1334 uint mult = (ext_csd[idx + 2] << 16) +
1335 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1338 if (!part_completed)
1340 mmc->capacity_gp[i] = mult;
1341 mmc->capacity_gp[i] *=
1342 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1343 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1344 mmc->capacity_gp[i] <<= 19;
1347 if (part_completed) {
1348 mmc->enh_user_size =
1349 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1350 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1351 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1352 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1353 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1354 mmc->enh_user_size <<= 19;
1355 mmc->enh_user_start =
1356 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1357 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1358 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1359 ext_csd[EXT_CSD_ENH_START_ADDR];
1360 if (mmc->high_capacity)
1361 mmc->enh_user_start <<= 9;
1365 * Host needs to enable ERASE_GRP_DEF bit if device is
1366 * partitioned. This bit will be lost every time after a reset
1367 * or power off. This will affect erase size.
1371 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1372 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1375 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1376 EXT_CSD_ERASE_GROUP_DEF, 1);
1381 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1384 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1385 /* Read out group size from ext_csd */
1386 mmc->erase_grp_size =
1387 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1389 * if high capacity and partition setting completed
1390 * SEC_COUNT is valid even if it is smaller than 2 GiB
1391 * JEDEC Standard JESD84-B45, 6.2.4
1393 if (mmc->high_capacity && part_completed) {
1394 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1395 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1396 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1397 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1398 capacity *= MMC_MAX_BLOCK_LEN;
1399 mmc->capacity_user = capacity;
1402 /* Calculate the group size from the csd value. */
1403 int erase_gsz, erase_gmul;
1404 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1405 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1406 mmc->erase_grp_size = (erase_gsz + 1)
1410 mmc->hc_wp_grp_size = 1024
1411 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1412 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1414 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1417 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1422 err = sd_change_freq(mmc);
1424 err = mmc_change_freq(mmc);
1429 /* Restrict card's capabilities by what the host can do */
1430 mmc->card_caps &= mmc->cfg->host_caps;
1433 if (mmc->card_caps & MMC_MODE_4BIT) {
1434 cmd.cmdidx = MMC_CMD_APP_CMD;
1435 cmd.resp_type = MMC_RSP_R1;
1436 cmd.cmdarg = mmc->rca << 16;
1438 err = mmc_send_cmd(mmc, &cmd, NULL);
1442 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1443 cmd.resp_type = MMC_RSP_R1;
1445 err = mmc_send_cmd(mmc, &cmd, NULL);
1449 mmc_set_bus_width(mmc, 4);
1452 err = sd_read_ssr(mmc);
1456 if (mmc->card_caps & MMC_MODE_HS)
1457 mmc->tran_speed = 50000000;
1459 mmc->tran_speed = 25000000;
1460 } else if (mmc->version >= MMC_VERSION_4) {
1461 /* Only version 4 of MMC supports wider bus widths */
1464 /* An array of possible bus widths in order of preference */
1465 static unsigned ext_csd_bits[] = {
1466 EXT_CSD_DDR_BUS_WIDTH_8,
1467 EXT_CSD_DDR_BUS_WIDTH_4,
1468 EXT_CSD_BUS_WIDTH_8,
1469 EXT_CSD_BUS_WIDTH_4,
1470 EXT_CSD_BUS_WIDTH_1,
1473 /* An array to map CSD bus widths to host cap bits */
1474 static unsigned ext_to_hostcaps[] = {
1475 [EXT_CSD_DDR_BUS_WIDTH_4] =
1476 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1477 [EXT_CSD_DDR_BUS_WIDTH_8] =
1478 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1479 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1480 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1483 /* An array to map chosen bus width to an integer */
1484 static unsigned widths[] = {
1488 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1489 unsigned int extw = ext_csd_bits[idx];
1490 unsigned int caps = ext_to_hostcaps[extw];
1493 * If the bus width is still not changed,
1494 * don't try to set the default again.
1495 * Otherwise, recover from switch attempts
1496 * by switching to 1-bit bus width.
1498 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1499 mmc->bus_width == 1) {
1505 * Check to make sure the card and controller support
1506 * these capabilities
1508 if ((mmc->card_caps & caps) != caps)
1511 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1512 EXT_CSD_BUS_WIDTH, extw);
1517 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1518 mmc_set_bus_width(mmc, widths[idx]);
1520 err = mmc_send_ext_csd(mmc, test_csd);
1525 /* Only compare read only fields */
1526 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1527 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1528 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1529 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1530 ext_csd[EXT_CSD_REV]
1531 == test_csd[EXT_CSD_REV] &&
1532 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1533 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1534 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1535 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1544 if (mmc->card_caps & MMC_MODE_HS) {
1545 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1546 mmc->tran_speed = 52000000;
1548 mmc->tran_speed = 26000000;
1552 mmc_set_clock(mmc, mmc->tran_speed);
1554 /* Fix the block length for DDR mode */
1555 if (mmc->ddr_mode) {
1556 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1557 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1560 /* fill in device description */
1561 bdesc = mmc_get_blk_desc(mmc);
1565 bdesc->blksz = mmc->read_bl_len;
1566 bdesc->log2blksz = LOG2(bdesc->blksz);
1567 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1568 #if !defined(CONFIG_SPL_BUILD) || \
1569 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1570 !defined(CONFIG_USE_TINY_PRINTF))
1571 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1572 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1573 (mmc->cid[3] >> 16) & 0xffff);
1574 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1575 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1576 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1577 (mmc->cid[2] >> 24) & 0xff);
1578 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1579 (mmc->cid[2] >> 16) & 0xf);
1581 bdesc->vendor[0] = 0;
1582 bdesc->product[0] = 0;
1583 bdesc->revision[0] = 0;
1585 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1592 static int mmc_send_if_cond(struct mmc *mmc)
1597 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1598 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1599 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1600 cmd.resp_type = MMC_RSP_R7;
1602 err = mmc_send_cmd(mmc, &cmd, NULL);
1607 if ((cmd.response[0] & 0xff) != 0xaa)
1610 mmc->version = SD_VERSION_2;
1615 /* board-specific MMC power initializations. */
1616 __weak void board_mmc_power_init(void)
1620 static int mmc_power_init(struct mmc *mmc)
1622 board_mmc_power_init();
1624 #if defined(CONFIG_DM_MMC) && defined(CONFIG_DM_REGULATOR) && \
1625 !defined(CONFIG_SPL_BUILD)
1626 struct udevice *vmmc_supply;
1629 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
1632 debug("%s: No vmmc supply\n", mmc->dev->name);
1636 ret = regulator_set_enable(vmmc_supply, true);
1638 puts("Error enabling VMMC supply\n");
1645 int mmc_start_init(struct mmc *mmc)
1650 /* we pretend there's no card when init is NULL */
1651 no_card = mmc_getcd(mmc) == 0;
1652 #ifndef CONFIG_DM_MMC_OPS
1653 no_card = no_card || (mmc->cfg->ops->init == NULL);
1657 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1658 printf("MMC: no card present\n");
1666 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1667 mmc_adapter_card_type_ident();
1669 err = mmc_power_init(mmc);
1673 #ifdef CONFIG_DM_MMC_OPS
1674 /* The device has already been probed ready for use */
1676 /* made sure it's not NULL earlier */
1677 err = mmc->cfg->ops->init(mmc);
1682 mmc_set_bus_width(mmc, 1);
1683 mmc_set_clock(mmc, 1);
1685 /* Reset the Card */
1686 err = mmc_go_idle(mmc);
1691 /* The internal partition reset to user partition(0) at every CMD0*/
1692 mmc_get_blk_desc(mmc)->hwpart = 0;
1694 /* Test for SD version 2 */
1695 err = mmc_send_if_cond(mmc);
1697 /* Now try to get the SD card's operating condition */
1698 err = sd_send_op_cond(mmc);
1700 /* If the command timed out, we check for an MMC card */
1701 if (err == -ETIMEDOUT) {
1702 err = mmc_send_op_cond(mmc);
1705 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1706 printf("Card did not respond to voltage select!\n");
1713 mmc->init_in_progress = 1;
1718 static int mmc_complete_init(struct mmc *mmc)
1722 mmc->init_in_progress = 0;
1723 if (mmc->op_cond_pending)
1724 err = mmc_complete_op_cond(mmc);
1727 err = mmc_startup(mmc);
1735 int mmc_init(struct mmc *mmc)
1738 __maybe_unused unsigned start;
1739 #ifdef CONFIG_DM_MMC
1740 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
1747 start = get_timer(0);
1749 if (!mmc->init_in_progress)
1750 err = mmc_start_init(mmc);
1753 err = mmc_complete_init(mmc);
1754 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
1758 int mmc_set_dsr(struct mmc *mmc, u16 val)
1764 /* CPU-specific MMC initializations */
1765 __weak int cpu_mmc_init(bd_t *bis)
1770 /* board-specific MMC initializations. */
1771 __weak int board_mmc_init(bd_t *bis)
1776 void mmc_set_preinit(struct mmc *mmc, int preinit)
1778 mmc->preinit = preinit;
1781 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
1782 static int mmc_probe(bd_t *bis)
1786 #elif defined(CONFIG_DM_MMC)
1787 static int mmc_probe(bd_t *bis)
1791 struct udevice *dev;
1793 ret = uclass_get(UCLASS_MMC, &uc);
1798 * Try to add them in sequence order. Really with driver model we
1799 * should allow holes, but the current MMC list does not allow that.
1800 * So if we request 0, 1, 3 we will get 0, 1, 2.
1802 for (i = 0; ; i++) {
1803 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1807 uclass_foreach_dev(dev, uc) {
1808 ret = device_probe(dev);
1810 printf("%s - probe failed: %d\n", dev->name, ret);
1816 static int mmc_probe(bd_t *bis)
1818 if (board_mmc_init(bis) < 0)
1825 int mmc_initialize(bd_t *bis)
1827 static int initialized = 0;
1829 if (initialized) /* Avoid initializing mmc multiple times */
1834 #if !CONFIG_IS_ENABLED(MMC_TINY)
1838 ret = mmc_probe(bis);
1842 #ifndef CONFIG_SPL_BUILD
1843 print_mmc_devices(',');
1850 #ifdef CONFIG_CMD_BKOPS_ENABLE
1851 int mmc_set_bkops_enable(struct mmc *mmc)
1854 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1856 err = mmc_send_ext_csd(mmc, ext_csd);
1858 puts("Could not get ext_csd register values\n");
1862 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
1863 puts("Background operations not supported on device\n");
1864 return -EMEDIUMTYPE;
1867 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
1868 puts("Background operations already enabled\n");
1872 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
1874 puts("Failed to enable manual background operations\n");
1878 puts("Enabled manual background operations\n");