1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
16 #include <asm/arch/sd_emmc.h>
17 #include <linux/log2.h>
19 static inline void *get_regbase(const struct mmc *mmc)
21 struct meson_mmc_platdata *pdata = mmc->priv;
23 return pdata->regbase;
26 static inline uint32_t meson_read(struct mmc *mmc, int offset)
28 return readl(get_regbase(mmc) + offset);
31 static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
33 writel(val, get_regbase(mmc) + offset);
36 static void meson_mmc_config_clock(struct mmc *mmc)
38 uint32_t meson_mmc_clk = 0;
39 unsigned int clk, clk_src, clk_div;
44 /* 1GHz / CLK_MAX_DIV = 15,9 MHz */
45 if (mmc->clock > 16000000) {
46 clk = SD_EMMC_CLKSRC_DIV2;
47 clk_src = CLK_SRC_DIV2;
49 clk = SD_EMMC_CLKSRC_24M;
50 clk_src = CLK_SRC_24M;
52 clk_div = DIV_ROUND_UP(clk, mmc->clock);
54 /* 180 phase core clock */
55 meson_mmc_clk |= CLK_CO_PHASE_180;
57 /* 180 phase tx clock */
58 meson_mmc_clk |= CLK_TX_PHASE_000;
61 meson_mmc_clk |= clk_src;
62 meson_mmc_clk |= clk_div;
64 meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK);
67 static int meson_dm_mmc_set_ios(struct udevice *dev)
69 struct mmc *mmc = mmc_get_mmc_dev(dev);
70 uint32_t meson_mmc_cfg;
72 meson_mmc_config_clock(mmc);
74 meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
76 meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK;
77 if (mmc->bus_width == 1)
78 meson_mmc_cfg |= CFG_BUS_WIDTH_1;
79 else if (mmc->bus_width == 4)
80 meson_mmc_cfg |= CFG_BUS_WIDTH_4;
81 else if (mmc->bus_width == 8)
82 meson_mmc_cfg |= CFG_BUS_WIDTH_8;
86 /* 512 bytes block length */
87 meson_mmc_cfg &= ~CFG_BL_LEN_MASK;
88 meson_mmc_cfg |= CFG_BL_LEN_512;
90 /* Response timeout 256 clk */
91 meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK;
92 meson_mmc_cfg |= CFG_RESP_TIMEOUT_256;
94 /* Command-command gap 16 clk */
95 meson_mmc_cfg &= ~CFG_RC_CC_MASK;
96 meson_mmc_cfg |= CFG_RC_CC_16;
98 meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG);
103 static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data,
106 uint32_t meson_mmc_cmd = 0, cfg;
108 meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT;
110 if (cmd->resp_type & MMC_RSP_PRESENT) {
111 if (cmd->resp_type & MMC_RSP_136)
112 meson_mmc_cmd |= CMD_CFG_RESP_128;
114 if (cmd->resp_type & MMC_RSP_BUSY)
115 meson_mmc_cmd |= CMD_CFG_R1B;
117 if (!(cmd->resp_type & MMC_RSP_CRC))
118 meson_mmc_cmd |= CMD_CFG_RESP_NOCRC;
120 meson_mmc_cmd |= CMD_CFG_NO_RESP;
124 cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
125 cfg &= ~CFG_BL_LEN_MASK;
126 cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT;
127 meson_write(mmc, cfg, MESON_SD_EMMC_CFG);
129 if (data->flags == MMC_DATA_WRITE)
130 meson_mmc_cmd |= CMD_CFG_DATA_WR;
132 meson_mmc_cmd |= CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE |
136 meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER |
137 CMD_CFG_END_OF_CHAIN;
139 meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG);
142 static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
144 struct meson_mmc_platdata *pdata = mmc->priv;
145 unsigned int data_size;
146 uint32_t data_addr = 0;
149 data_size = data->blocks * data->blocksize;
151 if (data->flags == MMC_DATA_READ) {
152 data_addr = (ulong) data->dest;
153 invalidate_dcache_range(data_addr,
154 data_addr + data_size);
156 pdata->w_buf = calloc(data_size, sizeof(char));
157 data_addr = (ulong) pdata->w_buf;
158 memcpy(pdata->w_buf, data->src, data_size);
159 flush_dcache_range(data_addr, data_addr + data_size);
163 meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT);
166 static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd)
168 if (cmd->resp_type & MMC_RSP_136) {
169 cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3);
170 cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2);
171 cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1);
172 cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
174 cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
178 static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
179 struct mmc_data *data)
181 struct mmc *mmc = mmc_get_mmc_dev(dev);
182 struct meson_mmc_platdata *pdata = mmc->priv;
187 /* max block size supported by chip is 512 byte */
188 if (data && data->blocksize > 512)
191 meson_mmc_setup_cmd(mmc, data, cmd);
192 meson_mmc_setup_addr(mmc, data);
194 meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG);
196 /* use 10s timeout */
197 start = get_timer(0);
199 status = meson_read(mmc, MESON_SD_EMMC_STATUS);
200 } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000);
202 if (!(status & STATUS_END_OF_CHAIN))
204 else if (status & STATUS_RESP_TIMEOUT)
206 else if (status & STATUS_ERR_MASK)
209 meson_mmc_read_response(mmc, cmd);
211 if (data && data->flags == MMC_DATA_WRITE)
214 /* reset status bits */
215 meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
220 static const struct dm_mmc_ops meson_dm_mmc_ops = {
221 .send_cmd = meson_dm_mmc_send_cmd,
222 .set_ios = meson_dm_mmc_set_ios,
225 static int meson_mmc_ofdata_to_platdata(struct udevice *dev)
227 struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
230 addr = devfdt_get_addr(dev);
231 if (addr == FDT_ADDR_T_NONE)
234 pdata->regbase = (void *)addr;
239 static int meson_mmc_probe(struct udevice *dev)
241 struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
242 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
243 struct mmc *mmc = &pdata->mmc;
244 struct mmc_config *cfg = &pdata->cfg;
245 struct clk_bulk clocks;
250 struct udevice *pwr_dev;
253 /* Enable the clocks feeding the MMC controller */
254 ret = clk_get_bulk(dev, &clocks);
258 ret = clk_enable_bulk(&clocks);
262 cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 |
263 MMC_VDD_31_32 | MMC_VDD_165_195;
264 cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
265 MMC_MODE_HS_52MHz | MMC_MODE_HS;
266 cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
267 cfg->f_max = 100000000; /* 100 MHz */
268 cfg->b_max = 511; /* max 512 - 1 blocks */
269 cfg->name = dev->name;
274 mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE);
277 /* Enable power if needed */
278 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
281 ret = pwrseq_set_power(pwr_dev, true);
287 /* reset all status bits */
288 meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
290 /* disable interrupts */
291 meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN);
293 /* enable auto clock mode */
294 val = meson_read(mmc, MESON_SD_EMMC_CFG);
295 val &= ~CFG_SDCLK_ALWAYS_ON;
297 meson_write(mmc, val, MESON_SD_EMMC_CFG);
302 int meson_mmc_bind(struct udevice *dev)
304 struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
306 return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
309 static const struct udevice_id meson_mmc_match[] = {
310 { .compatible = "amlogic,meson-gx-mmc" },
311 { .compatible = "amlogic,meson-axg-mmc" },
315 U_BOOT_DRIVER(meson_mmc) = {
316 .name = "meson_gx_mmc",
318 .of_match = meson_mmc_match,
319 .ops = &meson_dm_mmc_ops,
320 .probe = meson_mmc_probe,
321 .bind = meson_mmc_bind,
322 .ofdata_to_platdata = meson_mmc_ofdata_to_platdata,
323 .platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata),
327 static int meson_mmc_pwrseq_set_power(struct udevice *dev, bool enable)
329 struct gpio_desc reset;
332 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
335 dm_gpio_set_value(&reset, 1);
337 dm_gpio_set_value(&reset, 0);
343 static const struct pwrseq_ops meson_mmc_pwrseq_ops = {
344 .set_power = meson_mmc_pwrseq_set_power,
347 static const struct udevice_id meson_mmc_pwrseq_ids[] = {
348 { .compatible = "mmc-pwrseq-emmc" },
352 U_BOOT_DRIVER(meson_mmc_pwrseq_drv) = {
353 .name = "mmc_pwrseq_emmc",
355 .of_match = meson_mmc_pwrseq_ids,
356 .ops = &meson_mmc_pwrseq_ops,