1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
14 #include <asm/arch/sd_emmc.h>
15 #include <linux/log2.h>
17 static inline void *get_regbase(const struct mmc *mmc)
19 struct meson_mmc_platdata *pdata = mmc->priv;
21 return pdata->regbase;
24 static inline uint32_t meson_read(struct mmc *mmc, int offset)
26 return readl(get_regbase(mmc) + offset);
29 static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
31 writel(val, get_regbase(mmc) + offset);
34 static void meson_mmc_config_clock(struct mmc *mmc)
36 uint32_t meson_mmc_clk = 0;
37 unsigned int clk, clk_src, clk_div;
42 /* 1GHz / CLK_MAX_DIV = 15,9 MHz */
43 if (mmc->clock > 16000000) {
44 clk = SD_EMMC_CLKSRC_DIV2;
45 clk_src = CLK_SRC_DIV2;
47 clk = SD_EMMC_CLKSRC_24M;
48 clk_src = CLK_SRC_24M;
50 clk_div = DIV_ROUND_UP(clk, mmc->clock);
52 /* 180 phase core clock */
53 meson_mmc_clk |= CLK_CO_PHASE_180;
55 /* 180 phase tx clock */
56 meson_mmc_clk |= CLK_TX_PHASE_000;
59 meson_mmc_clk |= clk_src;
60 meson_mmc_clk |= clk_div;
62 meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK);
65 static int meson_dm_mmc_set_ios(struct udevice *dev)
67 struct mmc *mmc = mmc_get_mmc_dev(dev);
68 uint32_t meson_mmc_cfg;
70 meson_mmc_config_clock(mmc);
72 meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
74 meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK;
75 if (mmc->bus_width == 1)
76 meson_mmc_cfg |= CFG_BUS_WIDTH_1;
77 else if (mmc->bus_width == 4)
78 meson_mmc_cfg |= CFG_BUS_WIDTH_4;
79 else if (mmc->bus_width == 8)
80 meson_mmc_cfg |= CFG_BUS_WIDTH_8;
84 /* 512 bytes block length */
85 meson_mmc_cfg &= ~CFG_BL_LEN_MASK;
86 meson_mmc_cfg |= CFG_BL_LEN_512;
88 /* Response timeout 256 clk */
89 meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK;
90 meson_mmc_cfg |= CFG_RESP_TIMEOUT_256;
92 /* Command-command gap 16 clk */
93 meson_mmc_cfg &= ~CFG_RC_CC_MASK;
94 meson_mmc_cfg |= CFG_RC_CC_16;
96 meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG);
101 static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data,
104 uint32_t meson_mmc_cmd = 0, cfg;
106 meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT;
108 if (cmd->resp_type & MMC_RSP_PRESENT) {
109 if (cmd->resp_type & MMC_RSP_136)
110 meson_mmc_cmd |= CMD_CFG_RESP_128;
112 if (cmd->resp_type & MMC_RSP_BUSY)
113 meson_mmc_cmd |= CMD_CFG_R1B;
115 if (!(cmd->resp_type & MMC_RSP_CRC))
116 meson_mmc_cmd |= CMD_CFG_RESP_NOCRC;
118 meson_mmc_cmd |= CMD_CFG_NO_RESP;
122 cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
123 cfg &= ~CFG_BL_LEN_MASK;
124 cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT;
125 meson_write(mmc, cfg, MESON_SD_EMMC_CFG);
127 if (data->flags == MMC_DATA_WRITE)
128 meson_mmc_cmd |= CMD_CFG_DATA_WR;
130 meson_mmc_cmd |= CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE |
134 meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER |
135 CMD_CFG_END_OF_CHAIN;
137 meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG);
140 static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
142 struct meson_mmc_platdata *pdata = mmc->priv;
143 unsigned int data_size;
144 uint32_t data_addr = 0;
147 data_size = data->blocks * data->blocksize;
149 if (data->flags == MMC_DATA_READ) {
150 data_addr = (ulong) data->dest;
151 invalidate_dcache_range(data_addr,
152 data_addr + data_size);
154 pdata->w_buf = calloc(data_size, sizeof(char));
155 data_addr = (ulong) pdata->w_buf;
156 memcpy(pdata->w_buf, data->src, data_size);
157 flush_dcache_range(data_addr, data_addr + data_size);
161 meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT);
164 static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd)
166 if (cmd->resp_type & MMC_RSP_136) {
167 cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3);
168 cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2);
169 cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1);
170 cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
172 cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
176 static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
177 struct mmc_data *data)
179 struct mmc *mmc = mmc_get_mmc_dev(dev);
180 struct meson_mmc_platdata *pdata = mmc->priv;
185 /* max block size supported by chip is 512 byte */
186 if (data && data->blocksize > 512)
189 meson_mmc_setup_cmd(mmc, data, cmd);
190 meson_mmc_setup_addr(mmc, data);
192 meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG);
194 /* use 10s timeout */
195 start = get_timer(0);
197 status = meson_read(mmc, MESON_SD_EMMC_STATUS);
198 } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000);
200 if (!(status & STATUS_END_OF_CHAIN))
202 else if (status & STATUS_RESP_TIMEOUT)
204 else if (status & STATUS_ERR_MASK)
207 meson_mmc_read_response(mmc, cmd);
209 if (data && data->flags == MMC_DATA_WRITE)
212 /* reset status bits */
213 meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
218 static const struct dm_mmc_ops meson_dm_mmc_ops = {
219 .send_cmd = meson_dm_mmc_send_cmd,
220 .set_ios = meson_dm_mmc_set_ios,
223 static int meson_mmc_ofdata_to_platdata(struct udevice *dev)
225 struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
228 addr = devfdt_get_addr(dev);
229 if (addr == FDT_ADDR_T_NONE)
232 pdata->regbase = (void *)addr;
237 static int meson_mmc_probe(struct udevice *dev)
239 struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
240 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
241 struct mmc *mmc = &pdata->mmc;
242 struct mmc_config *cfg = &pdata->cfg;
245 struct udevice *pwr_dev;
249 cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 |
250 MMC_VDD_31_32 | MMC_VDD_165_195;
251 cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
252 MMC_MODE_HS_52MHz | MMC_MODE_HS;
253 cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
254 cfg->f_max = 100000000; /* 100 MHz */
255 cfg->b_max = 511; /* max 512 - 1 blocks */
256 cfg->name = dev->name;
261 mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE);
264 /* Enable power if needed */
265 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
268 ret = pwrseq_set_power(pwr_dev, true);
274 /* reset all status bits */
275 meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
277 /* disable interrupts */
278 meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN);
280 /* enable auto clock mode */
281 val = meson_read(mmc, MESON_SD_EMMC_CFG);
282 val &= ~CFG_SDCLK_ALWAYS_ON;
284 meson_write(mmc, val, MESON_SD_EMMC_CFG);
289 int meson_mmc_bind(struct udevice *dev)
291 struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
293 return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
296 static const struct udevice_id meson_mmc_match[] = {
297 { .compatible = "amlogic,meson-gx-mmc" },
298 { .compatible = "amlogic,meson-axg-mmc" },
302 U_BOOT_DRIVER(meson_mmc) = {
303 .name = "meson_gx_mmc",
305 .of_match = meson_mmc_match,
306 .ops = &meson_dm_mmc_ops,
307 .probe = meson_mmc_probe,
308 .bind = meson_mmc_bind,
309 .ofdata_to_platdata = meson_mmc_ofdata_to_platdata,
310 .platdata_auto_alloc_size = sizeof(struct meson_mmc_platdata),
314 static int meson_mmc_pwrseq_set_power(struct udevice *dev, bool enable)
316 struct gpio_desc reset;
319 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
322 dm_gpio_set_value(&reset, 1);
324 dm_gpio_set_value(&reset, 0);
330 static const struct pwrseq_ops meson_mmc_pwrseq_ops = {
331 .set_power = meson_mmc_pwrseq_set_power,
334 static const struct udevice_id meson_mmc_pwrseq_ids[] = {
335 { .compatible = "mmc-pwrseq-emmc" },
339 U_BOOT_DRIVER(meson_mmc_pwrseq_drv) = {
340 .name = "mmc_pwrseq_emmc",
342 .of_match = meson_mmc_pwrseq_ids,
343 .ops = &meson_mmc_pwrseq_ops,