drivers/mmc/matsushita-common.c

   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <fdtdec.h>
  11 #include <mmc.h>
  12 #include <dm.h>
  13 #include <linux/compat.h>
  14 #include <linux/dma-direction.h>
  15 #include <linux/io.h>
  16 #include <linux/sizes.h>
  17 #include <power/regulator.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "matsushita-common.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 static u64 matsu_sd_readq(struct matsu_sd_priv *priv, unsigned int reg)
  25 {
  26         if (priv->caps & MATSU_SD_CAP_64BIT)
  27                 return readq(priv->regbase + (reg << 1));
  28         else
  29                 return readq(priv->regbase + reg);
  30 }
  31
  32 static void matsu_sd_writeq(struct matsu_sd_priv *priv,
  33                                u64 val, unsigned int reg)
  34 {
  35         if (priv->caps & MATSU_SD_CAP_64BIT)
  36                 writeq(val, priv->regbase + (reg << 1));
  37         else
  38                 writeq(val, priv->regbase + reg);
  39 }
  40
  41 static u32 matsu_sd_readl(struct matsu_sd_priv *priv, unsigned int reg)
  42 {
  43         if (priv->caps & MATSU_SD_CAP_64BIT)
  44                 return readl(priv->regbase + (reg << 1));
  45         else
  46                 return readl(priv->regbase + reg);
  47 }
  48
  49 static void matsu_sd_writel(struct matsu_sd_priv *priv,
  50                                u32 val, unsigned int reg)
  51 {
  52         if (priv->caps & MATSU_SD_CAP_64BIT)
  53                 writel(val, priv->regbase + (reg << 1));
  54         else
  55                 writel(val, priv->regbase + reg);
  56 }
  57
  58 static dma_addr_t __dma_map_single(void *ptr, size_t size,
  59                                    enum dma_data_direction dir)
  60 {
  61         unsigned long addr = (unsigned long)ptr;
  62
  63         if (dir == DMA_FROM_DEVICE)
  64                 invalidate_dcache_range(addr, addr + size);
  65         else
  66                 flush_dcache_range(addr, addr + size);
  67
  68         return addr;
  69 }
  70
  71 static void __dma_unmap_single(dma_addr_t addr, size_t size,
  72                                enum dma_data_direction dir)
  73 {
  74         if (dir != DMA_TO_DEVICE)
  75                 invalidate_dcache_range(addr, addr + size);
  76 }
  77
  78 static int matsu_sd_check_error(struct udevice *dev)
  79 {
  80         struct matsu_sd_priv *priv = dev_get_priv(dev);
  81         u32 info2 = matsu_sd_readl(priv, MATSU_SD_INFO2);
  82
  83         if (info2 & MATSU_SD_INFO2_ERR_RTO) {
  84                 /*
  85                  * TIMEOUT must be returned for unsupported command.  Do not
  86                  * display error log since this might be a part of sequence to
  87                  * distinguish between SD and MMC.
  88                  */
  89                 return -ETIMEDOUT;
  90         }
  91
  92         if (info2 & MATSU_SD_INFO2_ERR_TO) {
  93                 dev_err(dev, "timeout error\n");
  94                 return -ETIMEDOUT;
  95         }
  96
  97         if (info2 & (MATSU_SD_INFO2_ERR_END | MATSU_SD_INFO2_ERR_CRC |
  98                      MATSU_SD_INFO2_ERR_IDX)) {
  99                 dev_err(dev, "communication out of sync\n");
 100                 return -EILSEQ;
 101         }
 102
 103         if (info2 & (MATSU_SD_INFO2_ERR_ILA | MATSU_SD_INFO2_ERR_ILR |
 104                      MATSU_SD_INFO2_ERR_ILW)) {
 105                 dev_err(dev, "illegal access\n");
 106                 return -EIO;
 107         }
 108
 109         return 0;
 110 }
 111
 112 static int matsu_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
 113                                     u32 flag)
 114 {
 115         struct matsu_sd_priv *priv = dev_get_priv(dev);
 116         long wait = 1000000;
 117         int ret;
 118
 119         while (!(matsu_sd_readl(priv, reg) & flag)) {
 120                 if (wait-- < 0) {
 121                         dev_err(dev, "timeout\n");
 122                         return -ETIMEDOUT;
 123                 }
 124
 125                 ret = matsu_sd_check_error(dev);
 126                 if (ret)
 127                         return ret;
 128
 129                 udelay(1);
 130         }
 131
 132         return 0;
 133 }
 134
 135 #define matsu_pio_read_fifo(__width, __suffix)                          \
 136 static void matsu_pio_read_fifo_##__width(struct matsu_sd_priv *priv,   \
 137                                           char *pbuf, uint blksz)       \
 138 {                                                                       \
 139         u##__width *buf = (u##__width *)pbuf;                           \
 140         int i;                                                          \
 141                                                                         \
 142         if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) {      \
 143                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 144                         *buf++ = matsu_sd_read##__suffix(priv,          \
 145                                                          MATSU_SD_BUF); \
 146                 }                                                       \
 147         } else {                                                        \
 148                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 149                         u##__width data;                                \
 150                         data = matsu_sd_read##__suffix(priv,            \
 151                                                        MATSU_SD_BUF);   \
 152                         put_unaligned(data, buf++);                     \
 153                 }                                                       \
 154         }                                                               \
 155 }
 156
 157 matsu_pio_read_fifo(64, q)
 158 matsu_pio_read_fifo(32, l)
 159
 160 static int matsu_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
 161                                           uint blocksize)
 162 {
 163         struct matsu_sd_priv *priv = dev_get_priv(dev);
 164         int ret;
 165
 166         /* wait until the buffer is filled with data */
 167         ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
 168                                        MATSU_SD_INFO2_BRE);
 169         if (ret)
 170                 return ret;
 171
 172         /*
 173          * Clear the status flag _before_ read the buffer out because
 174          * MATSU_SD_INFO2_BRE is edge-triggered, not level-triggered.
 175          */
 176         matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
 177
 178         if (priv->caps & MATSU_SD_CAP_64BIT)
 179                 matsu_pio_read_fifo_64(priv, pbuf, blocksize);
 180         else
 181                 matsu_pio_read_fifo_32(priv, pbuf, blocksize);
 182
 183         return 0;
 184 }
 185
 186 #define matsu_pio_write_fifo(__width, __suffix)                         \
 187 static void matsu_pio_write_fifo_##__width(struct matsu_sd_priv *priv,  \
 188                                            const char *pbuf, uint blksz)\
 189 {                                                                       \
 190         const u##__width *buf = (const u##__width *)pbuf;               \
 191         int i;                                                          \
 192                                                                         \
 193         if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) {      \
 194                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 195                         matsu_sd_write##__suffix(priv, *buf++,          \
 196                                                  MATSU_SD_BUF);         \
 197                 }                                                       \
 198         } else {                                                        \
 199                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 200                         u##__width data = get_unaligned(buf++);         \
 201                         matsu_sd_write##__suffix(priv, data,            \
 202                                                  MATSU_SD_BUF);         \
 203                 }                                                       \
 204         }                                                               \
 205 }
 206
 207 matsu_pio_write_fifo(64, q)
 208 matsu_pio_write_fifo(32, l)
 209
 210 static int matsu_sd_pio_write_one_block(struct udevice *dev,
 211                                            const char *pbuf, uint blocksize)
 212 {
 213         struct matsu_sd_priv *priv = dev_get_priv(dev);
 214         int ret;
 215
 216         /* wait until the buffer becomes empty */
 217         ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
 218                                     MATSU_SD_INFO2_BWE);
 219         if (ret)
 220                 return ret;
 221
 222         matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
 223
 224         if (priv->caps & MATSU_SD_CAP_64BIT)
 225                 matsu_pio_write_fifo_64(priv, pbuf, blocksize);
 226         else
 227                 matsu_pio_write_fifo_32(priv, pbuf, blocksize);
 228
 229         return 0;
 230 }
 231
 232 static int matsu_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
 233 {
 234         const char *src = data->src;
 235         char *dest = data->dest;
 236         int i, ret;
 237
 238         for (i = 0; i < data->blocks; i++) {
 239                 if (data->flags & MMC_DATA_READ)
 240                         ret = matsu_sd_pio_read_one_block(dev, dest,
 241                                                              data->blocksize);
 242                 else
 243                         ret = matsu_sd_pio_write_one_block(dev, src,
 244                                                               data->blocksize);
 245                 if (ret)
 246                         return ret;
 247
 248                 if (data->flags & MMC_DATA_READ)
 249                         dest += data->blocksize;
 250                 else
 251                         src += data->blocksize;
 252         }
 253
 254         return 0;
 255 }
 256
 257 static void matsu_sd_dma_start(struct matsu_sd_priv *priv,
 258                                   dma_addr_t dma_addr)
 259 {
 260         u32 tmp;
 261
 262         matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO1);
 263         matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO2);
 264
 265         /* enable DMA */
 266         tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
 267         tmp |= MATSU_SD_EXTMODE_DMA_EN;
 268         matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
 269
 270         matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_L);
 271
 272         /* suppress the warning "right shift count >= width of type" */
 273         dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
 274
 275         matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_H);
 276
 277         matsu_sd_writel(priv, MATSU_SD_DMA_CTL_START, MATSU_SD_DMA_CTL);
 278 }
 279
 280 static int matsu_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
 281                                         unsigned int blocks)
 282 {
 283         struct matsu_sd_priv *priv = dev_get_priv(dev);
 284         long wait = 1000000 + 10 * blocks;
 285
 286         while (!(matsu_sd_readl(priv, MATSU_SD_DMA_INFO1) & flag)) {
 287                 if (wait-- < 0) {
 288                         dev_err(dev, "timeout during DMA\n");
 289                         return -ETIMEDOUT;
 290                 }
 291
 292                 udelay(10);
 293         }
 294
 295         if (matsu_sd_readl(priv, MATSU_SD_DMA_INFO2)) {
 296                 dev_err(dev, "error during DMA\n");
 297                 return -EIO;
 298         }
 299
 300         return 0;
 301 }
 302
 303 static int matsu_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
 304 {
 305         struct matsu_sd_priv *priv = dev_get_priv(dev);
 306         size_t len = data->blocks * data->blocksize;
 307         void *buf;
 308         enum dma_data_direction dir;
 309         dma_addr_t dma_addr;
 310         u32 poll_flag, tmp;
 311         int ret;
 312
 313         tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
 314
 315         if (data->flags & MMC_DATA_READ) {
 316                 buf = data->dest;
 317                 dir = DMA_FROM_DEVICE;
 318                 poll_flag = MATSU_SD_DMA_INFO1_END_RD2;
 319                 tmp |= MATSU_SD_DMA_MODE_DIR_RD;
 320         } else {
 321                 buf = (void *)data->src;
 322                 dir = DMA_TO_DEVICE;
 323                 poll_flag = MATSU_SD_DMA_INFO1_END_WR;
 324                 tmp &= ~MATSU_SD_DMA_MODE_DIR_RD;
 325         }
 326
 327         matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
 328
 329         dma_addr = __dma_map_single(buf, len, dir);
 330
 331         matsu_sd_dma_start(priv, dma_addr);
 332
 333         ret = matsu_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
 334
 335         __dma_unmap_single(dma_addr, len, dir);
 336
 337         return ret;
 338 }
 339
 340 /* check if the address is DMA'able */
 341 static bool matsu_sd_addr_is_dmaable(unsigned long addr)
 342 {
 343         if (!IS_ALIGNED(addr, MATSU_SD_DMA_MINALIGN))
 344                 return false;
 345
 346 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
 347         defined(CONFIG_SPL_BUILD)
 348         /*
 349          * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
 350          * of L2, which is unreachable from the DMA engine.
 351          */
 352         if (addr < CONFIG_SPL_STACK)
 353                 return false;
 354 #endif
 355
 356         return true;
 357 }
 358
 359 int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 360                       struct mmc_data *data)
 361 {
 362         struct matsu_sd_priv *priv = dev_get_priv(dev);
 363         int ret;
 364         u32 tmp;
 365
 366         if (matsu_sd_readl(priv, MATSU_SD_INFO2) & MATSU_SD_INFO2_CBSY) {
 367                 dev_err(dev, "command busy\n");
 368                 return -EBUSY;
 369         }
 370
 371         /* clear all status flags */
 372         matsu_sd_writel(priv, 0, MATSU_SD_INFO1);
 373         matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
 374
 375         /* disable DMA once */
 376         tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
 377         tmp &= ~MATSU_SD_EXTMODE_DMA_EN;
 378         matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
 379
 380         matsu_sd_writel(priv, cmd->cmdarg, MATSU_SD_ARG);
 381
 382         tmp = cmd->cmdidx;
 383
 384         if (data) {
 385                 matsu_sd_writel(priv, data->blocksize, MATSU_SD_SIZE);
 386                 matsu_sd_writel(priv, data->blocks, MATSU_SD_SECCNT);
 387
 388                 /* Do not send CMD12 automatically */
 389                 tmp |= MATSU_SD_CMD_NOSTOP | MATSU_SD_CMD_DATA;
 390
 391                 if (data->blocks > 1)
 392                         tmp |= MATSU_SD_CMD_MULTI;
 393
 394                 if (data->flags & MMC_DATA_READ)
 395                         tmp |= MATSU_SD_CMD_RD;
 396         }
 397
 398         /*
 399          * Do not use the response type auto-detection on this hardware.
 400          * CMD8, for example, has different response types on SD and eMMC,
 401          * while this controller always assumes the response type for SD.
 402          * Set the response type manually.
 403          */
 404         switch (cmd->resp_type) {
 405         case MMC_RSP_NONE:
 406                 tmp |= MATSU_SD_CMD_RSP_NONE;
 407                 break;
 408         case MMC_RSP_R1:
 409                 tmp |= MATSU_SD_CMD_RSP_R1;
 410                 break;
 411         case MMC_RSP_R1b:
 412                 tmp |= MATSU_SD_CMD_RSP_R1B;
 413                 break;
 414         case MMC_RSP_R2:
 415                 tmp |= MATSU_SD_CMD_RSP_R2;
 416                 break;
 417         case MMC_RSP_R3:
 418                 tmp |= MATSU_SD_CMD_RSP_R3;
 419                 break;
 420         default:
 421                 dev_err(dev, "unknown response type\n");
 422                 return -EINVAL;
 423         }
 424
 425         dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
 426                 cmd->cmdidx, tmp, cmd->cmdarg);
 427         matsu_sd_writel(priv, tmp, MATSU_SD_CMD);
 428
 429         ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
 430                                        MATSU_SD_INFO1_RSP);
 431         if (ret)
 432                 return ret;
 433
 434         if (cmd->resp_type & MMC_RSP_136) {
 435                 u32 rsp_127_104 = matsu_sd_readl(priv, MATSU_SD_RSP76);
 436                 u32 rsp_103_72 = matsu_sd_readl(priv, MATSU_SD_RSP54);
 437                 u32 rsp_71_40 = matsu_sd_readl(priv, MATSU_SD_RSP32);
 438                 u32 rsp_39_8 = matsu_sd_readl(priv, MATSU_SD_RSP10);
 439
 440                 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
 441                                    ((rsp_103_72  & 0xff000000) >> 24);
 442                 cmd->response[1] = ((rsp_103_72  & 0x00ffffff) << 8) |
 443                                    ((rsp_71_40   & 0xff000000) >> 24);
 444                 cmd->response[2] = ((rsp_71_40   & 0x00ffffff) << 8) |
 445                                    ((rsp_39_8    & 0xff000000) >> 24);
 446                 cmd->response[3] = (rsp_39_8     & 0xffffff)   << 8;
 447         } else {
 448                 /* bit 39-8 */
 449                 cmd->response[0] = matsu_sd_readl(priv, MATSU_SD_RSP10);
 450         }
 451
 452         if (data) {
 453                 /* use DMA if the HW supports it and the buffer is aligned */
 454                 if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL &&
 455                     matsu_sd_addr_is_dmaable((long)data->src))
 456                         ret = matsu_sd_dma_xfer(dev, data);
 457                 else
 458                         ret = matsu_sd_pio_xfer(dev, data);
 459
 460                 ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
 461                                                MATSU_SD_INFO1_CMP);
 462                 if (ret)
 463                         return ret;
 464         }
 465
 466         return ret;
 467 }
 468
 469 static int matsu_sd_set_bus_width(struct matsu_sd_priv *priv,
 470                                      struct mmc *mmc)
 471 {
 472         u32 val, tmp;
 473
 474         switch (mmc->bus_width) {
 475         case 1:
 476                 val = MATSU_SD_OPTION_WIDTH_1;
 477                 break;
 478         case 4:
 479                 val = MATSU_SD_OPTION_WIDTH_4;
 480                 break;
 481         case 8:
 482                 val = MATSU_SD_OPTION_WIDTH_8;
 483                 break;
 484         default:
 485                 return -EINVAL;
 486         }
 487
 488         tmp = matsu_sd_readl(priv, MATSU_SD_OPTION);
 489         tmp &= ~MATSU_SD_OPTION_WIDTH_MASK;
 490         tmp |= val;
 491         matsu_sd_writel(priv, tmp, MATSU_SD_OPTION);
 492
 493         return 0;
 494 }
 495
 496 static void matsu_sd_set_ddr_mode(struct matsu_sd_priv *priv,
 497                                      struct mmc *mmc)
 498 {
 499         u32 tmp;
 500
 501         tmp = matsu_sd_readl(priv, MATSU_SD_IF_MODE);
 502         if (mmc->ddr_mode)
 503                 tmp |= MATSU_SD_IF_MODE_DDR;
 504         else
 505                 tmp &= ~MATSU_SD_IF_MODE_DDR;
 506         matsu_sd_writel(priv, tmp, MATSU_SD_IF_MODE);
 507 }
 508
 509 static void matsu_sd_set_clk_rate(struct matsu_sd_priv *priv,
 510                                      struct mmc *mmc)
 511 {
 512         unsigned int divisor;
 513         u32 val, tmp;
 514
 515         if (!mmc->clock)
 516                 return;
 517
 518         divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
 519
 520         if (divisor <= 1)
 521                 val = MATSU_SD_CLKCTL_DIV1;
 522         else if (divisor <= 2)
 523                 val = MATSU_SD_CLKCTL_DIV2;
 524         else if (divisor <= 4)
 525                 val = MATSU_SD_CLKCTL_DIV4;
 526         else if (divisor <= 8)
 527                 val = MATSU_SD_CLKCTL_DIV8;
 528         else if (divisor <= 16)
 529                 val = MATSU_SD_CLKCTL_DIV16;
 530         else if (divisor <= 32)
 531                 val = MATSU_SD_CLKCTL_DIV32;
 532         else if (divisor <= 64)
 533                 val = MATSU_SD_CLKCTL_DIV64;
 534         else if (divisor <= 128)
 535                 val = MATSU_SD_CLKCTL_DIV128;
 536         else if (divisor <= 256)
 537                 val = MATSU_SD_CLKCTL_DIV256;
 538         else if (divisor <= 512 || !(priv->caps & MATSU_SD_CAP_DIV1024))
 539                 val = MATSU_SD_CLKCTL_DIV512;
 540         else
 541                 val = MATSU_SD_CLKCTL_DIV1024;
 542
 543         tmp = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
 544         if (tmp & MATSU_SD_CLKCTL_SCLKEN &&
 545             (tmp & MATSU_SD_CLKCTL_DIV_MASK) == val)
 546                 return;
 547
 548         /* stop the clock before changing its rate to avoid a glitch signal */
 549         tmp &= ~MATSU_SD_CLKCTL_SCLKEN;
 550         matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
 551
 552         tmp &= ~MATSU_SD_CLKCTL_DIV_MASK;
 553         tmp |= val | MATSU_SD_CLKCTL_OFFEN;
 554         matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
 555
 556         tmp |= MATSU_SD_CLKCTL_SCLKEN;
 557         matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
 558
 559         udelay(1000);
 560 }
 561
 562 int matsu_sd_set_ios(struct udevice *dev)
 563 {
 564         struct matsu_sd_priv *priv = dev_get_priv(dev);
 565         struct mmc *mmc = mmc_get_mmc_dev(dev);
 566         int ret;
 567
 568         dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
 569                 mmc->clock, mmc->ddr_mode, mmc->bus_width);
 570
 571         ret = matsu_sd_set_bus_width(priv, mmc);
 572         if (ret)
 573                 return ret;
 574         matsu_sd_set_ddr_mode(priv, mmc);
 575         matsu_sd_set_clk_rate(priv, mmc);
 576
 577         return 0;
 578 }
 579
 580 int matsu_sd_get_cd(struct udevice *dev)
 581 {
 582         struct matsu_sd_priv *priv = dev_get_priv(dev);
 583
 584         if (priv->caps & MATSU_SD_CAP_NONREMOVABLE)
 585                 return 1;
 586
 587         return !!(matsu_sd_readl(priv, MATSU_SD_INFO1) &
 588                   MATSU_SD_INFO1_CD);
 589 }
 590
 591 static void matsu_sd_host_init(struct matsu_sd_priv *priv)
 592 {
 593         u32 tmp;
 594
 595         /* soft reset of the host */
 596         tmp = matsu_sd_readl(priv, MATSU_SD_SOFT_RST);
 597         tmp &= ~MATSU_SD_SOFT_RST_RSTX;
 598         matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
 599         tmp |= MATSU_SD_SOFT_RST_RSTX;
 600         matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
 601
 602         /* FIXME: implement eMMC hw_reset */
 603
 604         matsu_sd_writel(priv, MATSU_SD_STOP_SEC, MATSU_SD_STOP);
 605
 606         /*
 607          * Connected to 32bit AXI.
 608          * This register dropped backward compatibility at version 0x10.
 609          * Write an appropriate value depending on the IP version.
 610          */
 611         matsu_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000,
 612                            MATSU_SD_HOST_MODE);
 613
 614         if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL) {
 615                 tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
 616                 tmp |= MATSU_SD_DMA_MODE_ADDR_INC;
 617                 matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
 618         }
 619 }
 620
 621 int matsu_sd_bind(struct udevice *dev)
 622 {
 623         struct matsu_sd_plat *plat = dev_get_platdata(dev);
 624
 625         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 626 }
 627
 628 int matsu_sd_probe(struct udevice *dev)
 629 {
 630         struct matsu_sd_plat *plat = dev_get_platdata(dev);
 631         struct matsu_sd_priv *priv = dev_get_priv(dev);
 632         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 633         const u32 quirks = dev_get_driver_data(dev);
 634         fdt_addr_t base;
 635         struct clk clk;
 636         int ret;
 637 #ifdef CONFIG_DM_REGULATOR
 638         struct udevice *vqmmc_dev;
 639 #endif
 640
 641         base = devfdt_get_addr(dev);
 642         if (base == FDT_ADDR_T_NONE)
 643                 return -EINVAL;
 644
 645         priv->regbase = devm_ioremap(dev, base, SZ_2K);
 646         if (!priv->regbase)
 647                 return -ENOMEM;
 648
 649 #ifdef CONFIG_DM_REGULATOR
 650         ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
 651         if (!ret) {
 652                 /* Set the regulator to 3.3V until we support 1.8V modes */
 653                 regulator_set_value(vqmmc_dev, 3300000);
 654                 regulator_set_enable(vqmmc_dev, true);
 655         }
 656 #endif
 657
 658         ret = clk_get_by_index(dev, 0, &clk);
 659         if (ret < 0) {
 660                 dev_err(dev, "failed to get host clock\n");
 661                 return ret;
 662         }
 663
 664         /* set to max rate */
 665         priv->mclk = clk_set_rate(&clk, ULONG_MAX);
 666         if (IS_ERR_VALUE(priv->mclk)) {
 667                 dev_err(dev, "failed to set rate for host clock\n");
 668                 clk_free(&clk);
 669                 return priv->mclk;
 670         }
 671
 672         ret = clk_enable(&clk);
 673         clk_free(&clk);
 674         if (ret) {
 675                 dev_err(dev, "failed to enable host clock\n");
 676                 return ret;
 677         }
 678
 679         plat->cfg.name = dev->name;
 680         plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
 681
 682         switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
 683                                1)) {
 684         case 8:
 685                 plat->cfg.host_caps |= MMC_MODE_8BIT;
 686                 break;
 687         case 4:
 688                 plat->cfg.host_caps |= MMC_MODE_4BIT;
 689                 break;
 690         case 1:
 691                 break;
 692         default:
 693                 dev_err(dev, "Invalid \"bus-width\" value\n");
 694                 return -EINVAL;
 695         }
 696
 697         if (quirks) {
 698                 priv->caps = quirks;
 699         } else {
 700                 priv->version = matsu_sd_readl(priv, MATSU_SD_VERSION) &
 701                                                         MATSU_SD_VERSION_IP;
 702                 dev_dbg(dev, "version %x\n", priv->version);
 703                 if (priv->version >= 0x10) {
 704                         priv->caps |= MATSU_SD_CAP_DMA_INTERNAL;
 705                         priv->caps |= MATSU_SD_CAP_DIV1024;
 706                 }
 707         }
 708
 709         if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
 710                              NULL))
 711                 priv->caps |= MATSU_SD_CAP_NONREMOVABLE;
 712
 713         matsu_sd_host_init(priv);
 714
 715         plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
 716         plat->cfg.f_min = priv->mclk /
 717                         (priv->caps & MATSU_SD_CAP_DIV1024 ? 1024 : 512);
 718         plat->cfg.f_max = priv->mclk;
 719         plat->cfg.b_max = U32_MAX; /* max value of MATSU_SD_SECCNT */
 720
 721         upriv->mmc = &plat->mmc;
 722
 723         return 0;
 724 }