drivers/mmc/matsushita-common.c

   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <fdtdec.h>
  11 #include <mmc.h>
  12 #include <dm.h>
  13 #include <linux/compat.h>
  14 #include <linux/dma-direction.h>
  15 #include <linux/io.h>
  16 #include <linux/sizes.h>
  17 #include <power/regulator.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "matsushita-common.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 static u64 matsu_sd_readq(struct matsu_sd_priv *priv, unsigned int reg)
  25 {
  26         return readq(priv->regbase + (reg << 1));
  27 }
  28
  29 static void matsu_sd_writeq(struct matsu_sd_priv *priv,
  30                                u64 val, unsigned int reg)
  31 {
  32         writeq(val, priv->regbase + (reg << 1));
  33 }
  34
  35 static u32 matsu_sd_readl(struct matsu_sd_priv *priv, unsigned int reg)
  36 {
  37         if (priv->caps & MATSU_SD_CAP_64BIT)
  38                 return readl(priv->regbase + (reg << 1));
  39         else
  40                 return readl(priv->regbase + reg);
  41 }
  42
  43 static void matsu_sd_writel(struct matsu_sd_priv *priv,
  44                                u32 val, unsigned int reg)
  45 {
  46         if (priv->caps & MATSU_SD_CAP_64BIT)
  47                 writel(val, priv->regbase + (reg << 1));
  48         else
  49                 writel(val, priv->regbase + reg);
  50 }
  51
  52 static dma_addr_t __dma_map_single(void *ptr, size_t size,
  53                                    enum dma_data_direction dir)
  54 {
  55         unsigned long addr = (unsigned long)ptr;
  56
  57         if (dir == DMA_FROM_DEVICE)
  58                 invalidate_dcache_range(addr, addr + size);
  59         else
  60                 flush_dcache_range(addr, addr + size);
  61
  62         return addr;
  63 }
  64
  65 static void __dma_unmap_single(dma_addr_t addr, size_t size,
  66                                enum dma_data_direction dir)
  67 {
  68         if (dir != DMA_TO_DEVICE)
  69                 invalidate_dcache_range(addr, addr + size);
  70 }
  71
  72 static int matsu_sd_check_error(struct udevice *dev)
  73 {
  74         struct matsu_sd_priv *priv = dev_get_priv(dev);
  75         u32 info2 = matsu_sd_readl(priv, MATSU_SD_INFO2);
  76
  77         if (info2 & MATSU_SD_INFO2_ERR_RTO) {
  78                 /*
  79                  * TIMEOUT must be returned for unsupported command.  Do not
  80                  * display error log since this might be a part of sequence to
  81                  * distinguish between SD and MMC.
  82                  */
  83                 return -ETIMEDOUT;
  84         }
  85
  86         if (info2 & MATSU_SD_INFO2_ERR_TO) {
  87                 dev_err(dev, "timeout error\n");
  88                 return -ETIMEDOUT;
  89         }
  90
  91         if (info2 & (MATSU_SD_INFO2_ERR_END | MATSU_SD_INFO2_ERR_CRC |
  92                      MATSU_SD_INFO2_ERR_IDX)) {
  93                 dev_err(dev, "communication out of sync\n");
  94                 return -EILSEQ;
  95         }
  96
  97         if (info2 & (MATSU_SD_INFO2_ERR_ILA | MATSU_SD_INFO2_ERR_ILR |
  98                      MATSU_SD_INFO2_ERR_ILW)) {
  99                 dev_err(dev, "illegal access\n");
 100                 return -EIO;
 101         }
 102
 103         return 0;
 104 }
 105
 106 static int matsu_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
 107                                     u32 flag)
 108 {
 109         struct matsu_sd_priv *priv = dev_get_priv(dev);
 110         long wait = 1000000;
 111         int ret;
 112
 113         while (!(matsu_sd_readl(priv, reg) & flag)) {
 114                 if (wait-- < 0) {
 115                         dev_err(dev, "timeout\n");
 116                         return -ETIMEDOUT;
 117                 }
 118
 119                 ret = matsu_sd_check_error(dev);
 120                 if (ret)
 121                         return ret;
 122
 123                 udelay(1);
 124         }
 125
 126         return 0;
 127 }
 128
 129 #define matsu_pio_read_fifo(__width, __suffix)                          \
 130 static void matsu_pio_read_fifo_##__width(struct matsu_sd_priv *priv,   \
 131                                           char *pbuf, uint blksz)       \
 132 {                                                                       \
 133         u##__width *buf = (u##__width *)pbuf;                           \
 134         int i;                                                          \
 135                                                                         \
 136         if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) {      \
 137                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 138                         *buf++ = matsu_sd_read##__suffix(priv,          \
 139                                                          MATSU_SD_BUF); \
 140                 }                                                       \
 141         } else {                                                        \
 142                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 143                         u##__width data;                                \
 144                         data = matsu_sd_read##__suffix(priv,            \
 145                                                        MATSU_SD_BUF);   \
 146                         put_unaligned(data, buf++);                     \
 147                 }                                                       \
 148         }                                                               \
 149 }
 150
 151 matsu_pio_read_fifo(64, q)
 152 matsu_pio_read_fifo(32, l)
 153
 154 static int matsu_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
 155                                           uint blocksize)
 156 {
 157         struct matsu_sd_priv *priv = dev_get_priv(dev);
 158         int ret;
 159
 160         /* wait until the buffer is filled with data */
 161         ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
 162                                        MATSU_SD_INFO2_BRE);
 163         if (ret)
 164                 return ret;
 165
 166         /*
 167          * Clear the status flag _before_ read the buffer out because
 168          * MATSU_SD_INFO2_BRE is edge-triggered, not level-triggered.
 169          */
 170         matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
 171
 172         if (priv->caps & MATSU_SD_CAP_64BIT)
 173                 matsu_pio_read_fifo_64(priv, pbuf, blocksize);
 174         else
 175                 matsu_pio_read_fifo_32(priv, pbuf, blocksize);
 176
 177         return 0;
 178 }
 179
 180 #define matsu_pio_write_fifo(__width, __suffix)                         \
 181 static void matsu_pio_write_fifo_##__width(struct matsu_sd_priv *priv,  \
 182                                            const char *pbuf, uint blksz)\
 183 {                                                                       \
 184         const u##__width *buf = (const u##__width *)pbuf;               \
 185         int i;                                                          \
 186                                                                         \
 187         if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) {      \
 188                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 189                         matsu_sd_write##__suffix(priv, *buf++,          \
 190                                                  MATSU_SD_BUF);         \
 191                 }                                                       \
 192         } else {                                                        \
 193                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 194                         u##__width data = get_unaligned(buf++);         \
 195                         matsu_sd_write##__suffix(priv, data,            \
 196                                                  MATSU_SD_BUF);         \
 197                 }                                                       \
 198         }                                                               \
 199 }
 200
 201 matsu_pio_write_fifo(64, q)
 202 matsu_pio_write_fifo(32, l)
 203
 204 static int matsu_sd_pio_write_one_block(struct udevice *dev,
 205                                            const char *pbuf, uint blocksize)
 206 {
 207         struct matsu_sd_priv *priv = dev_get_priv(dev);
 208         int ret;
 209
 210         /* wait until the buffer becomes empty */
 211         ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
 212                                     MATSU_SD_INFO2_BWE);
 213         if (ret)
 214                 return ret;
 215
 216         matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
 217
 218         if (priv->caps & MATSU_SD_CAP_64BIT)
 219                 matsu_pio_write_fifo_64(priv, pbuf, blocksize);
 220         else
 221                 matsu_pio_write_fifo_32(priv, pbuf, blocksize);
 222
 223         return 0;
 224 }
 225
 226 static int matsu_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
 227 {
 228         const char *src = data->src;
 229         char *dest = data->dest;
 230         int i, ret;
 231
 232         for (i = 0; i < data->blocks; i++) {
 233                 if (data->flags & MMC_DATA_READ)
 234                         ret = matsu_sd_pio_read_one_block(dev, dest,
 235                                                              data->blocksize);
 236                 else
 237                         ret = matsu_sd_pio_write_one_block(dev, src,
 238                                                               data->blocksize);
 239                 if (ret)
 240                         return ret;
 241
 242                 if (data->flags & MMC_DATA_READ)
 243                         dest += data->blocksize;
 244                 else
 245                         src += data->blocksize;
 246         }
 247
 248         return 0;
 249 }
 250
 251 static void matsu_sd_dma_start(struct matsu_sd_priv *priv,
 252                                   dma_addr_t dma_addr)
 253 {
 254         u32 tmp;
 255
 256         matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO1);
 257         matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO2);
 258
 259         /* enable DMA */
 260         tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
 261         tmp |= MATSU_SD_EXTMODE_DMA_EN;
 262         matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
 263
 264         matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_L);
 265
 266         /* suppress the warning "right shift count >= width of type" */
 267         dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
 268
 269         matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_H);
 270
 271         matsu_sd_writel(priv, MATSU_SD_DMA_CTL_START, MATSU_SD_DMA_CTL);
 272 }
 273
 274 static int matsu_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
 275                                         unsigned int blocks)
 276 {
 277         struct matsu_sd_priv *priv = dev_get_priv(dev);
 278         long wait = 1000000 + 10 * blocks;
 279
 280         while (!(matsu_sd_readl(priv, MATSU_SD_DMA_INFO1) & flag)) {
 281                 if (wait-- < 0) {
 282                         dev_err(dev, "timeout during DMA\n");
 283                         return -ETIMEDOUT;
 284                 }
 285
 286                 udelay(10);
 287         }
 288
 289         if (matsu_sd_readl(priv, MATSU_SD_DMA_INFO2)) {
 290                 dev_err(dev, "error during DMA\n");
 291                 return -EIO;
 292         }
 293
 294         return 0;
 295 }
 296
 297 static int matsu_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
 298 {
 299         struct matsu_sd_priv *priv = dev_get_priv(dev);
 300         size_t len = data->blocks * data->blocksize;
 301         void *buf;
 302         enum dma_data_direction dir;
 303         dma_addr_t dma_addr;
 304         u32 poll_flag, tmp;
 305         int ret;
 306
 307         tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
 308
 309         if (data->flags & MMC_DATA_READ) {
 310                 buf = data->dest;
 311                 dir = DMA_FROM_DEVICE;
 312                 poll_flag = MATSU_SD_DMA_INFO1_END_RD2;
 313                 tmp |= MATSU_SD_DMA_MODE_DIR_RD;
 314         } else {
 315                 buf = (void *)data->src;
 316                 dir = DMA_TO_DEVICE;
 317                 poll_flag = MATSU_SD_DMA_INFO1_END_WR;
 318                 tmp &= ~MATSU_SD_DMA_MODE_DIR_RD;
 319         }
 320
 321         matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
 322
 323         dma_addr = __dma_map_single(buf, len, dir);
 324
 325         matsu_sd_dma_start(priv, dma_addr);
 326
 327         ret = matsu_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
 328
 329         __dma_unmap_single(dma_addr, len, dir);
 330
 331         return ret;
 332 }
 333
 334 /* check if the address is DMA'able */
 335 static bool matsu_sd_addr_is_dmaable(unsigned long addr)
 336 {
 337         if (!IS_ALIGNED(addr, MATSU_SD_DMA_MINALIGN))
 338                 return false;
 339
 340 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
 341         defined(CONFIG_SPL_BUILD)
 342         /*
 343          * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
 344          * of L2, which is unreachable from the DMA engine.
 345          */
 346         if (addr < CONFIG_SPL_STACK)
 347                 return false;
 348 #endif
 349
 350         return true;
 351 }
 352
 353 int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 354                       struct mmc_data *data)
 355 {
 356         struct matsu_sd_priv *priv = dev_get_priv(dev);
 357         int ret;
 358         u32 tmp;
 359
 360         if (matsu_sd_readl(priv, MATSU_SD_INFO2) & MATSU_SD_INFO2_CBSY) {
 361                 dev_err(dev, "command busy\n");
 362                 return -EBUSY;
 363         }
 364
 365         /* clear all status flags */
 366         matsu_sd_writel(priv, 0, MATSU_SD_INFO1);
 367         matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
 368
 369         /* disable DMA once */
 370         tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
 371         tmp &= ~MATSU_SD_EXTMODE_DMA_EN;
 372         matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
 373
 374         matsu_sd_writel(priv, cmd->cmdarg, MATSU_SD_ARG);
 375
 376         tmp = cmd->cmdidx;
 377
 378         if (data) {
 379                 matsu_sd_writel(priv, data->blocksize, MATSU_SD_SIZE);
 380                 matsu_sd_writel(priv, data->blocks, MATSU_SD_SECCNT);
 381
 382                 /* Do not send CMD12 automatically */
 383                 tmp |= MATSU_SD_CMD_NOSTOP | MATSU_SD_CMD_DATA;
 384
 385                 if (data->blocks > 1)
 386                         tmp |= MATSU_SD_CMD_MULTI;
 387
 388                 if (data->flags & MMC_DATA_READ)
 389                         tmp |= MATSU_SD_CMD_RD;
 390         }
 391
 392         /*
 393          * Do not use the response type auto-detection on this hardware.
 394          * CMD8, for example, has different response types on SD and eMMC,
 395          * while this controller always assumes the response type for SD.
 396          * Set the response type manually.
 397          */
 398         switch (cmd->resp_type) {
 399         case MMC_RSP_NONE:
 400                 tmp |= MATSU_SD_CMD_RSP_NONE;
 401                 break;
 402         case MMC_RSP_R1:
 403                 tmp |= MATSU_SD_CMD_RSP_R1;
 404                 break;
 405         case MMC_RSP_R1b:
 406                 tmp |= MATSU_SD_CMD_RSP_R1B;
 407                 break;
 408         case MMC_RSP_R2:
 409                 tmp |= MATSU_SD_CMD_RSP_R2;
 410                 break;
 411         case MMC_RSP_R3:
 412                 tmp |= MATSU_SD_CMD_RSP_R3;
 413                 break;
 414         default:
 415                 dev_err(dev, "unknown response type\n");
 416                 return -EINVAL;
 417         }
 418
 419         dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
 420                 cmd->cmdidx, tmp, cmd->cmdarg);
 421         matsu_sd_writel(priv, tmp, MATSU_SD_CMD);
 422
 423         ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
 424                                        MATSU_SD_INFO1_RSP);
 425         if (ret)
 426                 return ret;
 427
 428         if (cmd->resp_type & MMC_RSP_136) {
 429                 u32 rsp_127_104 = matsu_sd_readl(priv, MATSU_SD_RSP76);
 430                 u32 rsp_103_72 = matsu_sd_readl(priv, MATSU_SD_RSP54);
 431                 u32 rsp_71_40 = matsu_sd_readl(priv, MATSU_SD_RSP32);
 432                 u32 rsp_39_8 = matsu_sd_readl(priv, MATSU_SD_RSP10);
 433
 434                 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
 435                                    ((rsp_103_72  & 0xff000000) >> 24);
 436                 cmd->response[1] = ((rsp_103_72  & 0x00ffffff) << 8) |
 437                                    ((rsp_71_40   & 0xff000000) >> 24);
 438                 cmd->response[2] = ((rsp_71_40   & 0x00ffffff) << 8) |
 439                                    ((rsp_39_8    & 0xff000000) >> 24);
 440                 cmd->response[3] = (rsp_39_8     & 0xffffff)   << 8;
 441         } else {
 442                 /* bit 39-8 */
 443                 cmd->response[0] = matsu_sd_readl(priv, MATSU_SD_RSP10);
 444         }
 445
 446         if (data) {
 447                 /* use DMA if the HW supports it and the buffer is aligned */
 448                 if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL &&
 449                     matsu_sd_addr_is_dmaable((long)data->src))
 450                         ret = matsu_sd_dma_xfer(dev, data);
 451                 else
 452                         ret = matsu_sd_pio_xfer(dev, data);
 453
 454                 ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
 455                                                MATSU_SD_INFO1_CMP);
 456                 if (ret)
 457                         return ret;
 458         }
 459
 460         return ret;
 461 }
 462
 463 static int matsu_sd_set_bus_width(struct matsu_sd_priv *priv,
 464                                      struct mmc *mmc)
 465 {
 466         u32 val, tmp;
 467
 468         switch (mmc->bus_width) {
 469         case 1:
 470                 val = MATSU_SD_OPTION_WIDTH_1;
 471                 break;
 472         case 4:
 473                 val = MATSU_SD_OPTION_WIDTH_4;
 474                 break;
 475         case 8:
 476                 val = MATSU_SD_OPTION_WIDTH_8;
 477                 break;
 478         default:
 479                 return -EINVAL;
 480         }
 481
 482         tmp = matsu_sd_readl(priv, MATSU_SD_OPTION);
 483         tmp &= ~MATSU_SD_OPTION_WIDTH_MASK;
 484         tmp |= val;
 485         matsu_sd_writel(priv, tmp, MATSU_SD_OPTION);
 486
 487         return 0;
 488 }
 489
 490 static void matsu_sd_set_ddr_mode(struct matsu_sd_priv *priv,
 491                                      struct mmc *mmc)
 492 {
 493         u32 tmp;
 494
 495         tmp = matsu_sd_readl(priv, MATSU_SD_IF_MODE);
 496         if (mmc->ddr_mode)
 497                 tmp |= MATSU_SD_IF_MODE_DDR;
 498         else
 499                 tmp &= ~MATSU_SD_IF_MODE_DDR;
 500         matsu_sd_writel(priv, tmp, MATSU_SD_IF_MODE);
 501 }
 502
 503 static void matsu_sd_set_clk_rate(struct matsu_sd_priv *priv,
 504                                      struct mmc *mmc)
 505 {
 506         unsigned int divisor;
 507         u32 val, tmp;
 508
 509         if (!mmc->clock)
 510                 return;
 511
 512         divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
 513
 514         if (divisor <= 1)
 515                 val = MATSU_SD_CLKCTL_DIV1;
 516         else if (divisor <= 2)
 517                 val = MATSU_SD_CLKCTL_DIV2;
 518         else if (divisor <= 4)
 519                 val = MATSU_SD_CLKCTL_DIV4;
 520         else if (divisor <= 8)
 521                 val = MATSU_SD_CLKCTL_DIV8;
 522         else if (divisor <= 16)
 523                 val = MATSU_SD_CLKCTL_DIV16;
 524         else if (divisor <= 32)
 525                 val = MATSU_SD_CLKCTL_DIV32;
 526         else if (divisor <= 64)
 527                 val = MATSU_SD_CLKCTL_DIV64;
 528         else if (divisor <= 128)
 529                 val = MATSU_SD_CLKCTL_DIV128;
 530         else if (divisor <= 256)
 531                 val = MATSU_SD_CLKCTL_DIV256;
 532         else if (divisor <= 512 || !(priv->caps & MATSU_SD_CAP_DIV1024))
 533                 val = MATSU_SD_CLKCTL_DIV512;
 534         else
 535                 val = MATSU_SD_CLKCTL_DIV1024;
 536
 537         tmp = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
 538         if (tmp & MATSU_SD_CLKCTL_SCLKEN &&
 539             (tmp & MATSU_SD_CLKCTL_DIV_MASK) == val)
 540                 return;
 541
 542         /* stop the clock before changing its rate to avoid a glitch signal */
 543         tmp &= ~MATSU_SD_CLKCTL_SCLKEN;
 544         matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
 545
 546         tmp &= ~MATSU_SD_CLKCTL_DIV_MASK;
 547         tmp |= val | MATSU_SD_CLKCTL_OFFEN;
 548         matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
 549
 550         tmp |= MATSU_SD_CLKCTL_SCLKEN;
 551         matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
 552
 553         udelay(1000);
 554 }
 555
 556 int matsu_sd_set_ios(struct udevice *dev)
 557 {
 558         struct matsu_sd_priv *priv = dev_get_priv(dev);
 559         struct mmc *mmc = mmc_get_mmc_dev(dev);
 560         int ret;
 561
 562         dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
 563                 mmc->clock, mmc->ddr_mode, mmc->bus_width);
 564
 565         ret = matsu_sd_set_bus_width(priv, mmc);
 566         if (ret)
 567                 return ret;
 568         matsu_sd_set_ddr_mode(priv, mmc);
 569         matsu_sd_set_clk_rate(priv, mmc);
 570
 571         return 0;
 572 }
 573
 574 int matsu_sd_get_cd(struct udevice *dev)
 575 {
 576         struct matsu_sd_priv *priv = dev_get_priv(dev);
 577
 578         if (priv->caps & MATSU_SD_CAP_NONREMOVABLE)
 579                 return 1;
 580
 581         return !!(matsu_sd_readl(priv, MATSU_SD_INFO1) &
 582                   MATSU_SD_INFO1_CD);
 583 }
 584
 585 static void matsu_sd_host_init(struct matsu_sd_priv *priv)
 586 {
 587         u32 tmp;
 588
 589         /* soft reset of the host */
 590         tmp = matsu_sd_readl(priv, MATSU_SD_SOFT_RST);
 591         tmp &= ~MATSU_SD_SOFT_RST_RSTX;
 592         matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
 593         tmp |= MATSU_SD_SOFT_RST_RSTX;
 594         matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
 595
 596         /* FIXME: implement eMMC hw_reset */
 597
 598         matsu_sd_writel(priv, MATSU_SD_STOP_SEC, MATSU_SD_STOP);
 599
 600         /*
 601          * Connected to 32bit AXI.
 602          * This register dropped backward compatibility at version 0x10.
 603          * Write an appropriate value depending on the IP version.
 604          */
 605         matsu_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000,
 606                            MATSU_SD_HOST_MODE);
 607
 608         if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL) {
 609                 tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
 610                 tmp |= MATSU_SD_DMA_MODE_ADDR_INC;
 611                 matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
 612         }
 613 }
 614
 615 int matsu_sd_bind(struct udevice *dev)
 616 {
 617         struct matsu_sd_plat *plat = dev_get_platdata(dev);
 618
 619         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 620 }
 621
 622 int matsu_sd_probe(struct udevice *dev)
 623 {
 624         struct matsu_sd_plat *plat = dev_get_platdata(dev);
 625         struct matsu_sd_priv *priv = dev_get_priv(dev);
 626         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 627         const u32 quirks = dev_get_driver_data(dev);
 628         fdt_addr_t base;
 629         struct clk clk;
 630         int ret;
 631 #ifdef CONFIG_DM_REGULATOR
 632         struct udevice *vqmmc_dev;
 633 #endif
 634
 635         base = devfdt_get_addr(dev);
 636         if (base == FDT_ADDR_T_NONE)
 637                 return -EINVAL;
 638
 639         priv->regbase = devm_ioremap(dev, base, SZ_2K);
 640         if (!priv->regbase)
 641                 return -ENOMEM;
 642
 643 #ifdef CONFIG_DM_REGULATOR
 644         ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
 645         if (!ret) {
 646                 /* Set the regulator to 3.3V until we support 1.8V modes */
 647                 regulator_set_value(vqmmc_dev, 3300000);
 648                 regulator_set_enable(vqmmc_dev, true);
 649         }
 650 #endif
 651
 652         ret = clk_get_by_index(dev, 0, &clk);
 653         if (ret < 0) {
 654                 dev_err(dev, "failed to get host clock\n");
 655                 return ret;
 656         }
 657
 658         /* set to max rate */
 659         priv->mclk = clk_set_rate(&clk, ULONG_MAX);
 660         if (IS_ERR_VALUE(priv->mclk)) {
 661                 dev_err(dev, "failed to set rate for host clock\n");
 662                 clk_free(&clk);
 663                 return priv->mclk;
 664         }
 665
 666         ret = clk_enable(&clk);
 667         clk_free(&clk);
 668         if (ret) {
 669                 dev_err(dev, "failed to enable host clock\n");
 670                 return ret;
 671         }
 672
 673         plat->cfg.name = dev->name;
 674         plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
 675
 676         switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
 677                                1)) {
 678         case 8:
 679                 plat->cfg.host_caps |= MMC_MODE_8BIT;
 680                 break;
 681         case 4:
 682                 plat->cfg.host_caps |= MMC_MODE_4BIT;
 683                 break;
 684         case 1:
 685                 break;
 686         default:
 687                 dev_err(dev, "Invalid \"bus-width\" value\n");
 688                 return -EINVAL;
 689         }
 690
 691         if (quirks) {
 692                 priv->caps = quirks;
 693         } else {
 694                 priv->version = matsu_sd_readl(priv, MATSU_SD_VERSION) &
 695                                                         MATSU_SD_VERSION_IP;
 696                 dev_dbg(dev, "version %x\n", priv->version);
 697                 if (priv->version >= 0x10) {
 698                         priv->caps |= MATSU_SD_CAP_DMA_INTERNAL;
 699                         priv->caps |= MATSU_SD_CAP_DIV1024;
 700                 }
 701         }
 702
 703         if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
 704                              NULL))
 705                 priv->caps |= MATSU_SD_CAP_NONREMOVABLE;
 706
 707         matsu_sd_host_init(priv);
 708
 709         plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
 710         plat->cfg.f_min = priv->mclk /
 711                         (priv->caps & MATSU_SD_CAP_DIV1024 ? 1024 : 512);
 712         plat->cfg.f_max = priv->mclk;
 713         plat->cfg.b_max = U32_MAX; /* max value of MATSU_SD_SECCNT */
 714
 715         upriv->mmc = &plat->mmc;
 716
 717         return 0;
 718 }