drivers/mmc/matsushita-common.c

   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <fdtdec.h>
  11 #include <mmc.h>
  12 #include <dm.h>
  13 #include <dm/pinctrl.h>
  14 #include <linux/compat.h>
  15 #include <linux/dma-direction.h>
  16 #include <linux/io.h>
  17 #include <linux/sizes.h>
  18 #include <power/regulator.h>
  19 #include <asm/unaligned.h>
  20
  21 #include "matsushita-common.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 static u64 matsu_sd_readq(struct matsu_sd_priv *priv, unsigned int reg)
  26 {
  27         return readq(priv->regbase + (reg << 1));
  28 }
  29
  30 static void matsu_sd_writeq(struct matsu_sd_priv *priv,
  31                                u64 val, unsigned int reg)
  32 {
  33         writeq(val, priv->regbase + (reg << 1));
  34 }
  35
  36 static u16 matsu_sd_readw(struct matsu_sd_priv *priv, unsigned int reg)
  37 {
  38         return readw(priv->regbase + (reg >> 1));
  39 }
  40
  41 static void matsu_sd_writew(struct matsu_sd_priv *priv,
  42                                u16 val, unsigned int reg)
  43 {
  44         writew(val, priv->regbase + (reg >> 1));
  45 }
  46
  47 static u32 matsu_sd_readl(struct matsu_sd_priv *priv, unsigned int reg)
  48 {
  49         u32 val;
  50
  51         if (priv->caps & MATSU_SD_CAP_64BIT)
  52                 return readl(priv->regbase + (reg << 1));
  53         else if (priv->caps & MATSU_SD_CAP_16BIT) {
  54                 val = readw(priv->regbase + (reg >> 1)) & 0xffff;
  55                 if ((reg == MATSU_SD_RSP10) || (reg == MATSU_SD_RSP32) ||
  56                     (reg == MATSU_SD_RSP54) || (reg == MATSU_SD_RSP76)) {
  57                         val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
  58                 }
  59                 return val;
  60         } else
  61                 return readl(priv->regbase + reg);
  62 }
  63
  64 static void matsu_sd_writel(struct matsu_sd_priv *priv,
  65                                u32 val, unsigned int reg)
  66 {
  67         if (priv->caps & MATSU_SD_CAP_64BIT)
  68                 writel(val, priv->regbase + (reg << 1));
  69         if (priv->caps & MATSU_SD_CAP_16BIT) {
  70                 writew(val & 0xffff, priv->regbase + (reg >> 1));
  71                 if (val >> 16)
  72                         writew(val >> 16, priv->regbase + (reg >> 1) + 2);
  73         } else
  74                 writel(val, priv->regbase + reg);
  75 }
  76
  77 static dma_addr_t __dma_map_single(void *ptr, size_t size,
  78                                    enum dma_data_direction dir)
  79 {
  80         unsigned long addr = (unsigned long)ptr;
  81
  82         if (dir == DMA_FROM_DEVICE)
  83                 invalidate_dcache_range(addr, addr + size);
  84         else
  85                 flush_dcache_range(addr, addr + size);
  86
  87         return addr;
  88 }
  89
  90 static void __dma_unmap_single(dma_addr_t addr, size_t size,
  91                                enum dma_data_direction dir)
  92 {
  93         if (dir != DMA_TO_DEVICE)
  94                 invalidate_dcache_range(addr, addr + size);
  95 }
  96
  97 static int matsu_sd_check_error(struct udevice *dev)
  98 {
  99         struct matsu_sd_priv *priv = dev_get_priv(dev);
 100         u32 info2 = matsu_sd_readl(priv, MATSU_SD_INFO2);
 101
 102         if (info2 & MATSU_SD_INFO2_ERR_RTO) {
 103                 /*
 104                  * TIMEOUT must be returned for unsupported command.  Do not
 105                  * display error log since this might be a part of sequence to
 106                  * distinguish between SD and MMC.
 107                  */
 108                 return -ETIMEDOUT;
 109         }
 110
 111         if (info2 & MATSU_SD_INFO2_ERR_TO) {
 112                 dev_err(dev, "timeout error\n");
 113                 return -ETIMEDOUT;
 114         }
 115
 116         if (info2 & (MATSU_SD_INFO2_ERR_END | MATSU_SD_INFO2_ERR_CRC |
 117                      MATSU_SD_INFO2_ERR_IDX)) {
 118                 dev_err(dev, "communication out of sync\n");
 119                 return -EILSEQ;
 120         }
 121
 122         if (info2 & (MATSU_SD_INFO2_ERR_ILA | MATSU_SD_INFO2_ERR_ILR |
 123                      MATSU_SD_INFO2_ERR_ILW)) {
 124                 dev_err(dev, "illegal access\n");
 125                 return -EIO;
 126         }
 127
 128         return 0;
 129 }
 130
 131 static int matsu_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
 132                                     u32 flag)
 133 {
 134         struct matsu_sd_priv *priv = dev_get_priv(dev);
 135         long wait = 1000000;
 136         int ret;
 137
 138         while (!(matsu_sd_readl(priv, reg) & flag)) {
 139                 if (wait-- < 0) {
 140                         dev_err(dev, "timeout\n");
 141                         return -ETIMEDOUT;
 142                 }
 143
 144                 ret = matsu_sd_check_error(dev);
 145                 if (ret)
 146                         return ret;
 147
 148                 udelay(1);
 149         }
 150
 151         return 0;
 152 }
 153
 154 #define matsu_pio_read_fifo(__width, __suffix)                          \
 155 static void matsu_pio_read_fifo_##__width(struct matsu_sd_priv *priv,   \
 156                                           char *pbuf, uint blksz)       \
 157 {                                                                       \
 158         u##__width *buf = (u##__width *)pbuf;                           \
 159         int i;                                                          \
 160                                                                         \
 161         if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) {      \
 162                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 163                         *buf++ = matsu_sd_read##__suffix(priv,          \
 164                                                          MATSU_SD_BUF); \
 165                 }                                                       \
 166         } else {                                                        \
 167                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 168                         u##__width data;                                \
 169                         data = matsu_sd_read##__suffix(priv,            \
 170                                                        MATSU_SD_BUF);   \
 171                         put_unaligned(data, buf++);                     \
 172                 }                                                       \
 173         }                                                               \
 174 }
 175
 176 matsu_pio_read_fifo(64, q)
 177 matsu_pio_read_fifo(32, l)
 178 matsu_pio_read_fifo(16, w)
 179
 180 static int matsu_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
 181                                           uint blocksize)
 182 {
 183         struct matsu_sd_priv *priv = dev_get_priv(dev);
 184         int ret;
 185
 186         /* wait until the buffer is filled with data */
 187         ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
 188                                        MATSU_SD_INFO2_BRE);
 189         if (ret)
 190                 return ret;
 191
 192         /*
 193          * Clear the status flag _before_ read the buffer out because
 194          * MATSU_SD_INFO2_BRE is edge-triggered, not level-triggered.
 195          */
 196         matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
 197
 198         if (priv->caps & MATSU_SD_CAP_64BIT)
 199                 matsu_pio_read_fifo_64(priv, pbuf, blocksize);
 200         else if (priv->caps & MATSU_SD_CAP_16BIT)
 201                 matsu_pio_read_fifo_16(priv, pbuf, blocksize);
 202         else
 203                 matsu_pio_read_fifo_32(priv, pbuf, blocksize);
 204
 205         return 0;
 206 }
 207
 208 #define matsu_pio_write_fifo(__width, __suffix)                         \
 209 static void matsu_pio_write_fifo_##__width(struct matsu_sd_priv *priv,  \
 210                                            const char *pbuf, uint blksz)\
 211 {                                                                       \
 212         const u##__width *buf = (const u##__width *)pbuf;               \
 213         int i;                                                          \
 214                                                                         \
 215         if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) {      \
 216                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 217                         matsu_sd_write##__suffix(priv, *buf++,          \
 218                                                  MATSU_SD_BUF);         \
 219                 }                                                       \
 220         } else {                                                        \
 221                 for (i = 0; i < blksz / ((__width) / 8); i++) {         \
 222                         u##__width data = get_unaligned(buf++);         \
 223                         matsu_sd_write##__suffix(priv, data,            \
 224                                                  MATSU_SD_BUF);         \
 225                 }                                                       \
 226         }                                                               \
 227 }
 228
 229 matsu_pio_write_fifo(64, q)
 230 matsu_pio_write_fifo(32, l)
 231 matsu_pio_write_fifo(16, w)
 232
 233 static int matsu_sd_pio_write_one_block(struct udevice *dev,
 234                                            const char *pbuf, uint blocksize)
 235 {
 236         struct matsu_sd_priv *priv = dev_get_priv(dev);
 237         int ret;
 238
 239         /* wait until the buffer becomes empty */
 240         ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO2,
 241                                     MATSU_SD_INFO2_BWE);
 242         if (ret)
 243                 return ret;
 244
 245         matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
 246
 247         if (priv->caps & MATSU_SD_CAP_64BIT)
 248                 matsu_pio_write_fifo_64(priv, pbuf, blocksize);
 249         else if (priv->caps & MATSU_SD_CAP_16BIT)
 250                 matsu_pio_write_fifo_16(priv, pbuf, blocksize);
 251         else
 252                 matsu_pio_write_fifo_32(priv, pbuf, blocksize);
 253
 254         return 0;
 255 }
 256
 257 static int matsu_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
 258 {
 259         const char *src = data->src;
 260         char *dest = data->dest;
 261         int i, ret;
 262
 263         for (i = 0; i < data->blocks; i++) {
 264                 if (data->flags & MMC_DATA_READ)
 265                         ret = matsu_sd_pio_read_one_block(dev, dest,
 266                                                              data->blocksize);
 267                 else
 268                         ret = matsu_sd_pio_write_one_block(dev, src,
 269                                                               data->blocksize);
 270                 if (ret)
 271                         return ret;
 272
 273                 if (data->flags & MMC_DATA_READ)
 274                         dest += data->blocksize;
 275                 else
 276                         src += data->blocksize;
 277         }
 278
 279         return 0;
 280 }
 281
 282 static void matsu_sd_dma_start(struct matsu_sd_priv *priv,
 283                                   dma_addr_t dma_addr)
 284 {
 285         u32 tmp;
 286
 287         matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO1);
 288         matsu_sd_writel(priv, 0, MATSU_SD_DMA_INFO2);
 289
 290         /* enable DMA */
 291         tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
 292         tmp |= MATSU_SD_EXTMODE_DMA_EN;
 293         matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
 294
 295         matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_L);
 296
 297         /* suppress the warning "right shift count >= width of type" */
 298         dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
 299
 300         matsu_sd_writel(priv, dma_addr & U32_MAX, MATSU_SD_DMA_ADDR_H);
 301
 302         matsu_sd_writel(priv, MATSU_SD_DMA_CTL_START, MATSU_SD_DMA_CTL);
 303 }
 304
 305 static int matsu_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
 306                                         unsigned int blocks)
 307 {
 308         struct matsu_sd_priv *priv = dev_get_priv(dev);
 309         long wait = 1000000 + 10 * blocks;
 310
 311         while (!(matsu_sd_readl(priv, MATSU_SD_DMA_INFO1) & flag)) {
 312                 if (wait-- < 0) {
 313                         dev_err(dev, "timeout during DMA\n");
 314                         return -ETIMEDOUT;
 315                 }
 316
 317                 udelay(10);
 318         }
 319
 320         if (matsu_sd_readl(priv, MATSU_SD_DMA_INFO2)) {
 321                 dev_err(dev, "error during DMA\n");
 322                 return -EIO;
 323         }
 324
 325         return 0;
 326 }
 327
 328 static int matsu_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
 329 {
 330         struct matsu_sd_priv *priv = dev_get_priv(dev);
 331         size_t len = data->blocks * data->blocksize;
 332         void *buf;
 333         enum dma_data_direction dir;
 334         dma_addr_t dma_addr;
 335         u32 poll_flag, tmp;
 336         int ret;
 337
 338         tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
 339
 340         if (data->flags & MMC_DATA_READ) {
 341                 buf = data->dest;
 342                 dir = DMA_FROM_DEVICE;
 343                 /*
 344                  * The DMA READ completion flag position differs on Socionext
 345                  * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
 346                  * bit 17 is a hardware bug and forbidden. It is bit 17 on
 347                  * Renesas SoCs and bit 20 does not work on them.
 348                  */
 349                 poll_flag = (priv->caps & MATSU_SD_CAP_RCAR) ?
 350                             MATSU_SD_DMA_INFO1_END_RD :
 351                             MATSU_SD_DMA_INFO1_END_RD2;
 352                 tmp |= MATSU_SD_DMA_MODE_DIR_RD;
 353         } else {
 354                 buf = (void *)data->src;
 355                 dir = DMA_TO_DEVICE;
 356                 poll_flag = MATSU_SD_DMA_INFO1_END_WR;
 357                 tmp &= ~MATSU_SD_DMA_MODE_DIR_RD;
 358         }
 359
 360         matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
 361
 362         dma_addr = __dma_map_single(buf, len, dir);
 363
 364         matsu_sd_dma_start(priv, dma_addr);
 365
 366         ret = matsu_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
 367
 368         __dma_unmap_single(dma_addr, len, dir);
 369
 370         return ret;
 371 }
 372
 373 /* check if the address is DMA'able */
 374 static bool matsu_sd_addr_is_dmaable(unsigned long addr)
 375 {
 376         if (!IS_ALIGNED(addr, MATSU_SD_DMA_MINALIGN))
 377                 return false;
 378
 379 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
 380         defined(CONFIG_SPL_BUILD)
 381         /*
 382          * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
 383          * of L2, which is unreachable from the DMA engine.
 384          */
 385         if (addr < CONFIG_SPL_STACK)
 386                 return false;
 387 #endif
 388
 389         return true;
 390 }
 391
 392 int matsu_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 393                       struct mmc_data *data)
 394 {
 395         struct matsu_sd_priv *priv = dev_get_priv(dev);
 396         int ret;
 397         u32 tmp;
 398
 399         if (matsu_sd_readl(priv, MATSU_SD_INFO2) & MATSU_SD_INFO2_CBSY) {
 400                 dev_err(dev, "command busy\n");
 401                 return -EBUSY;
 402         }
 403
 404         /* clear all status flags */
 405         matsu_sd_writel(priv, 0, MATSU_SD_INFO1);
 406         matsu_sd_writel(priv, 0, MATSU_SD_INFO2);
 407
 408         /* disable DMA once */
 409         tmp = matsu_sd_readl(priv, MATSU_SD_EXTMODE);
 410         tmp &= ~MATSU_SD_EXTMODE_DMA_EN;
 411         matsu_sd_writel(priv, tmp, MATSU_SD_EXTMODE);
 412
 413         matsu_sd_writel(priv, cmd->cmdarg, MATSU_SD_ARG);
 414
 415         tmp = cmd->cmdidx;
 416
 417         if (data) {
 418                 matsu_sd_writel(priv, data->blocksize, MATSU_SD_SIZE);
 419                 matsu_sd_writel(priv, data->blocks, MATSU_SD_SECCNT);
 420
 421                 /* Do not send CMD12 automatically */
 422                 tmp |= MATSU_SD_CMD_NOSTOP | MATSU_SD_CMD_DATA;
 423
 424                 if (data->blocks > 1)
 425                         tmp |= MATSU_SD_CMD_MULTI;
 426
 427                 if (data->flags & MMC_DATA_READ)
 428                         tmp |= MATSU_SD_CMD_RD;
 429         }
 430
 431         /*
 432          * Do not use the response type auto-detection on this hardware.
 433          * CMD8, for example, has different response types on SD and eMMC,
 434          * while this controller always assumes the response type for SD.
 435          * Set the response type manually.
 436          */
 437         switch (cmd->resp_type) {
 438         case MMC_RSP_NONE:
 439                 tmp |= MATSU_SD_CMD_RSP_NONE;
 440                 break;
 441         case MMC_RSP_R1:
 442                 tmp |= MATSU_SD_CMD_RSP_R1;
 443                 break;
 444         case MMC_RSP_R1b:
 445                 tmp |= MATSU_SD_CMD_RSP_R1B;
 446                 break;
 447         case MMC_RSP_R2:
 448                 tmp |= MATSU_SD_CMD_RSP_R2;
 449                 break;
 450         case MMC_RSP_R3:
 451                 tmp |= MATSU_SD_CMD_RSP_R3;
 452                 break;
 453         default:
 454                 dev_err(dev, "unknown response type\n");
 455                 return -EINVAL;
 456         }
 457
 458         dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
 459                 cmd->cmdidx, tmp, cmd->cmdarg);
 460         matsu_sd_writel(priv, tmp, MATSU_SD_CMD);
 461
 462         ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
 463                                        MATSU_SD_INFO1_RSP);
 464         if (ret)
 465                 return ret;
 466
 467         if (cmd->resp_type & MMC_RSP_136) {
 468                 u32 rsp_127_104 = matsu_sd_readl(priv, MATSU_SD_RSP76);
 469                 u32 rsp_103_72 = matsu_sd_readl(priv, MATSU_SD_RSP54);
 470                 u32 rsp_71_40 = matsu_sd_readl(priv, MATSU_SD_RSP32);
 471                 u32 rsp_39_8 = matsu_sd_readl(priv, MATSU_SD_RSP10);
 472
 473                 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
 474                                    ((rsp_103_72  & 0xff000000) >> 24);
 475                 cmd->response[1] = ((rsp_103_72  & 0x00ffffff) << 8) |
 476                                    ((rsp_71_40   & 0xff000000) >> 24);
 477                 cmd->response[2] = ((rsp_71_40   & 0x00ffffff) << 8) |
 478                                    ((rsp_39_8    & 0xff000000) >> 24);
 479                 cmd->response[3] = (rsp_39_8     & 0xffffff)   << 8;
 480         } else {
 481                 /* bit 39-8 */
 482                 cmd->response[0] = matsu_sd_readl(priv, MATSU_SD_RSP10);
 483         }
 484
 485         if (data) {
 486                 /* use DMA if the HW supports it and the buffer is aligned */
 487                 if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL &&
 488                     matsu_sd_addr_is_dmaable((long)data->src))
 489                         ret = matsu_sd_dma_xfer(dev, data);
 490                 else
 491                         ret = matsu_sd_pio_xfer(dev, data);
 492
 493                 ret = matsu_sd_wait_for_irq(dev, MATSU_SD_INFO1,
 494                                                MATSU_SD_INFO1_CMP);
 495                 if (ret)
 496                         return ret;
 497         }
 498
 499         return ret;
 500 }
 501
 502 static int matsu_sd_set_bus_width(struct matsu_sd_priv *priv,
 503                                      struct mmc *mmc)
 504 {
 505         u32 val, tmp;
 506
 507         switch (mmc->bus_width) {
 508         case 0:
 509         case 1:
 510                 val = MATSU_SD_OPTION_WIDTH_1;
 511                 break;
 512         case 4:
 513                 val = MATSU_SD_OPTION_WIDTH_4;
 514                 break;
 515         case 8:
 516                 val = MATSU_SD_OPTION_WIDTH_8;
 517                 break;
 518         default:
 519                 return -EINVAL;
 520         }
 521
 522         tmp = matsu_sd_readl(priv, MATSU_SD_OPTION);
 523         tmp &= ~MATSU_SD_OPTION_WIDTH_MASK;
 524         tmp |= val;
 525         matsu_sd_writel(priv, tmp, MATSU_SD_OPTION);
 526
 527         return 0;
 528 }
 529
 530 static void matsu_sd_set_ddr_mode(struct matsu_sd_priv *priv,
 531                                      struct mmc *mmc)
 532 {
 533         u32 tmp;
 534
 535         tmp = matsu_sd_readl(priv, MATSU_SD_IF_MODE);
 536         if (mmc->ddr_mode)
 537                 tmp |= MATSU_SD_IF_MODE_DDR;
 538         else
 539                 tmp &= ~MATSU_SD_IF_MODE_DDR;
 540         matsu_sd_writel(priv, tmp, MATSU_SD_IF_MODE);
 541 }
 542
 543 static void matsu_sd_set_clk_rate(struct matsu_sd_priv *priv,
 544                                      struct mmc *mmc)
 545 {
 546         unsigned int divisor;
 547         u32 val, tmp;
 548
 549         if (!mmc->clock)
 550                 return;
 551
 552         divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
 553
 554         if (divisor <= 1)
 555                 val = (priv->caps & MATSU_SD_CAP_RCAR) ?
 556                       MATSU_SD_CLKCTL_RCAR_DIV1 : MATSU_SD_CLKCTL_DIV1;
 557         else if (divisor <= 2)
 558                 val = MATSU_SD_CLKCTL_DIV2;
 559         else if (divisor <= 4)
 560                 val = MATSU_SD_CLKCTL_DIV4;
 561         else if (divisor <= 8)
 562                 val = MATSU_SD_CLKCTL_DIV8;
 563         else if (divisor <= 16)
 564                 val = MATSU_SD_CLKCTL_DIV16;
 565         else if (divisor <= 32)
 566                 val = MATSU_SD_CLKCTL_DIV32;
 567         else if (divisor <= 64)
 568                 val = MATSU_SD_CLKCTL_DIV64;
 569         else if (divisor <= 128)
 570                 val = MATSU_SD_CLKCTL_DIV128;
 571         else if (divisor <= 256)
 572                 val = MATSU_SD_CLKCTL_DIV256;
 573         else if (divisor <= 512 || !(priv->caps & MATSU_SD_CAP_DIV1024))
 574                 val = MATSU_SD_CLKCTL_DIV512;
 575         else
 576                 val = MATSU_SD_CLKCTL_DIV1024;
 577
 578         tmp = matsu_sd_readl(priv, MATSU_SD_CLKCTL);
 579         if (tmp & MATSU_SD_CLKCTL_SCLKEN &&
 580             (tmp & MATSU_SD_CLKCTL_DIV_MASK) == val)
 581                 return;
 582
 583         /* stop the clock before changing its rate to avoid a glitch signal */
 584         tmp &= ~MATSU_SD_CLKCTL_SCLKEN;
 585         matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
 586
 587         tmp &= ~MATSU_SD_CLKCTL_DIV_MASK;
 588         tmp |= val | MATSU_SD_CLKCTL_OFFEN;
 589         matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
 590
 591         tmp |= MATSU_SD_CLKCTL_SCLKEN;
 592         matsu_sd_writel(priv, tmp, MATSU_SD_CLKCTL);
 593
 594         udelay(1000);
 595 }
 596
 597 static void matsu_sd_set_pins(struct udevice *dev)
 598 {
 599         __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
 600
 601 #ifdef CONFIG_DM_REGULATOR
 602         struct matsu_sd_priv *priv = dev_get_priv(dev);
 603
 604         if (priv->vqmmc_dev) {
 605                 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
 606                         regulator_set_value(priv->vqmmc_dev, 1800000);
 607                 else
 608                         regulator_set_value(priv->vqmmc_dev, 3300000);
 609                 regulator_set_enable(priv->vqmmc_dev, true);
 610         }
 611 #endif
 612
 613 #ifdef CONFIG_PINCTRL
 614         switch (mmc->selected_mode) {
 615         case MMC_LEGACY:
 616         case SD_LEGACY:
 617         case MMC_HS:
 618         case SD_HS:
 619         case MMC_HS_52:
 620         case MMC_DDR_52:
 621                 pinctrl_select_state(dev, "default");
 622                 break;
 623         case UHS_SDR12:
 624         case UHS_SDR25:
 625         case UHS_SDR50:
 626         case UHS_DDR50:
 627         case UHS_SDR104:
 628         case MMC_HS_200:
 629                 pinctrl_select_state(dev, "state_uhs");
 630                 break;
 631         default:
 632                 break;
 633         }
 634 #endif
 635 }
 636
 637 int matsu_sd_set_ios(struct udevice *dev)
 638 {
 639         struct matsu_sd_priv *priv = dev_get_priv(dev);
 640         struct mmc *mmc = mmc_get_mmc_dev(dev);
 641         int ret;
 642
 643         dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
 644                 mmc->clock, mmc->ddr_mode, mmc->bus_width);
 645
 646         ret = matsu_sd_set_bus_width(priv, mmc);
 647         if (ret)
 648                 return ret;
 649         matsu_sd_set_ddr_mode(priv, mmc);
 650         matsu_sd_set_clk_rate(priv, mmc);
 651         matsu_sd_set_pins(dev);
 652
 653         return 0;
 654 }
 655
 656 int matsu_sd_get_cd(struct udevice *dev)
 657 {
 658         struct matsu_sd_priv *priv = dev_get_priv(dev);
 659
 660         if (priv->caps & MATSU_SD_CAP_NONREMOVABLE)
 661                 return 1;
 662
 663         return !!(matsu_sd_readl(priv, MATSU_SD_INFO1) &
 664                   MATSU_SD_INFO1_CD);
 665 }
 666
 667 static void matsu_sd_host_init(struct matsu_sd_priv *priv)
 668 {
 669         u32 tmp;
 670
 671         /* soft reset of the host */
 672         tmp = matsu_sd_readl(priv, MATSU_SD_SOFT_RST);
 673         tmp &= ~MATSU_SD_SOFT_RST_RSTX;
 674         matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
 675         tmp |= MATSU_SD_SOFT_RST_RSTX;
 676         matsu_sd_writel(priv, tmp, MATSU_SD_SOFT_RST);
 677
 678         /* FIXME: implement eMMC hw_reset */
 679
 680         matsu_sd_writel(priv, MATSU_SD_STOP_SEC, MATSU_SD_STOP);
 681
 682         /*
 683          * Connected to 32bit AXI.
 684          * This register dropped backward compatibility at version 0x10.
 685          * Write an appropriate value depending on the IP version.
 686          */
 687         if (priv->version >= 0x10)
 688                 matsu_sd_writel(priv, 0x101, MATSU_SD_HOST_MODE);
 689         else if (priv->caps & MATSU_SD_CAP_16BIT)
 690                 matsu_sd_writel(priv, 0x1, MATSU_SD_HOST_MODE);
 691         else
 692                 matsu_sd_writel(priv, 0x0, MATSU_SD_HOST_MODE);
 693
 694         if (priv->caps & MATSU_SD_CAP_DMA_INTERNAL) {
 695                 tmp = matsu_sd_readl(priv, MATSU_SD_DMA_MODE);
 696                 tmp |= MATSU_SD_DMA_MODE_ADDR_INC;
 697                 matsu_sd_writel(priv, tmp, MATSU_SD_DMA_MODE);
 698         }
 699 }
 700
 701 int matsu_sd_bind(struct udevice *dev)
 702 {
 703         struct matsu_sd_plat *plat = dev_get_platdata(dev);
 704
 705         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 706 }
 707
 708 int matsu_sd_probe(struct udevice *dev, u32 quirks)
 709 {
 710         struct matsu_sd_plat *plat = dev_get_platdata(dev);
 711         struct matsu_sd_priv *priv = dev_get_priv(dev);
 712         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 713         fdt_addr_t base;
 714         struct clk clk;
 715         int ret;
 716
 717         base = devfdt_get_addr(dev);
 718         if (base == FDT_ADDR_T_NONE)
 719                 return -EINVAL;
 720
 721         priv->regbase = devm_ioremap(dev, base, SZ_2K);
 722         if (!priv->regbase)
 723                 return -ENOMEM;
 724
 725 #ifdef CONFIG_DM_REGULATOR
 726         device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
 727 #endif
 728
 729         ret = clk_get_by_index(dev, 0, &clk);
 730         if (ret < 0) {
 731                 dev_err(dev, "failed to get host clock\n");
 732                 return ret;
 733         }
 734
 735         /* set to max rate */
 736         priv->mclk = clk_set_rate(&clk, ULONG_MAX);
 737         if (IS_ERR_VALUE(priv->mclk)) {
 738                 dev_err(dev, "failed to set rate for host clock\n");
 739                 clk_free(&clk);
 740                 return priv->mclk;
 741         }
 742
 743         ret = clk_enable(&clk);
 744         clk_free(&clk);
 745         if (ret) {
 746                 dev_err(dev, "failed to enable host clock\n");
 747                 return ret;
 748         }
 749
 750         ret = mmc_of_parse(dev, &plat->cfg);
 751         if (ret < 0) {
 752                 dev_err(dev, "failed to parse host caps\n");
 753                 return ret;
 754         }
 755
 756         plat->cfg.name = dev->name;
 757         plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 758
 759         if (quirks)
 760                 priv->caps = quirks;
 761
 762         priv->version = matsu_sd_readl(priv, MATSU_SD_VERSION) &
 763                                                 MATSU_SD_VERSION_IP;
 764         dev_dbg(dev, "version %x\n", priv->version);
 765         if (priv->version >= 0x10) {
 766                 priv->caps |= MATSU_SD_CAP_DMA_INTERNAL;
 767                 priv->caps |= MATSU_SD_CAP_DIV1024;
 768         }
 769
 770         if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
 771                              NULL))
 772                 priv->caps |= MATSU_SD_CAP_NONREMOVABLE;
 773
 774         matsu_sd_host_init(priv);
 775
 776         plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
 777         plat->cfg.f_min = priv->mclk /
 778                         (priv->caps & MATSU_SD_CAP_DIV1024 ? 1024 : 512);
 779         plat->cfg.f_max = priv->mclk;
 780         plat->cfg.b_max = U32_MAX; /* max value of MATSU_SD_SECCNT */
 781
 782         upriv->mmc = &plat->mmc;
 783
 784         return 0;
 785 }