1 // SPDX-License-Identifier: GPL-2.0+
3 * Ingenic JZ MMC driver
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
13 #include <asm/unaligned.h>
15 #include <dm/device_compat.h>
16 #include <mach/jz4780.h>
20 #define MSC_STRPCL 0x000
21 #define MSC_STAT 0x004
22 #define MSC_CLKRT 0x008
23 #define MSC_CMDAT 0x00c
24 #define MSC_RESTO 0x010
25 #define MSC_RDTO 0x014
26 #define MSC_BLKLEN 0x018
28 #define MSC_SNOB 0x020
29 #define MSC_IMASK 0x024
30 #define MSC_IREG 0x028
34 #define MSC_RXFIFO 0x038
35 #define MSC_TXFIFO 0x03c
37 #define MSC_DMAC 0x044
38 #define MSC_DMANDA 0x048
39 #define MSC_DMADA 0x04c
40 #define MSC_DMALEN 0x050
41 #define MSC_DMACMD 0x054
42 #define MSC_CTRL2 0x058
43 #define MSC_RTCNT 0x05c
46 /* MSC Clock and Control Register (MSC_STRPCL) */
47 #define MSC_STRPCL_EXIT_MULTIPLE BIT(7)
48 #define MSC_STRPCL_EXIT_TRANSFER BIT(6)
49 #define MSC_STRPCL_START_READWAIT BIT(5)
50 #define MSC_STRPCL_STOP_READWAIT BIT(4)
51 #define MSC_STRPCL_RESET BIT(3)
52 #define MSC_STRPCL_START_OP BIT(2)
53 #define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0)
54 #define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
56 /* MSC Status Register (MSC_STAT) */
57 #define MSC_STAT_AUTO_CMD_DONE BIT(31)
58 #define MSC_STAT_IS_RESETTING BIT(15)
59 #define MSC_STAT_SDIO_INT_ACTIVE BIT(14)
60 #define MSC_STAT_PRG_DONE BIT(13)
61 #define MSC_STAT_DATA_TRAN_DONE BIT(12)
62 #define MSC_STAT_END_CMD_RES BIT(11)
63 #define MSC_STAT_DATA_FIFO_AFULL BIT(10)
64 #define MSC_STAT_IS_READWAIT BIT(9)
65 #define MSC_STAT_CLK_EN BIT(8)
66 #define MSC_STAT_DATA_FIFO_FULL BIT(7)
67 #define MSC_STAT_DATA_FIFO_EMPTY BIT(6)
68 #define MSC_STAT_CRC_RES_ERR BIT(5)
69 #define MSC_STAT_CRC_READ_ERROR BIT(4)
70 #define MSC_STAT_CRC_WRITE_ERROR BIT(2)
71 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
72 #define MSC_STAT_TIME_OUT_RES BIT(1)
73 #define MSC_STAT_TIME_OUT_READ BIT(0)
75 /* MSC Bus Clock Control Register (MSC_CLKRT) */
76 #define MSC_CLKRT_CLK_RATE_MASK 0x7
78 /* MSC Command Sequence Control Register (MSC_CMDAT) */
79 #define MSC_CMDAT_IO_ABORT BIT(11)
80 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9)
81 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9)
82 #define MSC_CMDAT_DMA_EN BIT(8)
83 #define MSC_CMDAT_INIT BIT(7)
84 #define MSC_CMDAT_BUSY BIT(6)
85 #define MSC_CMDAT_STREAM_BLOCK BIT(5)
86 #define MSC_CMDAT_WRITE BIT(4)
87 #define MSC_CMDAT_DATA_EN BIT(3)
88 #define MSC_CMDAT_RESPONSE_MASK (0x7 << 0)
89 #define MSC_CMDAT_RESPONSE_NONE (0x0 << 0) /* No response */
90 #define MSC_CMDAT_RESPONSE_R1 (0x1 << 0) /* Format R1 and R1b */
91 #define MSC_CMDAT_RESPONSE_R2 (0x2 << 0) /* Format R2 */
92 #define MSC_CMDAT_RESPONSE_R3 (0x3 << 0) /* Format R3 */
93 #define MSC_CMDAT_RESPONSE_R4 (0x4 << 0) /* Format R4 */
94 #define MSC_CMDAT_RESPONSE_R5 (0x5 << 0) /* Format R5 */
95 #define MSC_CMDAT_RESPONSE_R6 (0x6 << 0) /* Format R6 */
97 /* MSC Interrupts Mask Register (MSC_IMASK) */
98 #define MSC_IMASK_TIME_OUT_RES BIT(9)
99 #define MSC_IMASK_TIME_OUT_READ BIT(8)
100 #define MSC_IMASK_SDIO BIT(7)
101 #define MSC_IMASK_TXFIFO_WR_REQ BIT(6)
102 #define MSC_IMASK_RXFIFO_RD_REQ BIT(5)
103 #define MSC_IMASK_END_CMD_RES BIT(2)
104 #define MSC_IMASK_PRG_DONE BIT(1)
105 #define MSC_IMASK_DATA_TRAN_DONE BIT(0)
107 /* MSC Interrupts Status Register (MSC_IREG) */
108 #define MSC_IREG_TIME_OUT_RES BIT(9)
109 #define MSC_IREG_TIME_OUT_READ BIT(8)
110 #define MSC_IREG_SDIO BIT(7)
111 #define MSC_IREG_TXFIFO_WR_REQ BIT(6)
112 #define MSC_IREG_RXFIFO_RD_REQ BIT(5)
113 #define MSC_IREG_END_CMD_RES BIT(2)
114 #define MSC_IREG_PRG_DONE BIT(1)
115 #define MSC_IREG_DATA_TRAN_DONE BIT(0)
118 struct mmc_config cfg;
126 #define JZ_MMC_BUS_WIDTH_MASK 0x3
127 #define JZ_MMC_BUS_WIDTH_1 0x0
128 #define JZ_MMC_BUS_WIDTH_4 0x2
129 #define JZ_MMC_BUS_WIDTH_8 0x3
130 #define JZ_MMC_SENT_INIT BIT(2)
133 static int jz_mmc_clock_rate(void)
138 #if CONFIG_IS_ENABLED(MMC_WRITE)
139 static inline void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
141 int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
142 const void *buf = data->src;
145 u32 val = get_unaligned_le32(buf);
147 wait_for_bit_le32(priv->regs + MSC_IREG,
148 MSC_IREG_TXFIFO_WR_REQ,
150 writel(val, priv->regs + MSC_TXFIFO);
155 static void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
159 static inline int jz_mmc_read_data(struct jz_mmc_priv *priv, struct mmc_data *data)
161 int sz = data->blocks * data->blocksize;
162 void *buf = data->dest;
166 stat = readl(priv->regs + MSC_STAT);
168 if (stat & MSC_STAT_TIME_OUT_READ)
170 if (stat & MSC_STAT_CRC_READ_ERROR)
172 if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
177 val = readl(priv->regs + MSC_RXFIFO);
179 *(u8 *)buf = (u8)val;
181 put_unaligned_le16(val, buf);
183 put_unaligned_le32(val, buf);
186 stat = readl(priv->regs + MSC_STAT);
187 } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
188 } while (!(stat & MSC_STAT_DATA_TRAN_DONE));
192 static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
193 struct mmc_cmd *cmd, struct mmc_data *data)
195 u32 stat, mask, cmdat = 0;
199 writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
200 ret = wait_for_bit_le32(priv->regs + MSC_STAT,
201 MSC_STAT_CLK_EN, false, 10000, false);
205 writel(0, priv->regs + MSC_DMAC);
208 writel(cmd->cmdidx, priv->regs + MSC_CMD);
209 writel(cmd->cmdarg, priv->regs + MSC_ARG);
213 cmdat |= MSC_CMDAT_DATA_EN;
214 if (data->flags & MMC_DATA_WRITE)
215 cmdat |= MSC_CMDAT_WRITE;
217 writel(data->blocks, priv->regs + MSC_NOB);
218 writel(data->blocksize, priv->regs + MSC_BLKLEN);
220 writel(0, priv->regs + MSC_NOB);
221 writel(0, priv->regs + MSC_BLKLEN);
225 switch (cmd->resp_type) {
230 cmdat |= MSC_CMDAT_RESPONSE_R1;
233 cmdat |= MSC_CMDAT_RESPONSE_R2;
236 cmdat |= MSC_CMDAT_RESPONSE_R3;
242 if (cmd->resp_type & MMC_RSP_BUSY)
243 cmdat |= MSC_CMDAT_BUSY;
245 /* set init for the first command only */
246 if (!(priv->flags & JZ_MMC_SENT_INIT)) {
247 cmdat |= MSC_CMDAT_INIT;
248 priv->flags |= JZ_MMC_SENT_INIT;
251 cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;
253 /* write the data setup */
254 writel(cmdat, priv->regs + MSC_CMDAT);
256 /* unmask interrupts */
257 mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES);
259 mask &= ~MSC_IMASK_DATA_TRAN_DONE;
260 if (data->flags & MMC_DATA_WRITE) {
261 mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
263 mask &= ~(MSC_IMASK_RXFIFO_RD_REQ |
264 MSC_IMASK_TIME_OUT_READ);
267 writel(mask, priv->regs + MSC_IMASK);
269 /* clear interrupts */
270 writel(0xffffffff, priv->regs + MSC_IREG);
272 /* start the command (& the clock) */
273 writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START,
274 priv->regs + MSC_STRPCL);
276 /* wait for completion */
277 for (i = 0; i < 100; i++) {
278 stat = readl(priv->regs + MSC_IREG);
279 stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES;
284 writel(stat, priv->regs + MSC_IREG);
285 if (stat & MSC_IREG_TIME_OUT_RES)
288 if (cmd->resp_type & MMC_RSP_PRESENT) {
289 /* read the response */
290 if (cmd->resp_type & MMC_RSP_136) {
293 a = readw(priv->regs + MSC_RES);
294 for (i = 0; i < 4; i++) {
295 b = readw(priv->regs + MSC_RES);
296 c = readw(priv->regs + MSC_RES);
298 (a << 24) | (b << 8) | (c >> 8);
302 cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
303 cmd->response[0] |= readw(priv->regs + MSC_RES) << 8;
304 cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
308 if (data->flags & MMC_DATA_WRITE)
309 jz_mmc_write_data(priv, data);
310 else if (data->flags & MMC_DATA_READ) {
311 ret = jz_mmc_read_data(priv, data);
320 static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv)
322 u32 real_rate = jz_mmc_clock_rate();
325 /* calculate clock divide */
326 while ((real_rate > mmc->clock) && (clk_div < 7)) {
330 writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);
332 /* set the bus width for the next command */
333 priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
334 if (mmc->bus_width == 8)
335 priv->flags |= JZ_MMC_BUS_WIDTH_8;
336 else if (mmc->bus_width == 4)
337 priv->flags |= JZ_MMC_BUS_WIDTH_4;
339 priv->flags |= JZ_MMC_BUS_WIDTH_1;
344 static int jz_mmc_core_init(struct mmc *mmc)
346 struct jz_mmc_priv *priv = mmc->priv;
350 writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
351 ret = wait_for_bit_le32(priv->regs + MSC_STAT,
352 MSC_STAT_IS_RESETTING, false, 10000, false);
356 /* Maximum timeouts */
357 writel(0xffff, priv->regs + MSC_RESTO);
358 writel(0xffffffff, priv->regs + MSC_RDTO);
360 /* Enable low power mode */
361 writel(0x1, priv->regs + MSC_LPM);
366 #if !CONFIG_IS_ENABLED(DM_MMC)
368 static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
369 struct mmc_data *data)
371 struct jz_mmc_priv *priv = mmc->priv;
373 return jz_mmc_send_cmd(mmc, priv, cmd, data);
376 static int jz_mmc_legacy_set_ios(struct mmc *mmc)
378 struct jz_mmc_priv *priv = mmc->priv;
380 return jz_mmc_set_ios(mmc, priv);
383 static const struct mmc_ops jz_msc_ops = {
384 .send_cmd = jz_mmc_legacy_send_cmd,
385 .set_ios = jz_mmc_legacy_set_ios,
386 .init = jz_mmc_core_init,
389 static struct jz_mmc_priv jz_mmc_priv_static;
390 static struct jz_mmc_plat jz_mmc_plat_static = {
395 .voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
396 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
397 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36,
398 .host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
402 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
406 int jz_mmc_init(void __iomem *base)
410 jz_mmc_priv_static.regs = base;
412 mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);
414 return mmc ? 0 : -ENODEV;
417 #else /* CONFIG_DM_MMC */
420 DECLARE_GLOBAL_DATA_PTR;
422 static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
423 struct mmc_data *data)
425 struct jz_mmc_priv *priv = dev_get_priv(dev);
426 struct mmc *mmc = mmc_get_mmc_dev(dev);
428 return jz_mmc_send_cmd(mmc, priv, cmd, data);
431 static int jz_mmc_dm_set_ios(struct udevice *dev)
433 struct jz_mmc_priv *priv = dev_get_priv(dev);
434 struct mmc *mmc = mmc_get_mmc_dev(dev);
436 return jz_mmc_set_ios(mmc, priv);
439 static const struct dm_mmc_ops jz_msc_ops = {
440 .send_cmd = jz_mmc_dm_send_cmd,
441 .set_ios = jz_mmc_dm_set_ios,
444 static int jz_mmc_ofdata_to_platdata(struct udevice *dev)
446 struct jz_mmc_priv *priv = dev_get_priv(dev);
447 struct jz_mmc_plat *plat = dev_get_platdata(dev);
448 struct mmc_config *cfg;
451 priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);
455 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
457 ret = mmc_of_parse(dev, cfg);
459 dev_err(dev, "failed to parse host caps\n");
464 cfg->f_max = 52000000;
466 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
467 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
472 static int jz_mmc_bind(struct udevice *dev)
474 struct jz_mmc_plat *plat = dev_get_platdata(dev);
476 return mmc_bind(dev, &plat->mmc, &plat->cfg);
479 static int jz_mmc_probe(struct udevice *dev)
481 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
482 struct jz_mmc_priv *priv = dev_get_priv(dev);
483 struct jz_mmc_plat *plat = dev_get_platdata(dev);
485 plat->mmc.priv = priv;
486 upriv->mmc = &plat->mmc;
487 return jz_mmc_core_init(&plat->mmc);
490 static const struct udevice_id jz_mmc_ids[] = {
491 { .compatible = "ingenic,jz4780-mmc" },
495 U_BOOT_DRIVER(jz_mmc_drv) = {
498 .of_match = jz_mmc_ids,
499 .ofdata_to_platdata = jz_mmc_ofdata_to_platdata,
501 .probe = jz_mmc_probe,
502 .priv_auto_alloc_size = sizeof(struct jz_mmc_priv),
503 .platdata_auto_alloc_size = sizeof(struct jz_mmc_plat),
506 #endif /* CONFIG_DM_MMC */