drivers/mmc/host/sdhci_am654.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
   4  *
   5  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/of.h>
  10 #include <linux/module.h>
  11 #include <linux/pm_runtime.h>
  12 #include <linux/property.h>
  13 #include <linux/regmap.h>
  14
  15 #include "sdhci-pltfm.h"
  16
  17 /* CTL_CFG Registers */
  18 #define CTL_CFG_2               0x14
  19
  20 #define SLOTTYPE_MASK           GENMASK(31, 30)
  21 #define SLOTTYPE_EMBEDDED       BIT(30)
  22
  23 /* PHY Registers */
  24 #define PHY_CTRL1       0x100
  25 #define PHY_CTRL2       0x104
  26 #define PHY_CTRL3       0x108
  27 #define PHY_CTRL4       0x10C
  28 #define PHY_CTRL5       0x110
  29 #define PHY_CTRL6       0x114
  30 #define PHY_STAT1       0x130
  31 #define PHY_STAT2       0x134
  32
  33 #define IOMUX_ENABLE_SHIFT      31
  34 #define IOMUX_ENABLE_MASK       BIT(IOMUX_ENABLE_SHIFT)
  35 #define OTAPDLYENA_SHIFT        20
  36 #define OTAPDLYENA_MASK         BIT(OTAPDLYENA_SHIFT)
  37 #define OTAPDLYSEL_SHIFT        12
  38 #define OTAPDLYSEL_MASK         GENMASK(15, 12)
  39 #define STRBSEL_SHIFT           24
  40 #define STRBSEL_4BIT_MASK       GENMASK(27, 24)
  41 #define STRBSEL_8BIT_MASK       GENMASK(31, 24)
  42 #define SEL50_SHIFT             8
  43 #define SEL50_MASK              BIT(SEL50_SHIFT)
  44 #define SEL100_SHIFT            9
  45 #define SEL100_MASK             BIT(SEL100_SHIFT)
  46 #define FREQSEL_SHIFT           8
  47 #define FREQSEL_MASK            GENMASK(10, 8)
  48 #define DLL_TRIM_ICP_SHIFT      4
  49 #define DLL_TRIM_ICP_MASK       GENMASK(7, 4)
  50 #define DR_TY_SHIFT             20
  51 #define DR_TY_MASK              GENMASK(22, 20)
  52 #define ENDLL_SHIFT             1
  53 #define ENDLL_MASK              BIT(ENDLL_SHIFT)
  54 #define DLLRDY_SHIFT            0
  55 #define DLLRDY_MASK             BIT(DLLRDY_SHIFT)
  56 #define PDB_SHIFT               0
  57 #define PDB_MASK                BIT(PDB_SHIFT)
  58 #define CALDONE_SHIFT           1
  59 #define CALDONE_MASK            BIT(CALDONE_SHIFT)
  60 #define RETRIM_SHIFT            17
  61 #define RETRIM_MASK             BIT(RETRIM_SHIFT)
  62
  63 #define DRIVER_STRENGTH_50_OHM  0x0
  64 #define DRIVER_STRENGTH_33_OHM  0x1
  65 #define DRIVER_STRENGTH_66_OHM  0x2
  66 #define DRIVER_STRENGTH_100_OHM 0x3
  67 #define DRIVER_STRENGTH_40_OHM  0x4
  68
  69 #define CLOCK_TOO_SLOW_HZ       400000
  70
  71 static struct regmap_config sdhci_am654_regmap_config = {
  72         .reg_bits = 32,
  73         .val_bits = 32,
  74         .reg_stride = 4,
  75         .fast_io = true,
  76 };
  77
  78 struct sdhci_am654_data {
  79         struct regmap *base;
  80         int otap_del_sel;
  81         int trm_icp;
  82         int drv_strength;
  83         bool dll_on;
  84         int strb_sel;
  85         u32 flags;
  86 };
  87
  88 struct sdhci_am654_driver_data {
  89         const struct sdhci_pltfm_data *pdata;
  90         u32 flags;
  91 #define IOMUX_PRESENT   (1 << 0)
  92 #define FREQSEL_2_BIT   (1 << 1)
  93 #define STRBSEL_4_BIT   (1 << 2)
  94 #define DLL_PRESENT     (1 << 3)
  95 };
  96
  97 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
  98 {
  99         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 100         struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 101         int sel50, sel100, freqsel;
 102         u32 mask, val;
 103         int ret;
 104
 105         if (sdhci_am654->dll_on) {
 106                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
 107
 108                 sdhci_am654->dll_on = false;
 109         }
 110
 111         sdhci_set_clock(host, clock);
 112
 113         if (clock > CLOCK_TOO_SLOW_HZ) {
 114                 /* Setup DLL Output TAP delay */
 115                 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 116                 val = (1 << OTAPDLYENA_SHIFT) |
 117                       (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT);
 118                 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
 119                 /* Write to STRBSEL for HS400 speed mode */
 120                 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
 121                         if (sdhci_am654->flags & STRBSEL_4_BIT)
 122                                 mask = STRBSEL_4BIT_MASK;
 123                         else
 124                                 mask = STRBSEL_8BIT_MASK;
 125
 126                         regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask,
 127                                            sdhci_am654->strb_sel <<
 128                                            STRBSEL_SHIFT);
 129                 }
 130
 131                 if (sdhci_am654->flags & FREQSEL_2_BIT) {
 132                         switch (clock) {
 133                         case 200000000:
 134                                 sel50 = 0;
 135                                 sel100 = 0;
 136                                 break;
 137                         case 100000000:
 138                                 sel50 = 0;
 139                                 sel100 = 1;
 140                                 break;
 141                         default:
 142                                 sel50 = 1;
 143                                 sel100 = 0;
 144                         }
 145
 146                         /* Configure PHY DLL frequency */
 147                         mask = SEL50_MASK | SEL100_MASK;
 148                         val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
 149                         regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask,
 150                                            val);
 151                 } else {
 152                         switch (clock) {
 153                         case 200000000:
 154                                 freqsel = 0x0;
 155                                 break;
 156                         default:
 157                                 freqsel = 0x4;
 158                         }
 159
 160                         regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
 161                                            FREQSEL_MASK,
 162                                            freqsel << FREQSEL_SHIFT);
 163                 }
 164
 165                 /* Configure DLL TRIM */
 166                 mask = DLL_TRIM_ICP_MASK;
 167                 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
 168
 169                 /* Configure DLL driver strength */
 170                 mask |= DR_TY_MASK;
 171                 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
 172                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
 173                 /* Enable DLL */
 174                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
 175                                    0x1 << ENDLL_SHIFT);
 176                 /*
 177                  * Poll for DLL ready. Use a one second timeout.
 178                  * Works in all experiments done so far
 179                  */
 180                 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1,
 181                                                val, val & DLLRDY_MASK, 1000,
 182                                                1000000);
 183                 if (ret) {
 184                         dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
 185                         return;
 186                 }
 187
 188                 sdhci_am654->dll_on = true;
 189         }
 190 }
 191
 192 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
 193                                        unsigned int clock)
 194 {
 195         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 196         struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 197         int val, mask;
 198
 199         mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 200         val = (1 << OTAPDLYENA_SHIFT) |
 201               (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT);
 202         regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
 203
 204         sdhci_set_clock(host, clock);
 205 }
 206
 207 static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode,
 208                                   unsigned short vdd)
 209 {
 210         if (!IS_ERR(host->mmc->supply.vmmc)) {
 211                 struct mmc_host *mmc = host->mmc;
 212
 213                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 214         }
 215         sdhci_set_power_noreg(host, mode, vdd);
 216 }
 217
 218 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
 219 {
 220         unsigned char timing = host->mmc->ios.timing;
 221
 222         if (reg == SDHCI_HOST_CONTROL) {
 223                 switch (timing) {
 224                 /*
 225                  * According to the data manual, HISPD bit
 226                  * should not be set in these speed modes.
 227                  */
 228                 case MMC_TIMING_SD_HS:
 229                 case MMC_TIMING_MMC_HS:
 230                 case MMC_TIMING_UHS_SDR12:
 231                 case MMC_TIMING_UHS_SDR25:
 232                         val &= ~SDHCI_CTRL_HISPD;
 233                 }
 234         }
 235
 236         writeb(val, host->ioaddr + reg);
 237 }
 238
 239 static struct sdhci_ops sdhci_am654_ops = {
 240         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 241         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 242         .set_uhs_signaling = sdhci_set_uhs_signaling,
 243         .set_bus_width = sdhci_set_bus_width,
 244         .set_power = sdhci_am654_set_power,
 245         .set_clock = sdhci_am654_set_clock,
 246         .write_b = sdhci_am654_write_b,
 247         .reset = sdhci_reset,
 248 };
 249
 250 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
 251         .ops = &sdhci_am654_ops,
 252         .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
 253                   SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
 254         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 255 };
 256
 257 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
 258         .pdata = &sdhci_am654_pdata,
 259         .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
 260 };
 261
 262 static struct sdhci_ops sdhci_j721e_8bit_ops = {
 263         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 264         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 265         .set_uhs_signaling = sdhci_set_uhs_signaling,
 266         .set_bus_width = sdhci_set_bus_width,
 267         .set_power = sdhci_am654_set_power,
 268         .set_clock = sdhci_am654_set_clock,
 269         .write_b = sdhci_am654_write_b,
 270         .reset = sdhci_reset,
 271 };
 272
 273 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
 274         .ops = &sdhci_j721e_8bit_ops,
 275         .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
 276                   SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
 277         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 278 };
 279
 280 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
 281         .pdata = &sdhci_j721e_8bit_pdata,
 282         .flags = DLL_PRESENT,
 283 };
 284
 285 static struct sdhci_ops sdhci_j721e_4bit_ops = {
 286         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 287         .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
 288         .set_uhs_signaling = sdhci_set_uhs_signaling,
 289         .set_bus_width = sdhci_set_bus_width,
 290         .set_power = sdhci_am654_set_power,
 291         .set_clock = sdhci_j721e_4bit_set_clock,
 292         .write_b = sdhci_am654_write_b,
 293         .reset = sdhci_reset,
 294 };
 295
 296 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
 297         .ops = &sdhci_j721e_4bit_ops,
 298         .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
 299                   SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
 300         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 301 };
 302
 303 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
 304         .pdata = &sdhci_j721e_4bit_pdata,
 305         .flags = IOMUX_PRESENT,
 306 };
 307 static int sdhci_am654_init(struct sdhci_host *host)
 308 {
 309         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 310         struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 311         u32 ctl_cfg_2 = 0;
 312         u32 mask;
 313         u32 val;
 314         int ret;
 315
 316         /* Reset OTAP to default value */
 317         mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
 318         regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
 319
 320         if (sdhci_am654->flags & DLL_PRESENT) {
 321                 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
 322                 if (~val & CALDONE_MASK) {
 323                         /* Calibrate IO lines */
 324                         regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
 325                                            PDB_MASK, PDB_MASK);
 326                         ret = regmap_read_poll_timeout(sdhci_am654->base,
 327                                                        PHY_STAT1, val,
 328                                                        val & CALDONE_MASK,
 329                                                        1, 20);
 330                         if (ret)
 331                                 return ret;
 332                 }
 333         }
 334
 335         /* Enable pins by setting IO mux to 0 */
 336         if (sdhci_am654->flags & IOMUX_PRESENT)
 337                 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
 338                                    IOMUX_ENABLE_MASK, 0);
 339
 340         /* Set slot type based on SD or eMMC */
 341         if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
 342                 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
 343
 344         regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
 345                            ctl_cfg_2);
 346
 347         return sdhci_add_host(host);
 348 }
 349
 350 static int sdhci_am654_get_of_property(struct platform_device *pdev,
 351                                         struct sdhci_am654_data *sdhci_am654)
 352 {
 353         struct device *dev = &pdev->dev;
 354         int drv_strength;
 355         int ret;
 356
 357         ret = device_property_read_u32(dev, "ti,otap-del-sel",
 358                                        &sdhci_am654->otap_del_sel);
 359         if (ret)
 360                 return ret;
 361
 362         if (sdhci_am654->flags & DLL_PRESENT) {
 363                 ret = device_property_read_u32(dev, "ti,trm-icp",
 364                                                &sdhci_am654->trm_icp);
 365                 if (ret)
 366                         return ret;
 367
 368                 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
 369                                                &drv_strength);
 370                 if (ret)
 371                         return ret;
 372
 373                 switch (drv_strength) {
 374                 case 50:
 375                         sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
 376                         break;
 377                 case 33:
 378                         sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
 379                         break;
 380                 case 66:
 381                         sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
 382                         break;
 383                 case 100:
 384                         sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
 385                         break;
 386                 case 40:
 387                         sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
 388                         break;
 389                 default:
 390                         dev_err(dev, "Invalid driver strength\n");
 391                         return -EINVAL;
 392                 }
 393         }
 394
 395         device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
 396
 397         sdhci_get_of_property(pdev);
 398
 399         return 0;
 400 }
 401
 402 static const struct of_device_id sdhci_am654_of_match[] = {
 403         {
 404                 .compatible = "ti,am654-sdhci-5.1",
 405                 .data = &sdhci_am654_drvdata,
 406         },
 407         {
 408                 .compatible = "ti,j721e-sdhci-8bit",
 409                 .data = &sdhci_j721e_8bit_drvdata,
 410         },
 411         {
 412                 .compatible = "ti,j721e-sdhci-4bit",
 413                 .data = &sdhci_j721e_4bit_drvdata,
 414         },
 415         { /* sentinel */ }
 416 };
 417
 418 static int sdhci_am654_probe(struct platform_device *pdev)
 419 {
 420         const struct sdhci_am654_driver_data *drvdata;
 421         struct sdhci_pltfm_host *pltfm_host;
 422         struct sdhci_am654_data *sdhci_am654;
 423         const struct of_device_id *match;
 424         struct sdhci_host *host;
 425         struct resource *res;
 426         struct clk *clk_xin;
 427         struct device *dev = &pdev->dev;
 428         void __iomem *base;
 429         int ret;
 430
 431         match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
 432         drvdata = match->data;
 433         host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
 434         if (IS_ERR(host))
 435                 return PTR_ERR(host);
 436
 437         pltfm_host = sdhci_priv(host);
 438         sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
 439         sdhci_am654->flags = drvdata->flags;
 440
 441         clk_xin = devm_clk_get(dev, "clk_xin");
 442         if (IS_ERR(clk_xin)) {
 443                 dev_err(dev, "clk_xin clock not found.\n");
 444                 ret = PTR_ERR(clk_xin);
 445                 goto err_pltfm_free;
 446         }
 447
 448         pltfm_host->clk = clk_xin;
 449
 450         /* Clocks are enabled using pm_runtime */
 451         pm_runtime_enable(dev);
 452         ret = pm_runtime_get_sync(dev);
 453         if (ret < 0) {
 454                 pm_runtime_put_noidle(dev);
 455                 goto pm_runtime_disable;
 456         }
 457
 458         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 459         base = devm_ioremap_resource(dev, res);
 460         if (IS_ERR(base)) {
 461                 ret = PTR_ERR(base);
 462                 goto pm_runtime_put;
 463         }
 464
 465         sdhci_am654->base = devm_regmap_init_mmio(dev, base,
 466                                                   &sdhci_am654_regmap_config);
 467         if (IS_ERR(sdhci_am654->base)) {
 468                 dev_err(dev, "Failed to initialize regmap\n");
 469                 ret = PTR_ERR(sdhci_am654->base);
 470                 goto pm_runtime_put;
 471         }
 472
 473         ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
 474         if (ret)
 475                 goto pm_runtime_put;
 476
 477         ret = mmc_of_parse(host->mmc);
 478         if (ret) {
 479                 dev_err(dev, "parsing dt failed (%d)\n", ret);
 480                 goto pm_runtime_put;
 481         }
 482
 483         ret = sdhci_am654_init(host);
 484         if (ret)
 485                 goto pm_runtime_put;
 486
 487         return 0;
 488
 489 pm_runtime_put:
 490         pm_runtime_put_sync(dev);
 491 pm_runtime_disable:
 492         pm_runtime_disable(dev);
 493 err_pltfm_free:
 494         sdhci_pltfm_free(pdev);
 495         return ret;
 496 }
 497
 498 static int sdhci_am654_remove(struct platform_device *pdev)
 499 {
 500         struct sdhci_host *host = platform_get_drvdata(pdev);
 501         int ret;
 502
 503         sdhci_remove_host(host, true);
 504         ret = pm_runtime_put_sync(&pdev->dev);
 505         if (ret < 0)
 506                 return ret;
 507
 508         pm_runtime_disable(&pdev->dev);
 509         sdhci_pltfm_free(pdev);
 510
 511         return 0;
 512 }
 513
 514 static struct platform_driver sdhci_am654_driver = {
 515         .driver = {
 516                 .name = "sdhci-am654",
 517                 .of_match_table = sdhci_am654_of_match,
 518         },
 519         .probe = sdhci_am654_probe,
 520         .remove = sdhci_am654_remove,
 521 };
 522
 523 module_platform_driver(sdhci_am654_driver);
 524
 525 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
 526 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
 527 MODULE_LICENSE("GPL");