1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
5 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
7 * Thanks to the following companies for their support:
9 * - JMicron (hardware and technical support)
12 #include <linux/delay.h>
13 #include <linux/ktime.h>
14 #include <linux/highmem.h>
16 #include <linux/module.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <linux/scatterlist.h>
20 #include <linux/sizes.h>
21 #include <linux/swiotlb.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
36 #define DRIVER_NAME "sdhci"
38 #define DBG(f, x...) \
39 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
41 #define SDHCI_DUMP(f, x...) \
42 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
44 #define MAX_TUNING_LOOP 40
46 static unsigned int debug_quirks = 0;
47 static unsigned int debug_quirks2;
49 static void sdhci_finish_data(struct sdhci_host *);
51 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
53 void sdhci_dumpregs(struct sdhci_host *host)
55 SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
57 SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
58 sdhci_readl(host, SDHCI_DMA_ADDRESS),
59 sdhci_readw(host, SDHCI_HOST_VERSION));
60 SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
61 sdhci_readw(host, SDHCI_BLOCK_SIZE),
62 sdhci_readw(host, SDHCI_BLOCK_COUNT));
63 SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
64 sdhci_readl(host, SDHCI_ARGUMENT),
65 sdhci_readw(host, SDHCI_TRANSFER_MODE));
66 SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
67 sdhci_readl(host, SDHCI_PRESENT_STATE),
68 sdhci_readb(host, SDHCI_HOST_CONTROL));
69 SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
70 sdhci_readb(host, SDHCI_POWER_CONTROL),
71 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
72 SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
73 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
74 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
75 SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
76 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
77 sdhci_readl(host, SDHCI_INT_STATUS));
78 SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
79 sdhci_readl(host, SDHCI_INT_ENABLE),
80 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
81 SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
82 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
83 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
84 SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
85 sdhci_readl(host, SDHCI_CAPABILITIES),
86 sdhci_readl(host, SDHCI_CAPABILITIES_1));
87 SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
88 sdhci_readw(host, SDHCI_COMMAND),
89 sdhci_readl(host, SDHCI_MAX_CURRENT));
90 SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
91 sdhci_readl(host, SDHCI_RESPONSE),
92 sdhci_readl(host, SDHCI_RESPONSE + 4));
93 SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
94 sdhci_readl(host, SDHCI_RESPONSE + 8),
95 sdhci_readl(host, SDHCI_RESPONSE + 12));
96 SDHCI_DUMP("Host ctl2: 0x%08x\n",
97 sdhci_readw(host, SDHCI_HOST_CONTROL2));
99 if (host->flags & SDHCI_USE_ADMA) {
100 if (host->flags & SDHCI_USE_64_BIT_DMA) {
101 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
102 sdhci_readl(host, SDHCI_ADMA_ERROR),
103 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
104 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
106 SDHCI_DUMP("ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
107 sdhci_readl(host, SDHCI_ADMA_ERROR),
108 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
112 SDHCI_DUMP("============================================\n");
114 EXPORT_SYMBOL_GPL(sdhci_dumpregs);
116 /*****************************************************************************\
118 * Low level functions *
120 \*****************************************************************************/
122 static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
126 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
127 if (ctrl2 & SDHCI_CTRL_V4_MODE)
130 ctrl2 |= SDHCI_CTRL_V4_MODE;
131 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
135 * This can be called before sdhci_add_host() by Vendor's host controller
136 * driver to enable v4 mode if supported.
138 void sdhci_enable_v4_mode(struct sdhci_host *host)
140 host->v4_mode = true;
141 sdhci_do_enable_v4_mode(host);
143 EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
145 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
147 return cmd->data || cmd->flags & MMC_RSP_BUSY;
150 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
154 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
155 !mmc_card_is_removable(host->mmc))
159 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
162 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
163 SDHCI_INT_CARD_INSERT;
165 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
168 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
169 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
172 static void sdhci_enable_card_detection(struct sdhci_host *host)
174 sdhci_set_card_detection(host, true);
177 static void sdhci_disable_card_detection(struct sdhci_host *host)
179 sdhci_set_card_detection(host, false);
182 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
187 pm_runtime_get_noresume(host->mmc->parent);
190 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
194 host->bus_on = false;
195 pm_runtime_put_noidle(host->mmc->parent);
198 void sdhci_reset(struct sdhci_host *host, u8 mask)
202 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
204 if (mask & SDHCI_RESET_ALL) {
206 /* Reset-all turns off SD Bus Power */
207 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
208 sdhci_runtime_pm_bus_off(host);
211 /* Wait max 100 ms */
212 timeout = ktime_add_ms(ktime_get(), 100);
214 /* hw clears the bit when it's done */
216 bool timedout = ktime_after(ktime_get(), timeout);
218 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
221 pr_err("%s: Reset 0x%x never completed.\n",
222 mmc_hostname(host->mmc), (int)mask);
223 sdhci_dumpregs(host);
229 EXPORT_SYMBOL_GPL(sdhci_reset);
231 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
233 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
234 struct mmc_host *mmc = host->mmc;
236 if (!mmc->ops->get_cd(mmc))
240 host->ops->reset(host, mask);
242 if (mask & SDHCI_RESET_ALL) {
243 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
244 if (host->ops->enable_dma)
245 host->ops->enable_dma(host);
248 /* Resetting the controller clears many */
249 host->preset_enabled = false;
253 static void sdhci_set_default_irqs(struct sdhci_host *host)
255 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
256 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
257 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
258 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
261 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
262 host->tuning_mode == SDHCI_TUNING_MODE_3)
263 host->ier |= SDHCI_INT_RETUNE;
265 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
266 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
269 static void sdhci_config_dma(struct sdhci_host *host)
274 if (host->version < SDHCI_SPEC_200)
277 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
280 * Always adjust the DMA selection as some controllers
281 * (e.g. JMicron) can't do PIO properly when the selection
284 ctrl &= ~SDHCI_CTRL_DMA_MASK;
285 if (!(host->flags & SDHCI_REQ_USE_DMA))
288 /* Note if DMA Select is zero then SDMA is selected */
289 if (host->flags & SDHCI_USE_ADMA)
290 ctrl |= SDHCI_CTRL_ADMA32;
292 if (host->flags & SDHCI_USE_64_BIT_DMA) {
294 * If v4 mode, all supported DMA can be 64-bit addressing if
295 * controller supports 64-bit system address, otherwise only
296 * ADMA can support 64-bit addressing.
299 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
300 ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
301 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
302 } else if (host->flags & SDHCI_USE_ADMA) {
304 * Don't need to undo SDHCI_CTRL_ADMA32 in order to
305 * set SDHCI_CTRL_ADMA64.
307 ctrl |= SDHCI_CTRL_ADMA64;
312 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
315 static void sdhci_init(struct sdhci_host *host, int soft)
317 struct mmc_host *mmc = host->mmc;
320 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
322 sdhci_do_reset(host, SDHCI_RESET_ALL);
325 sdhci_do_enable_v4_mode(host);
327 sdhci_set_default_irqs(host);
329 host->cqe_on = false;
332 /* force clock reconfiguration */
334 mmc->ops->set_ios(mmc, &mmc->ios);
338 static void sdhci_reinit(struct sdhci_host *host)
341 sdhci_enable_card_detection(host);
344 static void __sdhci_led_activate(struct sdhci_host *host)
348 if (host->quirks & SDHCI_QUIRK_NO_LED)
351 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
352 ctrl |= SDHCI_CTRL_LED;
353 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
356 static void __sdhci_led_deactivate(struct sdhci_host *host)
360 if (host->quirks & SDHCI_QUIRK_NO_LED)
363 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
364 ctrl &= ~SDHCI_CTRL_LED;
365 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
368 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
369 static void sdhci_led_control(struct led_classdev *led,
370 enum led_brightness brightness)
372 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
375 spin_lock_irqsave(&host->lock, flags);
377 if (host->runtime_suspended)
380 if (brightness == LED_OFF)
381 __sdhci_led_deactivate(host);
383 __sdhci_led_activate(host);
385 spin_unlock_irqrestore(&host->lock, flags);
388 static int sdhci_led_register(struct sdhci_host *host)
390 struct mmc_host *mmc = host->mmc;
392 if (host->quirks & SDHCI_QUIRK_NO_LED)
395 snprintf(host->led_name, sizeof(host->led_name),
396 "%s::", mmc_hostname(mmc));
398 host->led.name = host->led_name;
399 host->led.brightness = LED_OFF;
400 host->led.default_trigger = mmc_hostname(mmc);
401 host->led.brightness_set = sdhci_led_control;
403 return led_classdev_register(mmc_dev(mmc), &host->led);
406 static void sdhci_led_unregister(struct sdhci_host *host)
408 if (host->quirks & SDHCI_QUIRK_NO_LED)
411 led_classdev_unregister(&host->led);
414 static inline void sdhci_led_activate(struct sdhci_host *host)
418 static inline void sdhci_led_deactivate(struct sdhci_host *host)
424 static inline int sdhci_led_register(struct sdhci_host *host)
429 static inline void sdhci_led_unregister(struct sdhci_host *host)
433 static inline void sdhci_led_activate(struct sdhci_host *host)
435 __sdhci_led_activate(host);
438 static inline void sdhci_led_deactivate(struct sdhci_host *host)
440 __sdhci_led_deactivate(host);
445 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
446 unsigned long timeout)
448 if (sdhci_data_line_cmd(mrq->cmd))
449 mod_timer(&host->data_timer, timeout);
451 mod_timer(&host->timer, timeout);
454 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
456 if (sdhci_data_line_cmd(mrq->cmd))
457 del_timer(&host->data_timer);
459 del_timer(&host->timer);
462 static inline bool sdhci_has_requests(struct sdhci_host *host)
464 return host->cmd || host->data_cmd;
467 /*****************************************************************************\
471 \*****************************************************************************/
473 static void sdhci_read_block_pio(struct sdhci_host *host)
476 size_t blksize, len, chunk;
477 u32 uninitialized_var(scratch);
480 DBG("PIO reading\n");
482 blksize = host->data->blksz;
485 local_irq_save(flags);
488 BUG_ON(!sg_miter_next(&host->sg_miter));
490 len = min(host->sg_miter.length, blksize);
493 host->sg_miter.consumed = len;
495 buf = host->sg_miter.addr;
499 scratch = sdhci_readl(host, SDHCI_BUFFER);
503 *buf = scratch & 0xFF;
512 sg_miter_stop(&host->sg_miter);
514 local_irq_restore(flags);
517 static void sdhci_write_block_pio(struct sdhci_host *host)
520 size_t blksize, len, chunk;
524 DBG("PIO writing\n");
526 blksize = host->data->blksz;
530 local_irq_save(flags);
533 BUG_ON(!sg_miter_next(&host->sg_miter));
535 len = min(host->sg_miter.length, blksize);
538 host->sg_miter.consumed = len;
540 buf = host->sg_miter.addr;
543 scratch |= (u32)*buf << (chunk * 8);
549 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
550 sdhci_writel(host, scratch, SDHCI_BUFFER);
557 sg_miter_stop(&host->sg_miter);
559 local_irq_restore(flags);
562 static void sdhci_transfer_pio(struct sdhci_host *host)
566 if (host->blocks == 0)
569 if (host->data->flags & MMC_DATA_READ)
570 mask = SDHCI_DATA_AVAILABLE;
572 mask = SDHCI_SPACE_AVAILABLE;
575 * Some controllers (JMicron JMB38x) mess up the buffer bits
576 * for transfers < 4 bytes. As long as it is just one block,
577 * we can ignore the bits.
579 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
580 (host->data->blocks == 1))
583 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
584 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
587 if (host->data->flags & MMC_DATA_READ)
588 sdhci_read_block_pio(host);
590 sdhci_write_block_pio(host);
593 if (host->blocks == 0)
597 DBG("PIO transfer complete.\n");
600 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
601 struct mmc_data *data, int cookie)
606 * If the data buffers are already mapped, return the previous
607 * dma_map_sg() result.
609 if (data->host_cookie == COOKIE_PRE_MAPPED)
610 return data->sg_count;
612 /* Bounce write requests to the bounce buffer */
613 if (host->bounce_buffer) {
614 unsigned int length = data->blksz * data->blocks;
616 if (length > host->bounce_buffer_size) {
617 pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
618 mmc_hostname(host->mmc), length,
619 host->bounce_buffer_size);
622 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
623 /* Copy the data to the bounce buffer */
624 sg_copy_to_buffer(data->sg, data->sg_len,
628 /* Switch ownership to the DMA */
629 dma_sync_single_for_device(host->mmc->parent,
631 host->bounce_buffer_size,
632 mmc_get_dma_dir(data));
633 /* Just a dummy value */
636 /* Just access the data directly from memory */
637 sg_count = dma_map_sg(mmc_dev(host->mmc),
638 data->sg, data->sg_len,
639 mmc_get_dma_dir(data));
645 data->sg_count = sg_count;
646 data->host_cookie = cookie;
651 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
653 local_irq_save(*flags);
654 return kmap_atomic(sg_page(sg)) + sg->offset;
657 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
659 kunmap_atomic(buffer);
660 local_irq_restore(*flags);
663 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
664 dma_addr_t addr, int len, unsigned int cmd)
666 struct sdhci_adma2_64_desc *dma_desc = *desc;
668 /* 32-bit and 64-bit descriptors have these members in same position */
669 dma_desc->cmd = cpu_to_le16(cmd);
670 dma_desc->len = cpu_to_le16(len);
671 dma_desc->addr_lo = cpu_to_le32((u32)addr);
673 if (host->flags & SDHCI_USE_64_BIT_DMA)
674 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
676 *desc += host->desc_sz;
678 EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
680 static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
681 void **desc, dma_addr_t addr,
682 int len, unsigned int cmd)
684 if (host->ops->adma_write_desc)
685 host->ops->adma_write_desc(host, desc, addr, len, cmd);
687 sdhci_adma_write_desc(host, desc, addr, len, cmd);
690 static void sdhci_adma_mark_end(void *desc)
692 struct sdhci_adma2_64_desc *dma_desc = desc;
694 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
695 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
698 static void sdhci_adma_table_pre(struct sdhci_host *host,
699 struct mmc_data *data, int sg_count)
701 struct scatterlist *sg;
703 dma_addr_t addr, align_addr;
709 * The spec does not specify endianness of descriptor table.
710 * We currently guess that it is LE.
713 host->sg_count = sg_count;
715 desc = host->adma_table;
716 align = host->align_buffer;
718 align_addr = host->align_addr;
720 for_each_sg(data->sg, sg, host->sg_count, i) {
721 addr = sg_dma_address(sg);
722 len = sg_dma_len(sg);
725 * The SDHCI specification states that ADMA addresses must
726 * be 32-bit aligned. If they aren't, then we use a bounce
727 * buffer for the (up to three) bytes that screw up the
730 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
733 if (data->flags & MMC_DATA_WRITE) {
734 buffer = sdhci_kmap_atomic(sg, &flags);
735 memcpy(align, buffer, offset);
736 sdhci_kunmap_atomic(buffer, &flags);
740 __sdhci_adma_write_desc(host, &desc, align_addr,
741 offset, ADMA2_TRAN_VALID);
743 BUG_ON(offset > 65536);
745 align += SDHCI_ADMA2_ALIGN;
746 align_addr += SDHCI_ADMA2_ALIGN;
756 __sdhci_adma_write_desc(host, &desc, addr, len,
760 * If this triggers then we have a calculation bug
763 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
766 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
767 /* Mark the last descriptor as the terminating descriptor */
768 if (desc != host->adma_table) {
769 desc -= host->desc_sz;
770 sdhci_adma_mark_end(desc);
773 /* Add a terminating entry - nop, end, valid */
774 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
778 static void sdhci_adma_table_post(struct sdhci_host *host,
779 struct mmc_data *data)
781 struct scatterlist *sg;
787 if (data->flags & MMC_DATA_READ) {
788 bool has_unaligned = false;
790 /* Do a quick scan of the SG list for any unaligned mappings */
791 for_each_sg(data->sg, sg, host->sg_count, i)
792 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
793 has_unaligned = true;
798 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
799 data->sg_len, DMA_FROM_DEVICE);
801 align = host->align_buffer;
803 for_each_sg(data->sg, sg, host->sg_count, i) {
804 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
805 size = SDHCI_ADMA2_ALIGN -
806 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
808 buffer = sdhci_kmap_atomic(sg, &flags);
809 memcpy(buffer, align, size);
810 sdhci_kunmap_atomic(buffer, &flags);
812 align += SDHCI_ADMA2_ALIGN;
819 static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
821 if (host->bounce_buffer)
822 return host->bounce_addr;
824 return sg_dma_address(host->data->sg);
827 static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
830 sdhci_writel(host, addr, SDHCI_ADMA_ADDRESS);
831 if (host->flags & SDHCI_USE_64_BIT_DMA)
832 sdhci_writel(host, (u64)addr >> 32, SDHCI_ADMA_ADDRESS_HI);
834 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
838 static unsigned int sdhci_target_timeout(struct sdhci_host *host,
839 struct mmc_command *cmd,
840 struct mmc_data *data)
842 unsigned int target_timeout;
846 target_timeout = cmd->busy_timeout * 1000;
848 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
849 if (host->clock && data->timeout_clks) {
850 unsigned long long val;
853 * data->timeout_clks is in units of clock cycles.
854 * host->clock is in Hz. target_timeout is in us.
855 * Hence, us = 1000000 * cycles / Hz. Round up.
857 val = 1000000ULL * data->timeout_clks;
858 if (do_div(val, host->clock))
860 target_timeout += val;
864 return target_timeout;
867 static void sdhci_calc_sw_timeout(struct sdhci_host *host,
868 struct mmc_command *cmd)
870 struct mmc_data *data = cmd->data;
871 struct mmc_host *mmc = host->mmc;
872 struct mmc_ios *ios = &mmc->ios;
873 unsigned char bus_width = 1 << ios->bus_width;
879 target_timeout = sdhci_target_timeout(host, cmd, data);
880 target_timeout *= NSEC_PER_USEC;
884 freq = host->mmc->actual_clock ? : host->clock;
885 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
886 do_div(transfer_time, freq);
887 /* multiply by '2' to account for any unknowns */
888 transfer_time = transfer_time * 2;
889 /* calculate timeout for the entire data */
890 host->data_timeout = data->blocks * target_timeout +
893 host->data_timeout = target_timeout;
896 if (host->data_timeout)
897 host->data_timeout += MMC_CMD_TRANSFER_TIME;
900 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
904 struct mmc_data *data;
905 unsigned target_timeout, current_timeout;
910 * If the host controller provides us with an incorrect timeout
911 * value, just skip the check and use 0xE. The hardware may take
912 * longer to time out, but that's much better than having a too-short
915 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
918 /* Unspecified command, asume max */
923 /* Unspecified timeout, assume max */
924 if (!data && !cmd->busy_timeout)
928 target_timeout = sdhci_target_timeout(host, cmd, data);
931 * Figure out needed cycles.
932 * We do this in steps in order to fit inside a 32 bit int.
933 * The first step is the minimum timeout, which will have a
934 * minimum resolution of 6 bits:
935 * (1) 2^13*1000 > 2^22,
936 * (2) host->timeout_clk < 2^16
941 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
942 while (current_timeout < target_timeout) {
944 current_timeout <<= 1;
950 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
951 DBG("Too large timeout 0x%x requested for CMD%d!\n",
961 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
963 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
964 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
966 if (host->flags & SDHCI_REQ_USE_DMA)
967 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
969 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
971 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
972 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
974 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
976 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
977 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
980 static void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
983 host->ier |= SDHCI_INT_DATA_TIMEOUT;
985 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
986 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
987 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
990 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
994 if (host->ops->set_timeout) {
995 host->ops->set_timeout(host, cmd);
997 bool too_big = false;
999 count = sdhci_calc_timeout(host, cmd, &too_big);
1002 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1003 sdhci_calc_sw_timeout(host, cmd);
1004 sdhci_set_data_timeout_irq(host, false);
1005 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1006 sdhci_set_data_timeout_irq(host, true);
1009 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1013 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1015 struct mmc_data *data = cmd->data;
1017 host->data_timeout = 0;
1019 if (sdhci_data_line_cmd(cmd))
1020 sdhci_set_timeout(host, cmd);
1025 WARN_ON(host->data);
1028 BUG_ON(data->blksz * data->blocks > 524288);
1029 BUG_ON(data->blksz > host->mmc->max_blk_size);
1030 BUG_ON(data->blocks > 65535);
1033 host->data_early = 0;
1034 host->data->bytes_xfered = 0;
1036 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1037 struct scatterlist *sg;
1038 unsigned int length_mask, offset_mask;
1041 host->flags |= SDHCI_REQ_USE_DMA;
1044 * FIXME: This doesn't account for merging when mapping the
1047 * The assumption here being that alignment and lengths are
1048 * the same after DMA mapping to device address space.
1052 if (host->flags & SDHCI_USE_ADMA) {
1053 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1056 * As we use up to 3 byte chunks to work
1057 * around alignment problems, we need to
1058 * check the offset as well.
1063 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1065 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1069 if (unlikely(length_mask | offset_mask)) {
1070 for_each_sg(data->sg, sg, data->sg_len, i) {
1071 if (sg->length & length_mask) {
1072 DBG("Reverting to PIO because of transfer size (%d)\n",
1074 host->flags &= ~SDHCI_REQ_USE_DMA;
1077 if (sg->offset & offset_mask) {
1078 DBG("Reverting to PIO because of bad alignment\n");
1079 host->flags &= ~SDHCI_REQ_USE_DMA;
1086 if (host->flags & SDHCI_REQ_USE_DMA) {
1087 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1091 * This only happens when someone fed
1092 * us an invalid request.
1095 host->flags &= ~SDHCI_REQ_USE_DMA;
1096 } else if (host->flags & SDHCI_USE_ADMA) {
1097 sdhci_adma_table_pre(host, data, sg_cnt);
1099 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
1100 if (host->flags & SDHCI_USE_64_BIT_DMA)
1102 (u64)host->adma_addr >> 32,
1103 SDHCI_ADMA_ADDRESS_HI);
1105 WARN_ON(sg_cnt != 1);
1106 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1110 sdhci_config_dma(host);
1112 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1115 flags = SG_MITER_ATOMIC;
1116 if (host->data->flags & MMC_DATA_READ)
1117 flags |= SG_MITER_TO_SG;
1119 flags |= SG_MITER_FROM_SG;
1120 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1121 host->blocks = data->blocks;
1124 sdhci_set_transfer_irqs(host);
1126 /* Set the DMA boundary value and block size */
1127 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1131 * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1132 * can be supported, in that case 16-bit block count register must be 0.
1134 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1135 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1136 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1137 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1138 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1140 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1144 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1145 struct mmc_request *mrq)
1147 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1148 !mrq->cap_cmd_during_tfr;
1151 static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1152 struct mmc_command *cmd,
1155 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1156 (cmd->opcode != SD_IO_RW_EXTENDED);
1157 bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1161 * In case of Version 4.10 or later, use of 'Auto CMD Auto
1162 * Select' is recommended rather than use of 'Auto CMD12
1163 * Enable' or 'Auto CMD23 Enable'.
1165 if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) {
1166 *mode |= SDHCI_TRNS_AUTO_SEL;
1168 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1170 ctrl2 |= SDHCI_CMD23_ENABLE;
1172 ctrl2 &= ~SDHCI_CMD23_ENABLE;
1173 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1179 * If we are sending CMD23, CMD12 never gets sent
1180 * on successful completion (so no Auto-CMD12).
1183 *mode |= SDHCI_TRNS_AUTO_CMD12;
1185 *mode |= SDHCI_TRNS_AUTO_CMD23;
1188 static void sdhci_set_transfer_mode(struct sdhci_host *host,
1189 struct mmc_command *cmd)
1192 struct mmc_data *data = cmd->data;
1196 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1197 /* must not clear SDHCI_TRANSFER_MODE when tuning */
1198 if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1199 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1201 /* clear Auto CMD settings for no data CMDs */
1202 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1203 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1204 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1209 WARN_ON(!host->data);
1211 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1212 mode = SDHCI_TRNS_BLK_CNT_EN;
1214 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1215 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1216 sdhci_auto_cmd_select(host, cmd, &mode);
1217 if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23))
1218 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1221 if (data->flags & MMC_DATA_READ)
1222 mode |= SDHCI_TRNS_READ;
1223 if (host->flags & SDHCI_REQ_USE_DMA)
1224 mode |= SDHCI_TRNS_DMA;
1226 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1229 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1231 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1232 ((mrq->cmd && mrq->cmd->error) ||
1233 (mrq->sbc && mrq->sbc->error) ||
1234 (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1235 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1238 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1242 if (host->cmd && host->cmd->mrq == mrq)
1245 if (host->data_cmd && host->data_cmd->mrq == mrq)
1246 host->data_cmd = NULL;
1248 if (host->data && host->data->mrq == mrq)
1251 if (sdhci_needs_reset(host, mrq))
1252 host->pending_reset = true;
1254 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1255 if (host->mrqs_done[i] == mrq) {
1261 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1262 if (!host->mrqs_done[i]) {
1263 host->mrqs_done[i] = mrq;
1268 WARN_ON(i >= SDHCI_MAX_MRQS);
1270 sdhci_del_timer(host, mrq);
1272 if (!sdhci_has_requests(host))
1273 sdhci_led_deactivate(host);
1276 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1278 __sdhci_finish_mrq(host, mrq);
1280 queue_work(host->complete_wq, &host->complete_work);
1283 static void sdhci_finish_data(struct sdhci_host *host)
1285 struct mmc_command *data_cmd = host->data_cmd;
1286 struct mmc_data *data = host->data;
1289 host->data_cmd = NULL;
1292 * The controller needs a reset of internal state machines upon error
1296 if (!host->cmd || host->cmd == data_cmd)
1297 sdhci_do_reset(host, SDHCI_RESET_CMD);
1298 sdhci_do_reset(host, SDHCI_RESET_DATA);
1301 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1302 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1303 sdhci_adma_table_post(host, data);
1306 * The specification states that the block count register must
1307 * be updated, but it does not specify at what point in the
1308 * data flow. That makes the register entirely useless to read
1309 * back so we have to assume that nothing made it to the card
1310 * in the event of an error.
1313 data->bytes_xfered = 0;
1315 data->bytes_xfered = data->blksz * data->blocks;
1318 * Need to send CMD12 if -
1319 * a) open-ended multiblock transfer (no CMD23)
1320 * b) error in multiblock transfer
1326 * 'cap_cmd_during_tfr' request must not use the command line
1327 * after mmc_command_done() has been called. It is upper layer's
1328 * responsibility to send the stop command if required.
1330 if (data->mrq->cap_cmd_during_tfr) {
1331 __sdhci_finish_mrq(host, data->mrq);
1333 /* Avoid triggering warning in sdhci_send_command() */
1335 sdhci_send_command(host, data->stop);
1338 __sdhci_finish_mrq(host, data->mrq);
1342 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1346 unsigned long timeout;
1350 /* Initially, a command has no error */
1353 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1354 cmd->opcode == MMC_STOP_TRANSMISSION)
1355 cmd->flags |= MMC_RSP_BUSY;
1357 /* Wait max 10 ms */
1360 mask = SDHCI_CMD_INHIBIT;
1361 if (sdhci_data_line_cmd(cmd))
1362 mask |= SDHCI_DATA_INHIBIT;
1364 /* We shouldn't wait for data inihibit for stop commands, even
1365 though they might use busy signaling */
1366 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1367 mask &= ~SDHCI_DATA_INHIBIT;
1369 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1371 pr_err("%s: Controller never released inhibit bit(s).\n",
1372 mmc_hostname(host->mmc));
1373 sdhci_dumpregs(host);
1375 sdhci_finish_mrq(host, cmd->mrq);
1383 if (sdhci_data_line_cmd(cmd)) {
1384 WARN_ON(host->data_cmd);
1385 host->data_cmd = cmd;
1388 sdhci_prepare_data(host, cmd);
1390 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1392 sdhci_set_transfer_mode(host, cmd);
1394 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1395 pr_err("%s: Unsupported response type!\n",
1396 mmc_hostname(host->mmc));
1397 cmd->error = -EINVAL;
1398 sdhci_finish_mrq(host, cmd->mrq);
1402 if (!(cmd->flags & MMC_RSP_PRESENT))
1403 flags = SDHCI_CMD_RESP_NONE;
1404 else if (cmd->flags & MMC_RSP_136)
1405 flags = SDHCI_CMD_RESP_LONG;
1406 else if (cmd->flags & MMC_RSP_BUSY)
1407 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1409 flags = SDHCI_CMD_RESP_SHORT;
1411 if (cmd->flags & MMC_RSP_CRC)
1412 flags |= SDHCI_CMD_CRC;
1413 if (cmd->flags & MMC_RSP_OPCODE)
1414 flags |= SDHCI_CMD_INDEX;
1416 /* CMD19 is special in that the Data Present Select should be set */
1417 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1418 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1419 flags |= SDHCI_CMD_DATA;
1422 if (host->data_timeout)
1423 timeout += nsecs_to_jiffies(host->data_timeout);
1424 else if (!cmd->data && cmd->busy_timeout > 9000)
1425 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1428 sdhci_mod_timer(host, cmd->mrq, timeout);
1430 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1432 EXPORT_SYMBOL_GPL(sdhci_send_command);
1434 static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1438 for (i = 0; i < 4; i++) {
1439 reg = SDHCI_RESPONSE + (3 - i) * 4;
1440 cmd->resp[i] = sdhci_readl(host, reg);
1443 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1446 /* CRC is stripped so we need to do some shifting */
1447 for (i = 0; i < 4; i++) {
1450 cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1454 static void sdhci_finish_command(struct sdhci_host *host)
1456 struct mmc_command *cmd = host->cmd;
1460 if (cmd->flags & MMC_RSP_PRESENT) {
1461 if (cmd->flags & MMC_RSP_136) {
1462 sdhci_read_rsp_136(host, cmd);
1464 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1468 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1469 mmc_command_done(host->mmc, cmd->mrq);
1472 * The host can send and interrupt when the busy state has
1473 * ended, allowing us to wait without wasting CPU cycles.
1474 * The busy signal uses DAT0 so this is similar to waiting
1475 * for data to complete.
1477 * Note: The 1.0 specification is a bit ambiguous about this
1478 * feature so there might be some problems with older
1481 if (cmd->flags & MMC_RSP_BUSY) {
1483 DBG("Cannot wait for busy signal when also doing a data transfer");
1484 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1485 cmd == host->data_cmd) {
1486 /* Command complete before busy is ended */
1491 /* Finished CMD23, now send actual command. */
1492 if (cmd == cmd->mrq->sbc) {
1493 sdhci_send_command(host, cmd->mrq->cmd);
1496 /* Processed actual command. */
1497 if (host->data && host->data_early)
1498 sdhci_finish_data(host);
1501 __sdhci_finish_mrq(host, cmd->mrq);
1505 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1509 switch (host->timing) {
1510 case MMC_TIMING_UHS_SDR12:
1511 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1513 case MMC_TIMING_UHS_SDR25:
1514 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1516 case MMC_TIMING_UHS_SDR50:
1517 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1519 case MMC_TIMING_UHS_SDR104:
1520 case MMC_TIMING_MMC_HS200:
1521 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1523 case MMC_TIMING_UHS_DDR50:
1524 case MMC_TIMING_MMC_DDR52:
1525 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1527 case MMC_TIMING_MMC_HS400:
1528 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1531 pr_warn("%s: Invalid UHS-I mode selected\n",
1532 mmc_hostname(host->mmc));
1533 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1539 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1540 unsigned int *actual_clock)
1542 int div = 0; /* Initialized for compiler warning */
1543 int real_div = div, clk_mul = 1;
1545 bool switch_base_clk = false;
1547 if (host->version >= SDHCI_SPEC_300) {
1548 if (host->preset_enabled) {
1551 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1552 pre_val = sdhci_get_preset_value(host);
1553 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1554 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1555 if (host->clk_mul &&
1556 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1557 clk = SDHCI_PROG_CLOCK_MODE;
1559 clk_mul = host->clk_mul;
1561 real_div = max_t(int, 1, div << 1);
1567 * Check if the Host Controller supports Programmable Clock
1570 if (host->clk_mul) {
1571 for (div = 1; div <= 1024; div++) {
1572 if ((host->max_clk * host->clk_mul / div)
1576 if ((host->max_clk * host->clk_mul / div) <= clock) {
1578 * Set Programmable Clock Mode in the Clock
1581 clk = SDHCI_PROG_CLOCK_MODE;
1583 clk_mul = host->clk_mul;
1587 * Divisor can be too small to reach clock
1588 * speed requirement. Then use the base clock.
1590 switch_base_clk = true;
1594 if (!host->clk_mul || switch_base_clk) {
1595 /* Version 3.00 divisors must be a multiple of 2. */
1596 if (host->max_clk <= clock)
1599 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1601 if ((host->max_clk / div) <= clock)
1607 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1608 && !div && host->max_clk <= 25000000)
1612 /* Version 2.00 divisors must be a power of 2. */
1613 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1614 if ((host->max_clk / div) <= clock)
1623 *actual_clock = (host->max_clk * clk_mul) / real_div;
1624 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1625 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1626 << SDHCI_DIVIDER_HI_SHIFT;
1630 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1632 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1636 clk |= SDHCI_CLOCK_INT_EN;
1637 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1639 /* Wait max 20 ms */
1640 timeout = ktime_add_ms(ktime_get(), 20);
1642 bool timedout = ktime_after(ktime_get(), timeout);
1644 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1645 if (clk & SDHCI_CLOCK_INT_STABLE)
1648 pr_err("%s: Internal clock never stabilised.\n",
1649 mmc_hostname(host->mmc));
1650 sdhci_dumpregs(host);
1656 clk |= SDHCI_CLOCK_CARD_EN;
1657 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1659 EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1661 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1665 host->mmc->actual_clock = 0;
1667 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1672 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1673 sdhci_enable_clk(host, clk);
1675 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1677 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1680 struct mmc_host *mmc = host->mmc;
1682 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1684 if (mode != MMC_POWER_OFF)
1685 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1687 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1690 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1695 if (mode != MMC_POWER_OFF) {
1697 case MMC_VDD_165_195:
1699 * Without a regulator, SDHCI does not support 2.0v
1700 * so we only get here if the driver deliberately
1701 * added the 2.0v range to ocr_avail. Map it to 1.8v
1702 * for the purpose of turning on the power.
1705 pwr = SDHCI_POWER_180;
1709 pwr = SDHCI_POWER_300;
1713 pwr = SDHCI_POWER_330;
1716 WARN(1, "%s: Invalid vdd %#x\n",
1717 mmc_hostname(host->mmc), vdd);
1722 if (host->pwr == pwr)
1728 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1729 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1730 sdhci_runtime_pm_bus_off(host);
1733 * Spec says that we should clear the power reg before setting
1734 * a new value. Some controllers don't seem to like this though.
1736 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1737 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1740 * At least the Marvell CaFe chip gets confused if we set the
1741 * voltage and set turn on power at the same time, so set the
1744 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1745 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1747 pwr |= SDHCI_POWER_ON;
1749 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1751 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1752 sdhci_runtime_pm_bus_on(host);
1755 * Some controllers need an extra 10ms delay of 10ms before
1756 * they can apply clock after applying power
1758 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1762 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
1764 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1767 if (IS_ERR(host->mmc->supply.vmmc))
1768 sdhci_set_power_noreg(host, mode, vdd);
1770 sdhci_set_power_reg(host, mode, vdd);
1772 EXPORT_SYMBOL_GPL(sdhci_set_power);
1774 /*****************************************************************************\
1778 \*****************************************************************************/
1780 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1782 struct sdhci_host *host;
1784 unsigned long flags;
1786 host = mmc_priv(mmc);
1788 /* Firstly check card presence */
1789 present = mmc->ops->get_cd(mmc);
1791 spin_lock_irqsave(&host->lock, flags);
1793 sdhci_led_activate(host);
1796 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1797 * requests if Auto-CMD12 is enabled.
1799 if (sdhci_auto_cmd12(host, mrq)) {
1801 mrq->data->stop = NULL;
1806 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1807 mrq->cmd->error = -ENOMEDIUM;
1808 sdhci_finish_mrq(host, mrq);
1810 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1811 sdhci_send_command(host, mrq->sbc);
1813 sdhci_send_command(host, mrq->cmd);
1816 spin_unlock_irqrestore(&host->lock, flags);
1818 EXPORT_SYMBOL_GPL(sdhci_request);
1820 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1824 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1825 if (width == MMC_BUS_WIDTH_8) {
1826 ctrl &= ~SDHCI_CTRL_4BITBUS;
1827 ctrl |= SDHCI_CTRL_8BITBUS;
1829 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
1830 ctrl &= ~SDHCI_CTRL_8BITBUS;
1831 if (width == MMC_BUS_WIDTH_4)
1832 ctrl |= SDHCI_CTRL_4BITBUS;
1834 ctrl &= ~SDHCI_CTRL_4BITBUS;
1836 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1838 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1840 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1844 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1845 /* Select Bus Speed Mode for host */
1846 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1847 if ((timing == MMC_TIMING_MMC_HS200) ||
1848 (timing == MMC_TIMING_UHS_SDR104))
1849 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1850 else if (timing == MMC_TIMING_UHS_SDR12)
1851 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1852 else if (timing == MMC_TIMING_SD_HS ||
1853 timing == MMC_TIMING_MMC_HS ||
1854 timing == MMC_TIMING_UHS_SDR25)
1855 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1856 else if (timing == MMC_TIMING_UHS_SDR50)
1857 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1858 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1859 (timing == MMC_TIMING_MMC_DDR52))
1860 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1861 else if (timing == MMC_TIMING_MMC_HS400)
1862 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1863 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1865 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1867 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1869 struct sdhci_host *host = mmc_priv(mmc);
1872 if (ios->power_mode == MMC_POWER_UNDEFINED)
1875 if (host->flags & SDHCI_DEVICE_DEAD) {
1876 if (!IS_ERR(mmc->supply.vmmc) &&
1877 ios->power_mode == MMC_POWER_OFF)
1878 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1883 * Reset the chip on each power off.
1884 * Should clear out any weird states.
1886 if (ios->power_mode == MMC_POWER_OFF) {
1887 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1891 if (host->version >= SDHCI_SPEC_300 &&
1892 (ios->power_mode == MMC_POWER_UP) &&
1893 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1894 sdhci_enable_preset_value(host, false);
1896 if (!ios->clock || ios->clock != host->clock) {
1897 host->ops->set_clock(host, ios->clock);
1898 host->clock = ios->clock;
1900 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1902 host->timeout_clk = host->mmc->actual_clock ?
1903 host->mmc->actual_clock / 1000 :
1905 host->mmc->max_busy_timeout =
1906 host->ops->get_max_timeout_count ?
1907 host->ops->get_max_timeout_count(host) :
1909 host->mmc->max_busy_timeout /= host->timeout_clk;
1913 if (host->ops->set_power)
1914 host->ops->set_power(host, ios->power_mode, ios->vdd);
1916 sdhci_set_power(host, ios->power_mode, ios->vdd);
1918 if (host->ops->platform_send_init_74_clocks)
1919 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1921 host->ops->set_bus_width(host, ios->bus_width);
1923 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1925 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
1926 if (ios->timing == MMC_TIMING_SD_HS ||
1927 ios->timing == MMC_TIMING_MMC_HS ||
1928 ios->timing == MMC_TIMING_MMC_HS400 ||
1929 ios->timing == MMC_TIMING_MMC_HS200 ||
1930 ios->timing == MMC_TIMING_MMC_DDR52 ||
1931 ios->timing == MMC_TIMING_UHS_SDR50 ||
1932 ios->timing == MMC_TIMING_UHS_SDR104 ||
1933 ios->timing == MMC_TIMING_UHS_DDR50 ||
1934 ios->timing == MMC_TIMING_UHS_SDR25)
1935 ctrl |= SDHCI_CTRL_HISPD;
1937 ctrl &= ~SDHCI_CTRL_HISPD;
1940 if (host->version >= SDHCI_SPEC_300) {
1943 if (!host->preset_enabled) {
1944 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1946 * We only need to set Driver Strength if the
1947 * preset value enable is not set.
1949 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1950 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1951 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1952 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1953 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1954 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1955 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1956 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1957 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1958 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1960 pr_warn("%s: invalid driver type, default to driver type B\n",
1962 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1965 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1968 * According to SDHC Spec v3.00, if the Preset Value
1969 * Enable in the Host Control 2 register is set, we
1970 * need to reset SD Clock Enable before changing High
1971 * Speed Enable to avoid generating clock gliches.
1974 /* Reset SD Clock Enable */
1975 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1976 clk &= ~SDHCI_CLOCK_CARD_EN;
1977 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1979 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1981 /* Re-enable SD Clock */
1982 host->ops->set_clock(host, host->clock);
1985 /* Reset SD Clock Enable */
1986 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1987 clk &= ~SDHCI_CLOCK_CARD_EN;
1988 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1990 host->ops->set_uhs_signaling(host, ios->timing);
1991 host->timing = ios->timing;
1993 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1994 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1995 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1996 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1997 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1998 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1999 (ios->timing == MMC_TIMING_MMC_DDR52))) {
2002 sdhci_enable_preset_value(host, true);
2003 preset = sdhci_get_preset_value(host);
2004 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
2005 >> SDHCI_PRESET_DRV_SHIFT;
2008 /* Re-enable SD Clock */
2009 host->ops->set_clock(host, host->clock);
2011 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2014 * Some (ENE) controllers go apeshit on some ios operation,
2015 * signalling timeout and CRC errors even on CMD0. Resetting
2016 * it on each ios seems to solve the problem.
2018 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
2019 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2021 EXPORT_SYMBOL_GPL(sdhci_set_ios);
2023 static int sdhci_get_cd(struct mmc_host *mmc)
2025 struct sdhci_host *host = mmc_priv(mmc);
2026 int gpio_cd = mmc_gpio_get_cd(mmc);
2028 if (host->flags & SDHCI_DEVICE_DEAD)
2031 /* If nonremovable, assume that the card is always present. */
2032 if (!mmc_card_is_removable(host->mmc))
2036 * Try slot gpio detect, if defined it take precedence
2037 * over build in controller functionality
2042 /* If polling, assume that the card is always present. */
2043 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2046 /* Host native card detect */
2047 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2050 static int sdhci_check_ro(struct sdhci_host *host)
2052 unsigned long flags;
2055 spin_lock_irqsave(&host->lock, flags);
2057 if (host->flags & SDHCI_DEVICE_DEAD)
2059 else if (host->ops->get_ro)
2060 is_readonly = host->ops->get_ro(host);
2061 else if (mmc_can_gpio_ro(host->mmc))
2062 is_readonly = mmc_gpio_get_ro(host->mmc);
2064 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2065 & SDHCI_WRITE_PROTECT);
2067 spin_unlock_irqrestore(&host->lock, flags);
2069 /* This quirk needs to be replaced by a callback-function later */
2070 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2071 !is_readonly : is_readonly;
2074 #define SAMPLE_COUNT 5
2076 static int sdhci_get_ro(struct mmc_host *mmc)
2078 struct sdhci_host *host = mmc_priv(mmc);
2081 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2082 return sdhci_check_ro(host);
2085 for (i = 0; i < SAMPLE_COUNT; i++) {
2086 if (sdhci_check_ro(host)) {
2087 if (++ro_count > SAMPLE_COUNT / 2)
2095 static void sdhci_hw_reset(struct mmc_host *mmc)
2097 struct sdhci_host *host = mmc_priv(mmc);
2099 if (host->ops && host->ops->hw_reset)
2100 host->ops->hw_reset(host);
2103 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2105 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2107 host->ier |= SDHCI_INT_CARD_INT;
2109 host->ier &= ~SDHCI_INT_CARD_INT;
2111 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2112 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2116 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2118 struct sdhci_host *host = mmc_priv(mmc);
2119 unsigned long flags;
2122 pm_runtime_get_noresume(host->mmc->parent);
2124 spin_lock_irqsave(&host->lock, flags);
2126 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
2128 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
2130 sdhci_enable_sdio_irq_nolock(host, enable);
2131 spin_unlock_irqrestore(&host->lock, flags);
2134 pm_runtime_put_noidle(host->mmc->parent);
2136 EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2138 static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2140 struct sdhci_host *host = mmc_priv(mmc);
2141 unsigned long flags;
2143 spin_lock_irqsave(&host->lock, flags);
2144 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2145 sdhci_enable_sdio_irq_nolock(host, true);
2146 spin_unlock_irqrestore(&host->lock, flags);
2149 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2150 struct mmc_ios *ios)
2152 struct sdhci_host *host = mmc_priv(mmc);
2157 * Signal Voltage Switching is only applicable for Host Controllers
2160 if (host->version < SDHCI_SPEC_300)
2163 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2165 switch (ios->signal_voltage) {
2166 case MMC_SIGNAL_VOLTAGE_330:
2167 if (!(host->flags & SDHCI_SIGNALING_330))
2169 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2170 ctrl &= ~SDHCI_CTRL_VDD_180;
2171 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2173 if (!IS_ERR(mmc->supply.vqmmc)) {
2174 ret = mmc_regulator_set_vqmmc(mmc, ios);
2176 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2182 usleep_range(5000, 5500);
2184 /* 3.3V regulator output should be stable within 5 ms */
2185 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2186 if (!(ctrl & SDHCI_CTRL_VDD_180))
2189 pr_warn("%s: 3.3V regulator output did not became stable\n",
2193 case MMC_SIGNAL_VOLTAGE_180:
2194 if (!(host->flags & SDHCI_SIGNALING_180))
2196 if (!IS_ERR(mmc->supply.vqmmc)) {
2197 ret = mmc_regulator_set_vqmmc(mmc, ios);
2199 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2206 * Enable 1.8V Signal Enable in the Host Control2
2209 ctrl |= SDHCI_CTRL_VDD_180;
2210 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2212 /* Some controller need to do more when switching */
2213 if (host->ops->voltage_switch)
2214 host->ops->voltage_switch(host);
2216 /* 1.8V regulator output should be stable within 5 ms */
2217 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2218 if (ctrl & SDHCI_CTRL_VDD_180)
2221 pr_warn("%s: 1.8V regulator output did not became stable\n",
2225 case MMC_SIGNAL_VOLTAGE_120:
2226 if (!(host->flags & SDHCI_SIGNALING_120))
2228 if (!IS_ERR(mmc->supply.vqmmc)) {
2229 ret = mmc_regulator_set_vqmmc(mmc, ios);
2231 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2238 /* No signal voltage switch required */
2242 EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2244 static int sdhci_card_busy(struct mmc_host *mmc)
2246 struct sdhci_host *host = mmc_priv(mmc);
2249 /* Check whether DAT[0] is 0 */
2250 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2252 return !(present_state & SDHCI_DATA_0_LVL_MASK);
2255 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2257 struct sdhci_host *host = mmc_priv(mmc);
2258 unsigned long flags;
2260 spin_lock_irqsave(&host->lock, flags);
2261 host->flags |= SDHCI_HS400_TUNING;
2262 spin_unlock_irqrestore(&host->lock, flags);
2267 void sdhci_start_tuning(struct sdhci_host *host)
2271 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2272 ctrl |= SDHCI_CTRL_EXEC_TUNING;
2273 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2274 ctrl |= SDHCI_CTRL_TUNED_CLK;
2275 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2278 * As per the Host Controller spec v3.00, tuning command
2279 * generates Buffer Read Ready interrupt, so enable that.
2281 * Note: The spec clearly says that when tuning sequence
2282 * is being performed, the controller does not generate
2283 * interrupts other than Buffer Read Ready interrupt. But
2284 * to make sure we don't hit a controller bug, we _only_
2285 * enable Buffer Read Ready interrupt here.
2287 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2288 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2290 EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2292 void sdhci_end_tuning(struct sdhci_host *host)
2294 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2295 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2297 EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2299 void sdhci_reset_tuning(struct sdhci_host *host)
2303 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2304 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2305 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2306 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2308 EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2310 static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2312 sdhci_reset_tuning(host);
2314 sdhci_do_reset(host, SDHCI_RESET_CMD);
2315 sdhci_do_reset(host, SDHCI_RESET_DATA);
2317 sdhci_end_tuning(host);
2319 mmc_abort_tuning(host->mmc, opcode);
2323 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2324 * tuning command does not have a data payload (or rather the hardware does it
2325 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2326 * interrupt setup is different to other commands and there is no timeout
2327 * interrupt so special handling is needed.
2329 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2331 struct mmc_host *mmc = host->mmc;
2332 struct mmc_command cmd = {};
2333 struct mmc_request mrq = {};
2334 unsigned long flags;
2335 u32 b = host->sdma_boundary;
2337 spin_lock_irqsave(&host->lock, flags);
2339 cmd.opcode = opcode;
2340 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2345 * In response to CMD19, the card sends 64 bytes of tuning
2346 * block to the Host Controller. So we set the block size
2349 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2350 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2351 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2353 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2356 * The tuning block is sent by the card to the host controller.
2357 * So we set the TRNS_READ bit in the Transfer Mode register.
2358 * This also takes care of setting DMA Enable and Multi Block
2359 * Select in the same register to 0.
2361 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2363 sdhci_send_command(host, &cmd);
2367 sdhci_del_timer(host, &mrq);
2369 host->tuning_done = 0;
2371 spin_unlock_irqrestore(&host->lock, flags);
2373 /* Wait for Buffer Read Ready interrupt */
2374 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2375 msecs_to_jiffies(50));
2378 EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2380 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2385 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2386 * of loops reaches tuning loop count.
2388 for (i = 0; i < host->tuning_loop_count; i++) {
2391 sdhci_send_tuning(host, opcode);
2393 if (!host->tuning_done) {
2394 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2395 mmc_hostname(host->mmc));
2396 sdhci_abort_tuning(host, opcode);
2400 /* Spec does not require a delay between tuning cycles */
2401 if (host->tuning_delay > 0)
2402 mdelay(host->tuning_delay);
2404 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2405 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2406 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2407 return 0; /* Success! */
2413 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2414 mmc_hostname(host->mmc));
2415 sdhci_reset_tuning(host);
2419 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2421 struct sdhci_host *host = mmc_priv(mmc);
2423 unsigned int tuning_count = 0;
2426 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2428 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2429 tuning_count = host->tuning_count;
2432 * The Host Controller needs tuning in case of SDR104 and DDR50
2433 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2434 * the Capabilities register.
2435 * If the Host Controller supports the HS200 mode then the
2436 * tuning function has to be executed.
2438 switch (host->timing) {
2439 /* HS400 tuning is done in HS200 mode */
2440 case MMC_TIMING_MMC_HS400:
2444 case MMC_TIMING_MMC_HS200:
2446 * Periodic re-tuning for HS400 is not expected to be needed, so
2453 case MMC_TIMING_UHS_SDR104:
2454 case MMC_TIMING_UHS_DDR50:
2457 case MMC_TIMING_UHS_SDR50:
2458 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2466 if (host->ops->platform_execute_tuning) {
2467 err = host->ops->platform_execute_tuning(host, opcode);
2471 host->mmc->retune_period = tuning_count;
2473 if (host->tuning_delay < 0)
2474 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2476 sdhci_start_tuning(host);
2478 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2480 sdhci_end_tuning(host);
2482 host->flags &= ~SDHCI_HS400_TUNING;
2486 EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2488 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2490 /* Host Controller v3.00 defines preset value registers */
2491 if (host->version < SDHCI_SPEC_300)
2495 * We only enable or disable Preset Value if they are not already
2496 * enabled or disabled respectively. Otherwise, we bail out.
2498 if (host->preset_enabled != enable) {
2499 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2502 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2504 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2506 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2509 host->flags |= SDHCI_PV_ENABLED;
2511 host->flags &= ~SDHCI_PV_ENABLED;
2513 host->preset_enabled = enable;
2517 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2520 struct sdhci_host *host = mmc_priv(mmc);
2521 struct mmc_data *data = mrq->data;
2523 if (data->host_cookie != COOKIE_UNMAPPED)
2524 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2525 mmc_get_dma_dir(data));
2527 data->host_cookie = COOKIE_UNMAPPED;
2530 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2532 struct sdhci_host *host = mmc_priv(mmc);
2534 mrq->data->host_cookie = COOKIE_UNMAPPED;
2537 * No pre-mapping in the pre hook if we're using the bounce buffer,
2538 * for that we would need two bounce buffers since one buffer is
2539 * in flight when this is getting called.
2541 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2542 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2545 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2547 if (host->data_cmd) {
2548 host->data_cmd->error = err;
2549 sdhci_finish_mrq(host, host->data_cmd->mrq);
2553 host->cmd->error = err;
2554 sdhci_finish_mrq(host, host->cmd->mrq);
2558 static void sdhci_card_event(struct mmc_host *mmc)
2560 struct sdhci_host *host = mmc_priv(mmc);
2561 unsigned long flags;
2564 /* First check if client has provided their own card event */
2565 if (host->ops->card_event)
2566 host->ops->card_event(host);
2568 present = mmc->ops->get_cd(mmc);
2570 spin_lock_irqsave(&host->lock, flags);
2572 /* Check sdhci_has_requests() first in case we are runtime suspended */
2573 if (sdhci_has_requests(host) && !present) {
2574 pr_err("%s: Card removed during transfer!\n",
2575 mmc_hostname(host->mmc));
2576 pr_err("%s: Resetting controller.\n",
2577 mmc_hostname(host->mmc));
2579 sdhci_do_reset(host, SDHCI_RESET_CMD);
2580 sdhci_do_reset(host, SDHCI_RESET_DATA);
2582 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2585 spin_unlock_irqrestore(&host->lock, flags);
2588 static const struct mmc_host_ops sdhci_ops = {
2589 .request = sdhci_request,
2590 .post_req = sdhci_post_req,
2591 .pre_req = sdhci_pre_req,
2592 .set_ios = sdhci_set_ios,
2593 .get_cd = sdhci_get_cd,
2594 .get_ro = sdhci_get_ro,
2595 .hw_reset = sdhci_hw_reset,
2596 .enable_sdio_irq = sdhci_enable_sdio_irq,
2597 .ack_sdio_irq = sdhci_ack_sdio_irq,
2598 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2599 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2600 .execute_tuning = sdhci_execute_tuning,
2601 .card_event = sdhci_card_event,
2602 .card_busy = sdhci_card_busy,
2605 /*****************************************************************************\
2609 \*****************************************************************************/
2611 static bool sdhci_request_done(struct sdhci_host *host)
2613 unsigned long flags;
2614 struct mmc_request *mrq;
2617 spin_lock_irqsave(&host->lock, flags);
2619 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2620 mrq = host->mrqs_done[i];
2626 spin_unlock_irqrestore(&host->lock, flags);
2631 * Always unmap the data buffers if they were mapped by
2632 * sdhci_prepare_data() whenever we finish with a request.
2633 * This avoids leaking DMA mappings on error.
2635 if (host->flags & SDHCI_REQ_USE_DMA) {
2636 struct mmc_data *data = mrq->data;
2638 if (data && data->host_cookie == COOKIE_MAPPED) {
2639 if (host->bounce_buffer) {
2641 * On reads, copy the bounced data into the
2644 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
2645 unsigned int length = data->bytes_xfered;
2647 if (length > host->bounce_buffer_size) {
2648 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
2649 mmc_hostname(host->mmc),
2650 host->bounce_buffer_size,
2651 data->bytes_xfered);
2652 /* Cap it down and continue */
2653 length = host->bounce_buffer_size;
2655 dma_sync_single_for_cpu(
2658 host->bounce_buffer_size,
2660 sg_copy_from_buffer(data->sg,
2662 host->bounce_buffer,
2665 /* No copying, just switch ownership */
2666 dma_sync_single_for_cpu(
2669 host->bounce_buffer_size,
2670 mmc_get_dma_dir(data));
2673 /* Unmap the raw data */
2674 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
2676 mmc_get_dma_dir(data));
2678 data->host_cookie = COOKIE_UNMAPPED;
2683 * The controller needs a reset of internal state machines
2684 * upon error conditions.
2686 if (sdhci_needs_reset(host, mrq)) {
2688 * Do not finish until command and data lines are available for
2689 * reset. Note there can only be one other mrq, so it cannot
2690 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2691 * would both be null.
2693 if (host->cmd || host->data_cmd) {
2694 spin_unlock_irqrestore(&host->lock, flags);
2698 /* Some controllers need this kick or reset won't work here */
2699 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2700 /* This is to force an update */
2701 host->ops->set_clock(host, host->clock);
2703 /* Spec says we should do both at the same time, but Ricoh
2704 controllers do not like that. */
2705 sdhci_do_reset(host, SDHCI_RESET_CMD);
2706 sdhci_do_reset(host, SDHCI_RESET_DATA);
2708 host->pending_reset = false;
2711 host->mrqs_done[i] = NULL;
2713 spin_unlock_irqrestore(&host->lock, flags);
2715 mmc_request_done(host->mmc, mrq);
2720 static void sdhci_complete_work(struct work_struct *work)
2722 struct sdhci_host *host = container_of(work, struct sdhci_host,
2725 while (!sdhci_request_done(host))
2729 static void sdhci_timeout_timer(struct timer_list *t)
2731 struct sdhci_host *host;
2732 unsigned long flags;
2734 host = from_timer(host, t, timer);
2736 spin_lock_irqsave(&host->lock, flags);
2738 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2739 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2740 mmc_hostname(host->mmc));
2741 sdhci_dumpregs(host);
2743 host->cmd->error = -ETIMEDOUT;
2744 sdhci_finish_mrq(host, host->cmd->mrq);
2747 spin_unlock_irqrestore(&host->lock, flags);
2750 static void sdhci_timeout_data_timer(struct timer_list *t)
2752 struct sdhci_host *host;
2753 unsigned long flags;
2755 host = from_timer(host, t, data_timer);
2757 spin_lock_irqsave(&host->lock, flags);
2759 if (host->data || host->data_cmd ||
2760 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2761 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2762 mmc_hostname(host->mmc));
2763 sdhci_dumpregs(host);
2766 host->data->error = -ETIMEDOUT;
2767 sdhci_finish_data(host);
2768 queue_work(host->complete_wq, &host->complete_work);
2769 } else if (host->data_cmd) {
2770 host->data_cmd->error = -ETIMEDOUT;
2771 sdhci_finish_mrq(host, host->data_cmd->mrq);
2773 host->cmd->error = -ETIMEDOUT;
2774 sdhci_finish_mrq(host, host->cmd->mrq);
2778 spin_unlock_irqrestore(&host->lock, flags);
2781 /*****************************************************************************\
2783 * Interrupt handling *
2785 \*****************************************************************************/
2787 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
2789 /* Handle auto-CMD12 error */
2790 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
2791 struct mmc_request *mrq = host->data_cmd->mrq;
2792 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
2793 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
2794 SDHCI_INT_DATA_TIMEOUT :
2797 /* Treat auto-CMD12 error the same as data error */
2798 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
2799 *intmask_p |= data_err_bit;
2806 * SDHCI recovers from errors by resetting the cmd and data
2807 * circuits. Until that is done, there very well might be more
2808 * interrupts, so ignore them in that case.
2810 if (host->pending_reset)
2812 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2813 mmc_hostname(host->mmc), (unsigned)intmask);
2814 sdhci_dumpregs(host);
2818 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2819 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2820 if (intmask & SDHCI_INT_TIMEOUT)
2821 host->cmd->error = -ETIMEDOUT;
2823 host->cmd->error = -EILSEQ;
2825 /* Treat data command CRC error the same as data CRC error */
2826 if (host->cmd->data &&
2827 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2830 *intmask_p |= SDHCI_INT_DATA_CRC;
2834 __sdhci_finish_mrq(host, host->cmd->mrq);
2838 /* Handle auto-CMD23 error */
2839 if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
2840 struct mmc_request *mrq = host->cmd->mrq;
2841 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
2842 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
2846 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
2847 mrq->sbc->error = err;
2848 __sdhci_finish_mrq(host, mrq);
2853 if (intmask & SDHCI_INT_RESPONSE)
2854 sdhci_finish_command(host);
2857 static void sdhci_adma_show_error(struct sdhci_host *host)
2859 void *desc = host->adma_table;
2860 dma_addr_t dma = host->adma_addr;
2862 sdhci_dumpregs(host);
2865 struct sdhci_adma2_64_desc *dma_desc = desc;
2867 if (host->flags & SDHCI_USE_64_BIT_DMA)
2868 SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2869 (unsigned long long)dma,
2870 le32_to_cpu(dma_desc->addr_hi),
2871 le32_to_cpu(dma_desc->addr_lo),
2872 le16_to_cpu(dma_desc->len),
2873 le16_to_cpu(dma_desc->cmd));
2875 SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2876 (unsigned long long)dma,
2877 le32_to_cpu(dma_desc->addr_lo),
2878 le16_to_cpu(dma_desc->len),
2879 le16_to_cpu(dma_desc->cmd));
2881 desc += host->desc_sz;
2882 dma += host->desc_sz;
2884 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2889 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2893 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2894 if (intmask & SDHCI_INT_DATA_AVAIL) {
2895 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2896 if (command == MMC_SEND_TUNING_BLOCK ||
2897 command == MMC_SEND_TUNING_BLOCK_HS200) {
2898 host->tuning_done = 1;
2899 wake_up(&host->buf_ready_int);
2905 struct mmc_command *data_cmd = host->data_cmd;
2908 * The "data complete" interrupt is also used to
2909 * indicate that a busy state has ended. See comment
2910 * above in sdhci_cmd_irq().
2912 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
2913 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2914 host->data_cmd = NULL;
2915 data_cmd->error = -ETIMEDOUT;
2916 __sdhci_finish_mrq(host, data_cmd->mrq);
2919 if (intmask & SDHCI_INT_DATA_END) {
2920 host->data_cmd = NULL;
2922 * Some cards handle busy-end interrupt
2923 * before the command completed, so make
2924 * sure we do things in the proper order.
2926 if (host->cmd == data_cmd)
2929 __sdhci_finish_mrq(host, data_cmd->mrq);
2935 * SDHCI recovers from errors by resetting the cmd and data
2936 * circuits. Until that is done, there very well might be more
2937 * interrupts, so ignore them in that case.
2939 if (host->pending_reset)
2942 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2943 mmc_hostname(host->mmc), (unsigned)intmask);
2944 sdhci_dumpregs(host);
2949 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2950 host->data->error = -ETIMEDOUT;
2951 else if (intmask & SDHCI_INT_DATA_END_BIT)
2952 host->data->error = -EILSEQ;
2953 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2954 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2956 host->data->error = -EILSEQ;
2957 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2958 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
2960 sdhci_adma_show_error(host);
2961 host->data->error = -EIO;
2962 if (host->ops->adma_workaround)
2963 host->ops->adma_workaround(host, intmask);
2966 if (host->data->error)
2967 sdhci_finish_data(host);
2969 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2970 sdhci_transfer_pio(host);
2973 * We currently don't do anything fancy with DMA
2974 * boundaries, but as we can't disable the feature
2975 * we need to at least restart the transfer.
2977 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2978 * should return a valid address to continue from, but as
2979 * some controllers are faulty, don't trust them.
2981 if (intmask & SDHCI_INT_DMA_END) {
2982 dma_addr_t dmastart, dmanow;
2984 dmastart = sdhci_sdma_address(host);
2985 dmanow = dmastart + host->data->bytes_xfered;
2987 * Force update to the next DMA block boundary.
2990 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2991 SDHCI_DEFAULT_BOUNDARY_SIZE;
2992 host->data->bytes_xfered = dmanow - dmastart;
2993 DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
2994 &dmastart, host->data->bytes_xfered, &dmanow);
2995 sdhci_set_sdma_addr(host, dmanow);
2998 if (intmask & SDHCI_INT_DATA_END) {
2999 if (host->cmd == host->data_cmd) {
3001 * Data managed to finish before the
3002 * command completed. Make sure we do
3003 * things in the proper order.
3005 host->data_early = 1;
3007 sdhci_finish_data(host);
3013 static inline bool sdhci_defer_done(struct sdhci_host *host,
3014 struct mmc_request *mrq)
3016 struct mmc_data *data = mrq->data;
3018 return host->pending_reset ||
3019 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3020 data->host_cookie == COOKIE_MAPPED);
3023 static irqreturn_t sdhci_irq(int irq, void *dev_id)
3025 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3026 irqreturn_t result = IRQ_NONE;
3027 struct sdhci_host *host = dev_id;
3028 u32 intmask, mask, unexpected = 0;
3032 spin_lock(&host->lock);
3034 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
3035 spin_unlock(&host->lock);
3039 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3040 if (!intmask || intmask == 0xffffffff) {
3046 DBG("IRQ status 0x%08x\n", intmask);
3048 if (host->ops->irq) {
3049 intmask = host->ops->irq(host, intmask);
3054 /* Clear selected interrupts. */
3055 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3056 SDHCI_INT_BUS_POWER);
3057 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3059 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3060 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3064 * There is a observation on i.mx esdhc. INSERT
3065 * bit will be immediately set again when it gets
3066 * cleared, if a card is inserted. We have to mask
3067 * the irq to prevent interrupt storm which will
3068 * freeze the system. And the REMOVE gets the
3071 * More testing are needed here to ensure it works
3072 * for other platforms though.
3074 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3075 SDHCI_INT_CARD_REMOVE);
3076 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3077 SDHCI_INT_CARD_INSERT;
3078 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3079 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3081 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3082 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3084 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3085 SDHCI_INT_CARD_REMOVE);
3086 result = IRQ_WAKE_THREAD;
3089 if (intmask & SDHCI_INT_CMD_MASK)
3090 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3092 if (intmask & SDHCI_INT_DATA_MASK)
3093 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3095 if (intmask & SDHCI_INT_BUS_POWER)
3096 pr_err("%s: Card is consuming too much power!\n",
3097 mmc_hostname(host->mmc));
3099 if (intmask & SDHCI_INT_RETUNE)
3100 mmc_retune_needed(host->mmc);
3102 if ((intmask & SDHCI_INT_CARD_INT) &&
3103 (host->ier & SDHCI_INT_CARD_INT)) {
3104 sdhci_enable_sdio_irq_nolock(host, false);
3105 sdio_signal_irq(host->mmc);
3108 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3109 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3110 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3111 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3114 unexpected |= intmask;
3115 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3118 if (result == IRQ_NONE)
3119 result = IRQ_HANDLED;
3121 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3122 } while (intmask && --max_loops);
3124 /* Determine if mrqs can be completed immediately */
3125 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3126 struct mmc_request *mrq = host->mrqs_done[i];
3131 if (sdhci_defer_done(host, mrq)) {
3132 result = IRQ_WAKE_THREAD;
3135 host->mrqs_done[i] = NULL;
3139 spin_unlock(&host->lock);
3141 /* Process mrqs ready for immediate completion */
3142 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3144 mmc_request_done(host->mmc, mrqs_done[i]);
3148 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3149 mmc_hostname(host->mmc), unexpected);
3150 sdhci_dumpregs(host);
3156 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3158 struct sdhci_host *host = dev_id;
3159 unsigned long flags;
3162 while (!sdhci_request_done(host))
3165 spin_lock_irqsave(&host->lock, flags);
3166 isr = host->thread_isr;
3167 host->thread_isr = 0;
3168 spin_unlock_irqrestore(&host->lock, flags);
3170 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3171 struct mmc_host *mmc = host->mmc;
3173 mmc->ops->card_event(mmc);
3174 mmc_detect_change(mmc, msecs_to_jiffies(200));
3180 /*****************************************************************************\
3184 \*****************************************************************************/
3188 static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3190 return mmc_card_is_removable(host->mmc) &&
3191 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3192 !mmc_can_gpio_cd(host->mmc);
3196 * To enable wakeup events, the corresponding events have to be enabled in
3197 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3198 * Table' in the SD Host Controller Standard Specification.
3199 * It is useless to restore SDHCI_INT_ENABLE state in
3200 * sdhci_disable_irq_wakeups() since it will be set by
3201 * sdhci_enable_card_detection() or sdhci_init().
3203 static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3205 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3211 if (sdhci_cd_irq_can_wakeup(host)) {
3212 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3213 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3216 if (mmc_card_wake_sdio_irq(host->mmc)) {
3217 wake_val |= SDHCI_WAKE_ON_INT;
3218 irq_val |= SDHCI_INT_CARD_INT;
3224 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3227 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3229 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3231 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3233 return host->irq_wake_enabled;
3236 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3239 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3240 | SDHCI_WAKE_ON_INT;
3242 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3244 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3246 disable_irq_wake(host->irq);
3248 host->irq_wake_enabled = false;
3251 int sdhci_suspend_host(struct sdhci_host *host)
3253 sdhci_disable_card_detection(host);
3255 mmc_retune_timer_stop(host->mmc);
3257 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3258 !sdhci_enable_irq_wakeups(host)) {
3260 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3261 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3262 free_irq(host->irq, host);
3268 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3270 int sdhci_resume_host(struct sdhci_host *host)
3272 struct mmc_host *mmc = host->mmc;
3275 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3276 if (host->ops->enable_dma)
3277 host->ops->enable_dma(host);
3280 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3281 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3282 /* Card keeps power but host controller does not */
3283 sdhci_init(host, 0);
3286 mmc->ops->set_ios(mmc, &mmc->ios);
3288 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3291 if (host->irq_wake_enabled) {
3292 sdhci_disable_irq_wakeups(host);
3294 ret = request_threaded_irq(host->irq, sdhci_irq,
3295 sdhci_thread_irq, IRQF_SHARED,
3296 mmc_hostname(host->mmc), host);
3301 sdhci_enable_card_detection(host);
3306 EXPORT_SYMBOL_GPL(sdhci_resume_host);
3308 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3310 unsigned long flags;
3312 mmc_retune_timer_stop(host->mmc);
3314 spin_lock_irqsave(&host->lock, flags);
3315 host->ier &= SDHCI_INT_CARD_INT;
3316 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3317 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3318 spin_unlock_irqrestore(&host->lock, flags);
3320 synchronize_hardirq(host->irq);
3322 spin_lock_irqsave(&host->lock, flags);
3323 host->runtime_suspended = true;
3324 spin_unlock_irqrestore(&host->lock, flags);
3328 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3330 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3332 struct mmc_host *mmc = host->mmc;
3333 unsigned long flags;
3334 int host_flags = host->flags;
3336 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3337 if (host->ops->enable_dma)
3338 host->ops->enable_dma(host);
3341 sdhci_init(host, soft_reset);
3343 if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3344 mmc->ios.power_mode != MMC_POWER_OFF) {
3345 /* Force clock and power re-program */
3348 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3349 mmc->ops->set_ios(mmc, &mmc->ios);
3351 if ((host_flags & SDHCI_PV_ENABLED) &&
3352 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3353 spin_lock_irqsave(&host->lock, flags);
3354 sdhci_enable_preset_value(host, true);
3355 spin_unlock_irqrestore(&host->lock, flags);
3358 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3359 mmc->ops->hs400_enhanced_strobe)
3360 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3363 spin_lock_irqsave(&host->lock, flags);
3365 host->runtime_suspended = false;
3367 /* Enable SDIO IRQ */
3368 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3369 sdhci_enable_sdio_irq_nolock(host, true);
3371 /* Enable Card Detection */
3372 sdhci_enable_card_detection(host);
3374 spin_unlock_irqrestore(&host->lock, flags);
3378 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3380 #endif /* CONFIG_PM */
3382 /*****************************************************************************\
3384 * Command Queue Engine (CQE) helpers *
3386 \*****************************************************************************/
3388 void sdhci_cqe_enable(struct mmc_host *mmc)
3390 struct sdhci_host *host = mmc_priv(mmc);
3391 unsigned long flags;
3394 spin_lock_irqsave(&host->lock, flags);
3396 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3397 ctrl &= ~SDHCI_CTRL_DMA_MASK;
3399 * Host from V4.10 supports ADMA3 DMA type.
3400 * ADMA3 performs integrated descriptor which is more suitable
3401 * for cmd queuing to fetch both command and transfer descriptors.
3403 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3404 ctrl |= SDHCI_CTRL_ADMA3;
3405 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3406 ctrl |= SDHCI_CTRL_ADMA64;
3408 ctrl |= SDHCI_CTRL_ADMA32;
3409 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3411 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3414 /* Set maximum timeout */
3415 sdhci_set_timeout(host, NULL);
3417 host->ier = host->cqe_ier;
3419 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3420 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3422 host->cqe_on = true;
3424 pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3425 mmc_hostname(mmc), host->ier,
3426 sdhci_readl(host, SDHCI_INT_STATUS));
3428 spin_unlock_irqrestore(&host->lock, flags);
3430 EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3432 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3434 struct sdhci_host *host = mmc_priv(mmc);
3435 unsigned long flags;
3437 spin_lock_irqsave(&host->lock, flags);
3439 sdhci_set_default_irqs(host);
3441 host->cqe_on = false;
3444 sdhci_do_reset(host, SDHCI_RESET_CMD);
3445 sdhci_do_reset(host, SDHCI_RESET_DATA);
3448 pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3449 mmc_hostname(mmc), host->ier,
3450 sdhci_readl(host, SDHCI_INT_STATUS));
3452 spin_unlock_irqrestore(&host->lock, flags);
3454 EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3456 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3464 if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3465 *cmd_error = -EILSEQ;
3466 else if (intmask & SDHCI_INT_TIMEOUT)
3467 *cmd_error = -ETIMEDOUT;
3471 if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3472 *data_error = -EILSEQ;
3473 else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3474 *data_error = -ETIMEDOUT;
3475 else if (intmask & SDHCI_INT_ADMA_ERROR)
3480 /* Clear selected interrupts. */
3481 mask = intmask & host->cqe_ier;
3482 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3484 if (intmask & SDHCI_INT_BUS_POWER)
3485 pr_err("%s: Card is consuming too much power!\n",
3486 mmc_hostname(host->mmc));
3488 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3490 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3491 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3492 mmc_hostname(host->mmc), intmask);
3493 sdhci_dumpregs(host);
3498 EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3500 /*****************************************************************************\
3502 * Device allocation/registration *
3504 \*****************************************************************************/
3506 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3509 struct mmc_host *mmc;
3510 struct sdhci_host *host;
3512 WARN_ON(dev == NULL);
3514 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3516 return ERR_PTR(-ENOMEM);
3518 host = mmc_priv(mmc);
3520 host->mmc_host_ops = sdhci_ops;
3521 mmc->ops = &host->mmc_host_ops;
3523 host->flags = SDHCI_SIGNALING_330;
3525 host->cqe_ier = SDHCI_CQE_INT_MASK;
3526 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3528 host->tuning_delay = -1;
3529 host->tuning_loop_count = MAX_TUNING_LOOP;
3531 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3534 * The DMA table descriptor count is calculated as the maximum
3535 * number of segments times 2, to allow for an alignment
3536 * descriptor for each segment, plus 1 for a nop end descriptor.
3538 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3543 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3545 static int sdhci_set_dma_mask(struct sdhci_host *host)
3547 struct mmc_host *mmc = host->mmc;
3548 struct device *dev = mmc_dev(mmc);
3551 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3552 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3554 /* Try 64-bit mask if hardware is capable of it */
3555 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3556 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3558 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3560 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3564 /* 32-bit mask as default & fallback */
3566 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3568 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3575 void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3578 u64 dt_caps_mask = 0;
3581 if (host->read_caps)
3584 host->read_caps = true;
3587 host->quirks = debug_quirks;
3590 host->quirks2 = debug_quirks2;
3592 sdhci_do_reset(host, SDHCI_RESET_ALL);
3595 sdhci_do_enable_v4_mode(host);
3597 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3598 "sdhci-caps-mask", &dt_caps_mask);
3599 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3600 "sdhci-caps", &dt_caps);
3602 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3603 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3605 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3611 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3612 host->caps &= ~lower_32_bits(dt_caps_mask);
3613 host->caps |= lower_32_bits(dt_caps);
3616 if (host->version < SDHCI_SPEC_300)
3620 host->caps1 = *caps1;
3622 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3623 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3624 host->caps1 |= upper_32_bits(dt_caps);
3627 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3629 static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3631 struct mmc_host *mmc = host->mmc;
3632 unsigned int max_blocks;
3633 unsigned int bounce_size;
3637 * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
3638 * has diminishing returns, this is probably because SD/MMC
3639 * cards are usually optimized to handle this size of requests.
3641 bounce_size = SZ_64K;
3643 * Adjust downwards to maximum request size if this is less
3644 * than our segment size, else hammer down the maximum
3645 * request size to the maximum buffer size.
3647 if (mmc->max_req_size < bounce_size)
3648 bounce_size = mmc->max_req_size;
3649 max_blocks = bounce_size / 512;
3652 * When we just support one segment, we can get significant
3653 * speedups by the help of a bounce buffer to group scattered
3654 * reads/writes together.
3656 host->bounce_buffer = devm_kmalloc(mmc->parent,
3659 if (!host->bounce_buffer) {
3660 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
3664 * Exiting with zero here makes sure we proceed with
3665 * mmc->max_segs == 1.
3670 host->bounce_addr = dma_map_single(mmc->parent,
3671 host->bounce_buffer,
3674 ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3676 /* Again fall back to max_segs == 1 */
3678 host->bounce_buffer_size = bounce_size;
3680 /* Lie about this since we're bouncing */
3681 mmc->max_segs = max_blocks;
3682 mmc->max_seg_size = bounce_size;
3683 mmc->max_req_size = bounce_size;
3685 pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3686 mmc_hostname(mmc), max_blocks, bounce_size);
3689 static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
3692 * According to SD Host Controller spec v4.10, bit[27] added from
3693 * version 4.10 in Capabilities Register is used as 64-bit System
3694 * Address support for V4 mode.
3696 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
3697 return host->caps & SDHCI_CAN_64BIT_V4;
3699 return host->caps & SDHCI_CAN_64BIT;
3702 int sdhci_setup_host(struct sdhci_host *host)
3704 struct mmc_host *mmc;
3705 u32 max_current_caps;
3706 unsigned int ocr_avail;
3707 unsigned int override_timeout_clk;
3711 WARN_ON(host == NULL);
3718 * If there are external regulators, get them. Note this must be done
3719 * early before resetting the host and reading the capabilities so that
3720 * the host can take the appropriate action if regulators are not
3723 ret = mmc_regulator_get_supply(mmc);
3727 DBG("Version: 0x%08x | Present: 0x%08x\n",
3728 sdhci_readw(host, SDHCI_HOST_VERSION),
3729 sdhci_readl(host, SDHCI_PRESENT_STATE));
3730 DBG("Caps: 0x%08x | Caps_1: 0x%08x\n",
3731 sdhci_readl(host, SDHCI_CAPABILITIES),
3732 sdhci_readl(host, SDHCI_CAPABILITIES_1));
3734 sdhci_read_caps(host);
3736 override_timeout_clk = host->timeout_clk;
3738 if (host->version > SDHCI_SPEC_420) {
3739 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3740 mmc_hostname(mmc), host->version);
3743 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3744 host->flags |= SDHCI_USE_SDMA;
3745 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3746 DBG("Controller doesn't have SDMA capability\n");
3748 host->flags |= SDHCI_USE_SDMA;
3750 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3751 (host->flags & SDHCI_USE_SDMA)) {
3752 DBG("Disabling DMA as it is marked broken\n");
3753 host->flags &= ~SDHCI_USE_SDMA;
3756 if ((host->version >= SDHCI_SPEC_200) &&
3757 (host->caps & SDHCI_CAN_DO_ADMA2))
3758 host->flags |= SDHCI_USE_ADMA;
3760 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3761 (host->flags & SDHCI_USE_ADMA)) {
3762 DBG("Disabling ADMA as it is marked broken\n");
3763 host->flags &= ~SDHCI_USE_ADMA;
3766 if (sdhci_can_64bit_dma(host))
3767 host->flags |= SDHCI_USE_64_BIT_DMA;
3769 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3770 if (host->ops->set_dma_mask)
3771 ret = host->ops->set_dma_mask(host);
3773 ret = sdhci_set_dma_mask(host);
3775 if (!ret && host->ops->enable_dma)
3776 ret = host->ops->enable_dma(host);
3779 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3781 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3787 /* SDMA does not support 64-bit DMA if v4 mode not set */
3788 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
3789 host->flags &= ~SDHCI_USE_SDMA;
3791 if (host->flags & SDHCI_USE_ADMA) {
3795 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3796 host->adma_table_sz = host->adma_table_cnt *
3797 SDHCI_ADMA2_64_DESC_SZ(host);
3798 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
3800 host->adma_table_sz = host->adma_table_cnt *
3801 SDHCI_ADMA2_32_DESC_SZ;
3802 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3805 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3807 * Use zalloc to zero the reserved high 32-bits of 128-bit
3808 * descriptors so that they never need to be written.
3810 buf = dma_alloc_coherent(mmc_dev(mmc),
3811 host->align_buffer_sz + host->adma_table_sz,
3814 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3816 host->flags &= ~SDHCI_USE_ADMA;
3817 } else if ((dma + host->align_buffer_sz) &
3818 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
3819 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3821 host->flags &= ~SDHCI_USE_ADMA;
3822 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3823 host->adma_table_sz, buf, dma);
3825 host->align_buffer = buf;
3826 host->align_addr = dma;
3828 host->adma_table = buf + host->align_buffer_sz;
3829 host->adma_addr = dma + host->align_buffer_sz;
3834 * If we use DMA, then it's up to the caller to set the DMA
3835 * mask, but PIO does not need the hw shim so we set a new
3836 * mask here in that case.
3838 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3839 host->dma_mask = DMA_BIT_MASK(64);
3840 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3843 if (host->version >= SDHCI_SPEC_300)
3844 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3845 >> SDHCI_CLOCK_BASE_SHIFT;
3847 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3848 >> SDHCI_CLOCK_BASE_SHIFT;
3850 host->max_clk *= 1000000;
3851 if (host->max_clk == 0 || host->quirks &
3852 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3853 if (!host->ops->get_max_clock) {
3854 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3859 host->max_clk = host->ops->get_max_clock(host);
3863 * In case of Host Controller v3.00, find out whether clock
3864 * multiplier is supported.
3866 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3867 SDHCI_CLOCK_MUL_SHIFT;
3870 * In case the value in Clock Multiplier is 0, then programmable
3871 * clock mode is not supported, otherwise the actual clock
3872 * multiplier is one more than the value of Clock Multiplier
3873 * in the Capabilities Register.
3879 * Set host parameters.
3881 max_clk = host->max_clk;
3883 if (host->ops->get_min_clock)
3884 mmc->f_min = host->ops->get_min_clock(host);
3885 else if (host->version >= SDHCI_SPEC_300) {
3886 if (host->clk_mul) {
3887 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3888 max_clk = host->max_clk * host->clk_mul;
3890 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3892 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3894 if (!mmc->f_max || mmc->f_max > max_clk)
3895 mmc->f_max = max_clk;
3897 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3898 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3899 SDHCI_TIMEOUT_CLK_SHIFT;
3901 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3902 host->timeout_clk *= 1000;
3904 if (host->timeout_clk == 0) {
3905 if (!host->ops->get_timeout_clock) {
3906 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3913 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
3917 if (override_timeout_clk)
3918 host->timeout_clk = override_timeout_clk;
3920 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3921 host->ops->get_max_timeout_count(host) : 1 << 27;
3922 mmc->max_busy_timeout /= host->timeout_clk;
3925 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
3926 !host->ops->get_max_timeout_count)
3927 mmc->max_busy_timeout = 0;
3929 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3930 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3932 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3933 host->flags |= SDHCI_AUTO_CMD12;
3936 * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
3937 * For v4 mode, SDMA may use Auto-CMD23 as well.
3939 if ((host->version >= SDHCI_SPEC_300) &&
3940 ((host->flags & SDHCI_USE_ADMA) ||
3941 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
3942 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3943 host->flags |= SDHCI_AUTO_CMD23;
3944 DBG("Auto-CMD23 available\n");
3946 DBG("Auto-CMD23 unavailable\n");
3950 * A controller may support 8-bit width, but the board itself
3951 * might not have the pins brought out. Boards that support
3952 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3953 * their platform code before calling sdhci_add_host(), and we
3954 * won't assume 8-bit width for hosts without that CAP.
3956 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3957 mmc->caps |= MMC_CAP_4_BIT_DATA;
3959 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3960 mmc->caps &= ~MMC_CAP_CMD23;
3962 if (host->caps & SDHCI_CAN_DO_HISPD)
3963 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3965 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3966 mmc_card_is_removable(mmc) &&
3967 mmc_gpio_get_cd(host->mmc) < 0)
3968 mmc->caps |= MMC_CAP_NEEDS_POLL;
3970 if (!IS_ERR(mmc->supply.vqmmc)) {
3971 ret = regulator_enable(mmc->supply.vqmmc);
3973 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
3974 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3976 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3977 SDHCI_SUPPORT_SDR50 |
3978 SDHCI_SUPPORT_DDR50);
3980 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
3981 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
3983 host->flags &= ~SDHCI_SIGNALING_330;
3986 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3987 mmc_hostname(mmc), ret);
3988 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3992 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3993 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3994 SDHCI_SUPPORT_DDR50);
3996 * The SDHCI controller in a SoC might support HS200/HS400
3997 * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
3998 * but if the board is modeled such that the IO lines are not
3999 * connected to 1.8v then HS200/HS400 cannot be supported.
4000 * Disable HS200/HS400 if the board does not have 1.8v connected
4001 * to the IO lines. (Applicable for other modes in 1.8v)
4003 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4004 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4007 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4008 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4009 SDHCI_SUPPORT_DDR50))
4010 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4012 /* SDR104 supports also implies SDR50 support */
4013 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4014 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4015 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4016 * field can be promoted to support HS200.
4018 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4019 mmc->caps2 |= MMC_CAP2_HS200;
4020 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4021 mmc->caps |= MMC_CAP_UHS_SDR50;
4024 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4025 (host->caps1 & SDHCI_SUPPORT_HS400))
4026 mmc->caps2 |= MMC_CAP2_HS400;
4028 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4029 (IS_ERR(mmc->supply.vqmmc) ||
4030 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4032 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4034 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4035 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4036 mmc->caps |= MMC_CAP_UHS_DDR50;
4038 /* Does the host need tuning for SDR50? */
4039 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4040 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4042 /* Driver Type(s) (A, C, D) supported by the host */
4043 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4044 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4045 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4046 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4047 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4048 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4050 /* Initial value for re-tuning timer count */
4051 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
4052 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
4055 * In case Re-tuning Timer is not disabled, the actual value of
4056 * re-tuning timer will be 2 ^ (n - 1).
4058 if (host->tuning_count)
4059 host->tuning_count = 1 << (host->tuning_count - 1);
4061 /* Re-tuning mode supported by the Host Controller */
4062 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
4063 SDHCI_RETUNING_MODE_SHIFT;
4068 * According to SD Host Controller spec v3.00, if the Host System
4069 * can afford more than 150mA, Host Driver should set XPC to 1. Also
4070 * the value is meaningful only if Voltage Support in the Capabilities
4071 * register is set. The actual current value is 4 times the register
4074 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4075 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4076 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4079 /* convert to SDHCI_MAX_CURRENT format */
4080 curr = curr/1000; /* convert to mA */
4081 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4083 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4085 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
4086 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
4087 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
4091 if (host->caps & SDHCI_CAN_VDD_330) {
4092 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4094 mmc->max_current_330 = ((max_current_caps &
4095 SDHCI_MAX_CURRENT_330_MASK) >>
4096 SDHCI_MAX_CURRENT_330_SHIFT) *
4097 SDHCI_MAX_CURRENT_MULTIPLIER;
4099 if (host->caps & SDHCI_CAN_VDD_300) {
4100 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4102 mmc->max_current_300 = ((max_current_caps &
4103 SDHCI_MAX_CURRENT_300_MASK) >>
4104 SDHCI_MAX_CURRENT_300_SHIFT) *
4105 SDHCI_MAX_CURRENT_MULTIPLIER;
4107 if (host->caps & SDHCI_CAN_VDD_180) {
4108 ocr_avail |= MMC_VDD_165_195;
4110 mmc->max_current_180 = ((max_current_caps &
4111 SDHCI_MAX_CURRENT_180_MASK) >>
4112 SDHCI_MAX_CURRENT_180_SHIFT) *
4113 SDHCI_MAX_CURRENT_MULTIPLIER;
4116 /* If OCR set by host, use it instead. */
4118 ocr_avail = host->ocr_mask;
4120 /* If OCR set by external regulators, give it highest prio. */
4122 ocr_avail = mmc->ocr_avail;
4124 mmc->ocr_avail = ocr_avail;
4125 mmc->ocr_avail_sdio = ocr_avail;
4126 if (host->ocr_avail_sdio)
4127 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4128 mmc->ocr_avail_sd = ocr_avail;
4129 if (host->ocr_avail_sd)
4130 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4131 else /* normal SD controllers don't support 1.8V */
4132 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4133 mmc->ocr_avail_mmc = ocr_avail;
4134 if (host->ocr_avail_mmc)
4135 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4137 if (mmc->ocr_avail == 0) {
4138 pr_err("%s: Hardware doesn't report any support voltages.\n",
4144 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4145 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4146 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4147 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4148 host->flags |= SDHCI_SIGNALING_180;
4150 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4151 host->flags |= SDHCI_SIGNALING_120;
4153 spin_lock_init(&host->lock);
4156 * Maximum number of sectors in one transfer. Limited by SDMA boundary
4157 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4160 mmc->max_req_size = 524288;
4163 * Maximum number of segments. Depends on if the hardware
4164 * can do scatter/gather or not.
4166 if (host->flags & SDHCI_USE_ADMA) {
4167 mmc->max_segs = SDHCI_MAX_SEGS;
4168 } else if (host->flags & SDHCI_USE_SDMA) {
4170 if (swiotlb_max_segment()) {
4171 unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
4173 mmc->max_req_size = min(mmc->max_req_size,
4177 mmc->max_segs = SDHCI_MAX_SEGS;
4181 * Maximum segment size. Could be one segment with the maximum number
4182 * of bytes. When doing hardware scatter/gather, each entry cannot
4183 * be larger than 64 KiB though.
4185 if (host->flags & SDHCI_USE_ADMA) {
4186 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4187 mmc->max_seg_size = 65535;
4189 mmc->max_seg_size = 65536;
4191 mmc->max_seg_size = mmc->max_req_size;
4195 * Maximum block size. This varies from controller to controller and
4196 * is specified in the capabilities register.
4198 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4199 mmc->max_blk_size = 2;
4201 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4202 SDHCI_MAX_BLOCK_SHIFT;
4203 if (mmc->max_blk_size >= 3) {
4204 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4206 mmc->max_blk_size = 0;
4210 mmc->max_blk_size = 512 << mmc->max_blk_size;
4213 * Maximum block count.
4215 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4217 if (mmc->max_segs == 1)
4218 /* This may alter mmc->*_blk_* parameters */
4219 sdhci_allocate_bounce_buffer(host);
4224 if (!IS_ERR(mmc->supply.vqmmc))
4225 regulator_disable(mmc->supply.vqmmc);
4227 if (host->align_buffer)
4228 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4229 host->adma_table_sz, host->align_buffer,
4231 host->adma_table = NULL;
4232 host->align_buffer = NULL;
4236 EXPORT_SYMBOL_GPL(sdhci_setup_host);
4238 void sdhci_cleanup_host(struct sdhci_host *host)
4240 struct mmc_host *mmc = host->mmc;
4242 if (!IS_ERR(mmc->supply.vqmmc))
4243 regulator_disable(mmc->supply.vqmmc);
4245 if (host->align_buffer)
4246 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4247 host->adma_table_sz, host->align_buffer,
4249 host->adma_table = NULL;
4250 host->align_buffer = NULL;
4252 EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4254 int __sdhci_add_host(struct sdhci_host *host)
4256 unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4257 struct mmc_host *mmc = host->mmc;
4260 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4261 if (!host->complete_wq)
4264 INIT_WORK(&host->complete_work, sdhci_complete_work);
4266 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4267 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4269 init_waitqueue_head(&host->buf_ready_int);
4271 sdhci_init(host, 0);
4273 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4274 IRQF_SHARED, mmc_hostname(mmc), host);
4276 pr_err("%s: Failed to request IRQ %d: %d\n",
4277 mmc_hostname(mmc), host->irq, ret);
4281 ret = sdhci_led_register(host);
4283 pr_err("%s: Failed to register LED device: %d\n",
4284 mmc_hostname(mmc), ret);
4288 ret = mmc_add_host(mmc);
4292 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4293 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4294 (host->flags & SDHCI_USE_ADMA) ?
4295 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4296 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4298 sdhci_enable_card_detection(host);
4303 sdhci_led_unregister(host);
4305 sdhci_do_reset(host, SDHCI_RESET_ALL);
4306 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4307 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4308 free_irq(host->irq, host);
4310 destroy_workqueue(host->complete_wq);
4314 EXPORT_SYMBOL_GPL(__sdhci_add_host);
4316 int sdhci_add_host(struct sdhci_host *host)
4320 ret = sdhci_setup_host(host);
4324 ret = __sdhci_add_host(host);
4331 sdhci_cleanup_host(host);
4335 EXPORT_SYMBOL_GPL(sdhci_add_host);
4337 void sdhci_remove_host(struct sdhci_host *host, int dead)
4339 struct mmc_host *mmc = host->mmc;
4340 unsigned long flags;
4343 spin_lock_irqsave(&host->lock, flags);
4345 host->flags |= SDHCI_DEVICE_DEAD;
4347 if (sdhci_has_requests(host)) {
4348 pr_err("%s: Controller removed during "
4349 " transfer!\n", mmc_hostname(mmc));
4350 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4353 spin_unlock_irqrestore(&host->lock, flags);
4356 sdhci_disable_card_detection(host);
4358 mmc_remove_host(mmc);
4360 sdhci_led_unregister(host);
4363 sdhci_do_reset(host, SDHCI_RESET_ALL);
4365 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4366 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4367 free_irq(host->irq, host);
4369 del_timer_sync(&host->timer);
4370 del_timer_sync(&host->data_timer);
4372 destroy_workqueue(host->complete_wq);
4374 if (!IS_ERR(mmc->supply.vqmmc))
4375 regulator_disable(mmc->supply.vqmmc);
4377 if (host->align_buffer)
4378 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4379 host->adma_table_sz, host->align_buffer,
4382 host->adma_table = NULL;
4383 host->align_buffer = NULL;
4386 EXPORT_SYMBOL_GPL(sdhci_remove_host);
4388 void sdhci_free_host(struct sdhci_host *host)
4390 mmc_free_host(host->mmc);
4393 EXPORT_SYMBOL_GPL(sdhci_free_host);
4395 /*****************************************************************************\
4397 * Driver init/exit *
4399 \*****************************************************************************/
4401 static int __init sdhci_drv_init(void)
4404 ": Secure Digital Host Controller Interface driver\n");
4405 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4410 static void __exit sdhci_drv_exit(void)
4414 module_init(sdhci_drv_init);
4415 module_exit(sdhci_drv_exit);
4417 module_param(debug_quirks, uint, 0444);
4418 module_param(debug_quirks2, uint, 0444);
4420 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4421 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4422 MODULE_LICENSE("GPL");
4424 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4425 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");