drivers/mmc/host/sdhci-pxav3.c

   1 /*
   2  * Copyright (C) 2010 Marvell International Ltd.
   3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
   4  *              Kevin Wang <dwang4@marvell.com>
   5  *              Mingwei Wang <mwwang@marvell.com>
   6  *              Philip Rakity <prakity@marvell.com>
   7  *              Mark Brown <markb@marvell.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24 #include <linux/gpio.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/mmc/host.h>
  27 #include <linux/mmc/slot-gpio.h>
  28 #include <linux/platform_data/pxa_sdhci.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/module.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_gpio.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/mbus.h>
  38
  39 #include "sdhci.h"
  40 #include "sdhci-pltfm.h"
  41
  42 #define PXAV3_RPM_DELAY_MS     50
  43
  44 #define SD_CLOCK_BURST_SIZE_SETUP               0x10A
  45 #define SDCLK_SEL       0x100
  46 #define SDCLK_DELAY_SHIFT       9
  47 #define SDCLK_DELAY_MASK        0x1f
  48
  49 #define SD_CFG_FIFO_PARAM       0x100
  50 #define SDCFG_GEN_PAD_CLK_ON    (1<<6)
  51 #define SDCFG_GEN_PAD_CLK_CNT_MASK      0xFF
  52 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT     24
  53
  54 #define SD_SPI_MODE          0x108
  55 #define SD_CE_ATA_1          0x10C
  56
  57 #define SD_CE_ATA_2          0x10E
  58 #define SDCE_MISC_INT           (1<<2)
  59 #define SDCE_MISC_INT_EN        (1<<1)
  60
  61 /*
  62  * These registers are relative to the second register region, for the
  63  * MBus bridge.
  64  */
  65 #define SDHCI_WINDOW_CTRL(i)    (0x80 + ((i) << 3))
  66 #define SDHCI_WINDOW_BASE(i)    (0x84 + ((i) << 3))
  67 #define SDHCI_MAX_WIN_NUM       8
  68
  69 static int mv_conf_mbus_windows(struct platform_device *pdev,
  70                                 const struct mbus_dram_target_info *dram)
  71 {
  72         int i;
  73         void __iomem *regs;
  74         struct resource *res;
  75
  76         if (!dram) {
  77                 dev_err(&pdev->dev, "no mbus dram info\n");
  78                 return -EINVAL;
  79         }
  80
  81         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  82         if (!res) {
  83                 dev_err(&pdev->dev, "cannot get mbus registers\n");
  84                 return -EINVAL;
  85         }
  86
  87         regs = ioremap(res->start, resource_size(res));
  88         if (!regs) {
  89                 dev_err(&pdev->dev, "cannot map mbus registers\n");
  90                 return -ENOMEM;
  91         }
  92
  93         for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
  94                 writel(0, regs + SDHCI_WINDOW_CTRL(i));
  95                 writel(0, regs + SDHCI_WINDOW_BASE(i));
  96         }
  97
  98         for (i = 0; i < dram->num_cs; i++) {
  99                 const struct mbus_dram_window *cs = dram->cs + i;
 100
 101                 /* Write size, attributes and target id to control register */
 102                 writel(((cs->size - 1) & 0xffff0000) |
 103                         (cs->mbus_attr << 8) |
 104                         (dram->mbus_dram_target_id << 4) | 1,
 105                         regs + SDHCI_WINDOW_CTRL(i));
 106                 /* Write base address to base register */
 107                 writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
 108         }
 109
 110         iounmap(regs);
 111
 112         return 0;
 113 }
 114
 115 static int armada_38x_quirks(struct platform_device *pdev,
 116                              struct sdhci_host *host)
 117 {
 118         struct device_node *np = pdev->dev.of_node;
 119
 120         host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
 121         /*
 122          * According to erratum 'FE-2946959' both SDR50 and DDR50
 123          * modes require specific clock adjustments in SDIO3
 124          * Configuration register, if the adjustment is not done,
 125          * remove them from the capabilities.
 126          */
 127         host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 128         host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
 129
 130         /*
 131          * According to erratum 'ERR-7878951' Armada 38x SDHCI
 132          * controller has different capabilities than the ones shown
 133          * in its registers
 134          */
 135         host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 136         if (of_property_read_bool(np, "no-1-8-v")) {
 137                 host->caps &= ~SDHCI_CAN_VDD_180;
 138                 host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
 139         } else {
 140                 host->caps &= ~SDHCI_CAN_VDD_330;
 141         }
 142         host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
 143
 144         return 0;
 145 }
 146
 147 static void pxav3_reset(struct sdhci_host *host, u8 mask)
 148 {
 149         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
 150         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 151
 152         sdhci_reset(host, mask);
 153
 154         if (mask == SDHCI_RESET_ALL) {
 155                 /*
 156                  * tune timing of read data/command when crc error happen
 157                  * no performance impact
 158                  */
 159                 if (pdata && 0 != pdata->clk_delay_cycles) {
 160                         u16 tmp;
 161
 162                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 163                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
 164                                 << SDCLK_DELAY_SHIFT;
 165                         tmp |= SDCLK_SEL;
 166                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 167                 }
 168         }
 169 }
 170
 171 #define MAX_WAIT_COUNT 5
 172 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 173 {
 174         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 175         struct sdhci_pxa *pxa = pltfm_host->priv;
 176         u16 tmp;
 177         int count;
 178
 179         if (pxa->power_mode == MMC_POWER_UP
 180                         && power_mode == MMC_POWER_ON) {
 181
 182                 dev_dbg(mmc_dev(host->mmc),
 183                                 "%s: slot->power_mode = %d,"
 184                                 "ios->power_mode = %d\n",
 185                                 __func__,
 186                                 pxa->power_mode,
 187                                 power_mode);
 188
 189                 /* set we want notice of when 74 clocks are sent */
 190                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
 191                 tmp |= SDCE_MISC_INT_EN;
 192                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
 193
 194                 /* start sending the 74 clocks */
 195                 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
 196                 tmp |= SDCFG_GEN_PAD_CLK_ON;
 197                 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
 198
 199                 /* slowest speed is about 100KHz or 10usec per clock */
 200                 udelay(740);
 201                 count = 0;
 202
 203                 while (count++ < MAX_WAIT_COUNT) {
 204                         if ((readw(host->ioaddr + SD_CE_ATA_2)
 205                                                 & SDCE_MISC_INT) == 0)
 206                                 break;
 207                         udelay(10);
 208                 }
 209
 210                 if (count == MAX_WAIT_COUNT)
 211                         dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
 212
 213                 /* clear the interrupt bit if posted */
 214                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
 215                 tmp |= SDCE_MISC_INT;
 216                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
 217         }
 218         pxa->power_mode = power_mode;
 219 }
 220
 221 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 222 {
 223         u16 ctrl_2;
 224
 225         /*
 226          * Set V18_EN -- UHS modes do not work without this.
 227          * does not change signaling voltage
 228          */
 229         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 230
 231         /* Select Bus Speed Mode for host */
 232         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 233         switch (uhs) {
 234         case MMC_TIMING_UHS_SDR12:
 235                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 236                 break;
 237         case MMC_TIMING_UHS_SDR25:
 238                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 239                 break;
 240         case MMC_TIMING_UHS_SDR50:
 241                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
 242                 break;
 243         case MMC_TIMING_UHS_SDR104:
 244                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
 245                 break;
 246         case MMC_TIMING_UHS_DDR50:
 247                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
 248                 break;
 249         }
 250
 251         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 252         dev_dbg(mmc_dev(host->mmc),
 253                 "%s uhs = %d, ctrl_2 = %04X\n",
 254                 __func__, uhs, ctrl_2);
 255 }
 256
 257 static const struct sdhci_ops pxav3_sdhci_ops = {
 258         .set_clock = sdhci_set_clock,
 259         .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
 260         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 261         .set_bus_width = sdhci_set_bus_width,
 262         .reset = pxav3_reset,
 263         .set_uhs_signaling = pxav3_set_uhs_signaling,
 264 };
 265
 266 static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
 267         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
 268                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 269                 | SDHCI_QUIRK_32BIT_ADMA_SIZE
 270                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 271         .ops = &pxav3_sdhci_ops,
 272 };
 273
 274 #ifdef CONFIG_OF
 275 static const struct of_device_id sdhci_pxav3_of_match[] = {
 276         {
 277                 .compatible = "mrvl,pxav3-mmc",
 278         },
 279         {
 280                 .compatible = "marvell,armada-380-sdhci",
 281         },
 282         {},
 283 };
 284 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
 285
 286 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
 287 {
 288         struct sdhci_pxa_platdata *pdata;
 289         struct device_node *np = dev->of_node;
 290         u32 clk_delay_cycles;
 291
 292         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 293         if (!pdata)
 294                 return NULL;
 295
 296         if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
 297                                   &clk_delay_cycles))
 298                 pdata->clk_delay_cycles = clk_delay_cycles;
 299
 300         return pdata;
 301 }
 302 #else
 303 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
 304 {
 305         return NULL;
 306 }
 307 #endif
 308
 309 static int sdhci_pxav3_probe(struct platform_device *pdev)
 310 {
 311         struct sdhci_pltfm_host *pltfm_host;
 312         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 313         struct device *dev = &pdev->dev;
 314         struct device_node *np = pdev->dev.of_node;
 315         struct sdhci_host *host = NULL;
 316         struct sdhci_pxa *pxa = NULL;
 317         const struct of_device_id *match;
 318
 319         int ret;
 320         struct clk *clk;
 321
 322         pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
 323         if (!pxa)
 324                 return -ENOMEM;
 325
 326         host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
 327         if (IS_ERR(host))
 328                 return PTR_ERR(host);
 329
 330         /* enable 1/8V DDR capable */
 331         host->mmc->caps |= MMC_CAP_1_8V_DDR;
 332
 333         pltfm_host = sdhci_priv(host);
 334         pltfm_host->priv = pxa;
 335
 336         clk = devm_clk_get(dev, NULL);
 337         if (IS_ERR(clk)) {
 338                 dev_err(dev, "failed to get io clock\n");
 339                 ret = PTR_ERR(clk);
 340                 goto err_clk_get;
 341         }
 342         pltfm_host->clk = clk;
 343         clk_prepare_enable(clk);
 344
 345         if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
 346                 ret = armada_38x_quirks(pdev, host);
 347                 if (ret < 0)
 348                         goto err_clk_get;
 349                 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
 350                 if (ret < 0)
 351                         goto err_mbus_win;
 352         }
 353
 354         match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
 355         if (match) {
 356                 ret = mmc_of_parse(host->mmc);
 357                 if (ret)
 358                         goto err_of_parse;
 359                 sdhci_get_of_property(pdev);
 360                 pdata = pxav3_get_mmc_pdata(dev);
 361         } else if (pdata) {
 362                 /* on-chip device */
 363                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
 364                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
 365
 366                 /* If slot design supports 8 bit data, indicate this to MMC. */
 367                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
 368                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 369
 370                 if (pdata->quirks)
 371                         host->quirks |= pdata->quirks;
 372                 if (pdata->quirks2)
 373                         host->quirks2 |= pdata->quirks2;
 374                 if (pdata->host_caps)
 375                         host->mmc->caps |= pdata->host_caps;
 376                 if (pdata->host_caps2)
 377                         host->mmc->caps2 |= pdata->host_caps2;
 378                 if (pdata->pm_caps)
 379                         host->mmc->pm_caps |= pdata->pm_caps;
 380
 381                 if (gpio_is_valid(pdata->ext_cd_gpio)) {
 382                         ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
 383                                                   0);
 384                         if (ret) {
 385                                 dev_err(mmc_dev(host->mmc),
 386                                         "failed to allocate card detect gpio\n");
 387                                 goto err_cd_req;
 388                         }
 389                 }
 390         }
 391
 392         pm_runtime_get_noresume(&pdev->dev);
 393         pm_runtime_set_active(&pdev->dev);
 394         pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
 395         pm_runtime_use_autosuspend(&pdev->dev);
 396         pm_runtime_enable(&pdev->dev);
 397         pm_suspend_ignore_children(&pdev->dev, 1);
 398
 399         ret = sdhci_add_host(host);
 400         if (ret) {
 401                 dev_err(&pdev->dev, "failed to add host\n");
 402                 goto err_add_host;
 403         }
 404
 405         platform_set_drvdata(pdev, host);
 406
 407         if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
 408                 device_init_wakeup(&pdev->dev, 1);
 409                 host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
 410         } else {
 411                 device_init_wakeup(&pdev->dev, 0);
 412         }
 413
 414         pm_runtime_put_autosuspend(&pdev->dev);
 415
 416         return 0;
 417
 418 err_add_host:
 419         pm_runtime_disable(&pdev->dev);
 420         pm_runtime_put_noidle(&pdev->dev);
 421 err_of_parse:
 422 err_cd_req:
 423 err_mbus_win:
 424         clk_disable_unprepare(clk);
 425 err_clk_get:
 426         sdhci_pltfm_free(pdev);
 427         return ret;
 428 }
 429
 430 static int sdhci_pxav3_remove(struct platform_device *pdev)
 431 {
 432         struct sdhci_host *host = platform_get_drvdata(pdev);
 433         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 434
 435         pm_runtime_get_sync(&pdev->dev);
 436         sdhci_remove_host(host, 1);
 437         pm_runtime_disable(&pdev->dev);
 438
 439         clk_disable_unprepare(pltfm_host->clk);
 440
 441         sdhci_pltfm_free(pdev);
 442
 443         return 0;
 444 }
 445
 446 #ifdef CONFIG_PM_SLEEP
 447 static int sdhci_pxav3_suspend(struct device *dev)
 448 {
 449         int ret;
 450         struct sdhci_host *host = dev_get_drvdata(dev);
 451
 452         pm_runtime_get_sync(dev);
 453         ret = sdhci_suspend_host(host);
 454         pm_runtime_mark_last_busy(dev);
 455         pm_runtime_put_autosuspend(dev);
 456
 457         return ret;
 458 }
 459
 460 static int sdhci_pxav3_resume(struct device *dev)
 461 {
 462         int ret;
 463         struct sdhci_host *host = dev_get_drvdata(dev);
 464
 465         pm_runtime_get_sync(dev);
 466         ret = sdhci_resume_host(host);
 467         pm_runtime_mark_last_busy(dev);
 468         pm_runtime_put_autosuspend(dev);
 469
 470         return ret;
 471 }
 472 #endif
 473
 474 #ifdef CONFIG_PM_RUNTIME
 475 static int sdhci_pxav3_runtime_suspend(struct device *dev)
 476 {
 477         struct sdhci_host *host = dev_get_drvdata(dev);
 478         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 479         unsigned long flags;
 480
 481         if (pltfm_host->clk) {
 482                 spin_lock_irqsave(&host->lock, flags);
 483                 host->runtime_suspended = true;
 484                 spin_unlock_irqrestore(&host->lock, flags);
 485
 486                 clk_disable_unprepare(pltfm_host->clk);
 487         }
 488
 489         return 0;
 490 }
 491
 492 static int sdhci_pxav3_runtime_resume(struct device *dev)
 493 {
 494         struct sdhci_host *host = dev_get_drvdata(dev);
 495         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 496         unsigned long flags;
 497
 498         if (pltfm_host->clk) {
 499                 clk_prepare_enable(pltfm_host->clk);
 500
 501                 spin_lock_irqsave(&host->lock, flags);
 502                 host->runtime_suspended = false;
 503                 spin_unlock_irqrestore(&host->lock, flags);
 504         }
 505
 506         return 0;
 507 }
 508 #endif
 509
 510 #ifdef CONFIG_PM
 511 static const struct dev_pm_ops sdhci_pxav3_pmops = {
 512         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
 513         SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
 514                 sdhci_pxav3_runtime_resume, NULL)
 515 };
 516
 517 #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
 518
 519 #else
 520 #define SDHCI_PXAV3_PMOPS NULL
 521 #endif
 522
 523 static struct platform_driver sdhci_pxav3_driver = {
 524         .driver         = {
 525                 .name   = "sdhci-pxav3",
 526 #ifdef CONFIG_OF
 527                 .of_match_table = sdhci_pxav3_of_match,
 528 #endif
 529                 .pm     = SDHCI_PXAV3_PMOPS,
 530         },
 531         .probe          = sdhci_pxav3_probe,
 532         .remove         = sdhci_pxav3_remove,
 533 };
 534
 535 module_platform_driver(sdhci_pxav3_driver);
 536
 537 MODULE_DESCRIPTION("SDHCI driver for pxav3");
 538 MODULE_AUTHOR("Marvell International Ltd.");
 539 MODULE_LICENSE("GPL v2");
 540