2 * Copyright (C) 2011 Andes Technology Corporation
3 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <faraday/ftsdc010.h>
33 * setting the number CONFIG_FTSDC010_NUMBER in your configuration file.
35 static struct mmc ftsdc010_dev[CONFIG_FTSDC010_NUMBER];
36 static struct mmc_host ftsdc010_host[CONFIG_FTSDC010_NUMBER];
38 static struct ftsdc010_mmc *ftsdc010_get_base_mmc(int dev_index)
40 return (struct ftsdc010_mmc *)CONFIG_FTSDC010_BASE + dev_index;
44 static void ftsdc010_dump_reg(struct mmc_host *host)
46 debug("cmd: %08x\n", readl(&host->reg->cmd));
47 debug("argu: %08x\n", readl(&host->reg->argu));
48 debug("rsp0: %08x\n", readl(&host->reg->rsp0));
49 debug("rsp1: %08x\n", readl(&host->reg->rsp1));
50 debug("rsp2: %08x\n", readl(&host->reg->rsp2));
51 debug("rsp3: %08x\n", readl(&host->reg->rsp3));
52 debug("rsp_cmd: %08x\n", readl(&host->reg->rsp_cmd));
53 debug("dcr: %08x\n", readl(&host->reg->dcr));
54 debug("dtr: %08x\n", readl(&host->reg->dtr));
55 debug("dlr: %08x\n", readl(&host->reg->dlr));
56 debug("status: %08x\n", readl(&host->reg->status));
57 debug("clr: %08x\n", readl(&host->reg->clr));
58 debug("int_mask: %08x\n", readl(&host->reg->int_mask));
59 debug("pcr: %08x\n", readl(&host->reg->pcr));
60 debug("ccr: %08x\n", readl(&host->reg->ccr));
61 debug("bwr: %08x\n", readl(&host->reg->bwr));
62 debug("dwr: %08x\n", readl(&host->reg->dwr));
63 debug("feature: %08x\n", readl(&host->reg->feature));
64 debug("rev: %08x\n", readl(&host->reg->rev));
68 static unsigned int enable_imask(struct ftsdc010_mmc *reg, unsigned int imask)
72 newmask = readl(®->int_mask);
75 writel(newmask, ®->int_mask);
80 static void ftsdc010_pio_read(struct mmc_host *host, char *buf, unsigned int size)
83 unsigned int fifo_words;
86 unsigned int retry = 0;
89 ptr = (unsigned int *)buf;
92 status = readl(&host->reg->status);
94 if (status & FTSDC010_STATUS_FIFO_ORUN) {
95 fifo = host->fifo_len > size ?
96 size : host->fifo_len;
100 fifo_words = fifo >> 2;
103 *ptr++ = readl(&host->reg->dwr);
106 * for adding some delays for SD card to put
107 * data into FIFO again
109 udelay(4*FTSDC010_DELAY_UNIT);
111 #ifdef CONFIG_FTSDC010_SDIO
112 /* sdio allow non-power-of-2 blksz */
114 unsigned int n = fifo & 3;
115 unsigned int data = readl(&host->reg->dwr);
117 unsigned char *p = (unsigned char *)ptr;
127 if (++retry >= FTSDC010_PIO_RETRY) {
128 debug("%s: PIO_RETRY timeout\n", __func__);
135 static void ftsdc010_pio_write(struct mmc_host *host, const char *buf,
141 unsigned int retry = 0;
143 /* get data buffer */
144 ptr = (unsigned int *)buf;
147 status = readl(&host->reg->status);
149 if (status & FTSDC010_STATUS_FIFO_ORUN) {
150 fifo = host->fifo_len > size ?
151 size : host->fifo_len;
155 fifo = (fifo + 3) >> 2;
158 writel(*ptr, &host->reg->dwr);
164 if (++retry >= FTSDC010_PIO_RETRY) {
165 debug("%s: PIO_RETRY timeout\n", __func__);
172 static int ftsdc010_pio_check_status(struct mmc *mmc, struct mmc_cmd *cmd,
173 struct mmc_data *data)
175 struct mmc_host *host = mmc->priv;
177 unsigned int sta, clear;
180 /* check response and hardware status */
184 for (i = 0; i < FTSDC010_CMD_RETRY; i++) {
185 sta = readl(&host->reg->status);
186 /* Command Complete */
187 if (sta & FTSDC010_STATUS_CMD_SEND) {
189 clear |= FTSDC010_CLR_CMD_SEND;
194 if (i > FTSDC010_CMD_RETRY) {
195 printf("%s: send command timeout\n", __func__);
199 /* debug: print status register and command index*/
200 debug("sta: %08x cmd %d\n", sta, cmd->cmdidx);
202 /* handle data FIFO */
203 if ((sta & FTSDC010_STATUS_FIFO_ORUN) ||
204 (sta & FTSDC010_STATUS_FIFO_URUN)) {
206 /* Wrong DATA FIFO Flag */
208 printf("%s, data fifo wrong: sta: %08x cmd %d\n",
209 __func__, sta, cmd->cmdidx);
211 if (sta & FTSDC010_STATUS_FIFO_ORUN)
212 clear |= FTSDC010_STATUS_FIFO_ORUN;
213 if (sta & FTSDC010_STATUS_FIFO_URUN)
214 clear |= FTSDC010_STATUS_FIFO_URUN;
217 /* check RSP TIMEOUT or FAIL */
218 if (sta & FTSDC010_STATUS_RSP_TIMEOUT) {
220 debug("%s: RSP timeout: sta: %08x cmd %d\n",
221 __func__, sta, cmd->cmdidx);
223 clear |= FTSDC010_CLR_RSP_TIMEOUT;
224 writel(clear, &host->reg->clr);
227 } else if (sta & FTSDC010_STATUS_RSP_CRC_FAIL) {
228 /* clear response fail bit */
229 debug("%s: RSP CRC FAIL: sta: %08x cmd %d\n",
230 __func__, sta, cmd->cmdidx);
232 clear |= FTSDC010_CLR_RSP_CRC_FAIL;
233 writel(clear, &host->reg->clr);
236 } else if (sta & FTSDC010_STATUS_RSP_CRC_OK) {
238 /* clear response CRC OK bit */
239 clear |= FTSDC010_CLR_RSP_CRC_OK;
242 /* check DATA TIMEOUT or FAIL */
244 if (sta & FTSDC010_STATUS_DATA_TIMEOUT) {
246 debug("%s: DATA TIMEOUT: sta: %08x\n",
249 clear |= FTSDC010_STATUS_DATA_TIMEOUT;
250 writel(sta, &host->reg->clr);
252 } else if (sta & FTSDC010_STATUS_DATA_CRC_FAIL) {
253 /* Error Interrupt */
254 debug("%s: DATA CRC FAIL: sta: %08x\n",
257 clear |= FTSDC010_STATUS_DATA_CRC_FAIL;
258 writel(clear, &host->reg->clr);
261 } else if (sta & FTSDC010_STATUS_DATA_END) {
262 /* Transfer Complete */
263 clear |= FTSDC010_STATUS_DATA_END;
267 /* transaction is success and clear status register */
268 writel(clear, &host->reg->clr);
273 static int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
274 struct mmc_data *data)
276 struct mmc_host *host = mmc->priv;
278 #ifdef CONFIG_FTSDC010_SDIO
282 unsigned int mask, tmpmask;
286 mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
287 else if (cmd->resp_type & MMC_RSP_PRESENT)
288 mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
290 mask = FTSDC010_INT_MASK_CMD_SEND;
293 debug("%s: cmd->arg: %08x\n", __func__, cmd->cmdarg);
294 writel(cmd->cmdarg, &host->reg->argu);
297 debug("cmd: %d\n", cmd->cmdidx);
298 debug("resp: %08x\n", cmd->resp_type);
301 ccon = FTSDC010_CMD_IDX(cmd->cmdidx);
303 /* setup command flags */
304 ccon |= FTSDC010_CMD_CMD_EN;
307 * This hardware didn't support specific commands for mapping
308 * MMC_RSP_BUSY and MMC_RSP_OPCODE. Hence we don't deal with it.
310 if (cmd->resp_type & MMC_RSP_PRESENT) {
311 ccon |= FTSDC010_CMD_NEED_RSP;
312 mask |= FTSDC010_INT_MASK_RSP_CRC_OK |
313 FTSDC010_INT_MASK_RSP_CRC_FAIL;
316 if (cmd->resp_type & MMC_RSP_136)
317 ccon |= FTSDC010_CMD_LONG_RSP;
319 /* In Linux driver, MMC_CMD_APP_CMD is checked in last_opcode */
320 if (host->last_opcode == MMC_CMD_APP_CMD)
321 ccon |= FTSDC010_CMD_APP_CMD;
323 #ifdef CONFIG_FTSDC010_SDIO
324 scon = readl(&host->reg->sdio_ctrl1);
325 if (host->card_type == MMC_TYPE_SDIO)
326 scon |= FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
328 scon &= ~FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
329 writel(scon, &host->reg->sdio_ctrl1);
332 /* record last opcode for specifing the command type to hardware */
333 host->last_opcode = cmd->cmdidx;
335 /* write int_mask reg */
336 tmpmask = readl(&host->reg->int_mask);
338 writel(tmpmask, &host->reg->int_mask);
341 debug("%s: ccon: %08x\n", __func__, ccon);
342 writel(ccon, &host->reg->cmd);
343 udelay(4*FTSDC010_DELAY_UNIT);
345 /* read/write data */
346 if (data && (data->flags & MMC_DATA_READ)) {
347 ftsdc010_pio_read(host, data->dest,
348 data->blocksize * data->blocks);
349 } else if (data && (data->flags & MMC_DATA_WRITE)) {
350 ftsdc010_pio_write(host, data->src,
351 data->blocksize * data->blocks);
354 /* pio check response status */
355 ret = ftsdc010_pio_check_status(mmc, cmd, data);
357 /* if it is long response */
358 if (ccon & FTSDC010_CMD_LONG_RSP) {
359 cmd->response[0] = readl(&host->reg->rsp3);
360 cmd->response[1] = readl(&host->reg->rsp2);
361 cmd->response[2] = readl(&host->reg->rsp1);
362 cmd->response[3] = readl(&host->reg->rsp0);
365 cmd->response[0] = readl(&host->reg->rsp0);
369 udelay(FTSDC010_DELAY_UNIT);
373 static unsigned int cal_blksz(unsigned int blksz)
375 unsigned int blksztwo = 0;
383 static int ftsdc010_setup_data(struct mmc *mmc, struct mmc_data *data)
385 struct mmc_host *host = mmc->priv;
386 unsigned int dcon, newmask;
388 /* configure data transfer paramter */
392 if (((data->blocksize - 1) & data->blocksize) != 0) {
393 printf("%s: can't do non-power-of 2 sized block transfers"
394 " (blksz %d)\n", __func__, data->blocksize);
399 * We cannot deal with unaligned blocks with more than
400 * one block being transfered.
402 if ((data->blocksize <= 2) && (data->blocks > 1)) {
403 printf("%s: can't do non-word sized block transfers"
404 " (blksz %d)\n", __func__, data->blocksize);
409 dcon = data->blocksize * data->blocks;
410 writel(dcon, &host->reg->dlr);
412 /* write data control */
413 dcon = cal_blksz(data->blocksize);
415 /* add to IMASK register */
416 newmask = (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT);
419 * enable UNDERRUN will trigger interrupt immediatedly
420 * So setup it when rsp is received successfully
422 if (data->flags & MMC_DATA_WRITE) {
423 dcon |= FTSDC010_DCR_DATA_WRITE;
425 dcon &= ~FTSDC010_DCR_DATA_WRITE;
426 newmask |= FTSDC010_STATUS_FIFO_ORUN;
428 enable_imask(host->reg, newmask);
430 #ifdef CONFIG_FTSDC010_SDIO
431 /* always reset fifo since last transfer may fail */
432 dcon |= FTSDC010_DCR_FIFO_RST;
435 dcon = data->blocksize | data->blocks << 15;
436 if (data->blocks > 1)
437 dcon |= FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE;
440 /* enable data transfer which will be pended until cmd is send */
441 dcon |= FTSDC010_DCR_DATA_EN;
442 writel(dcon, &host->reg->dcr);
447 static int ftsdc010_send_request(struct mmc *mmc, struct mmc_cmd *cmd,
448 struct mmc_data *data)
453 ret = ftsdc010_setup_data(mmc, data);
456 printf("%s: setup data error\n", __func__);
460 if ((data->flags & MMC_DATA_BOTH_DIR) == MMC_DATA_BOTH_DIR) {
461 printf("%s: data is both direction\n", __func__);
467 ret = ftsdc010_send_cmd(mmc, cmd, data);
471 static int ftsdc010_card_detect(struct mmc *mmc)
473 struct mmc_host *host = mmc->priv;
476 sta = readl(&host->reg->status);
477 debug("%s: card status: %08x\n", __func__, sta);
479 return (sta & FTSDC010_STATUS_CARD_DETECT) ? 0 : 1;
482 static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
483 struct mmc_data *data)
487 if (ftsdc010_card_detect(mmc) == 0) {
488 printf("%s: no medium present\n", __func__);
491 ret = ftsdc010_send_request(mmc, cmd, data);
496 static void ftsdc010_set_clk(struct mmc *mmc)
498 struct mmc_host *host = mmc->priv;
499 unsigned char clk_div;
500 unsigned char real_rate;
503 debug("%s: mmc_set_clock: %x\n", __func__, mmc->clock);
504 clock = readl(&host->reg->ccr);
506 if (mmc->clock == 0) {
508 clock |= FTSDC010_CCR_CLK_DIS;
510 debug("%s, mmc->clock: %08x, origin clock: %08x\n",
511 __func__, mmc->clock, clock);
513 for (clk_div = 0; clk_div <= 127; clk_div++) {
514 real_rate = (CONFIG_SYS_CLK_FREQ / 2) /
517 if (real_rate <= mmc->clock)
521 debug("%s: computed real_rete: %x, clk_div: %x\n",
522 __func__, real_rate, clk_div);
525 debug("%s: no match clock rate, %x\n",
526 __func__, mmc->clock);
528 clock = (clock & ~FTSDC010_CCR_CLK_DIV(0x7f)) |
529 FTSDC010_CCR_CLK_DIV(clk_div);
531 clock &= ~FTSDC010_CCR_CLK_DIS;
534 debug("%s, set clock: %08x\n", __func__, clock);
535 writel(clock, &host->reg->ccr);
538 static void ftsdc010_set_ios(struct mmc *mmc)
540 struct mmc_host *host = mmc->priv;
543 unsigned int bus_width;
545 debug("%s: bus_width: %x, clock: %d\n",
546 __func__, mmc->bus_width, mmc->clock);
548 /* set pcr: power on */
549 power = readl(&host->reg->pcr);
550 power |= FTSDC010_PCR_POWER_ON;
551 writel(power, &host->reg->pcr);
554 ftsdc010_set_clk(mmc);
556 /* set bwr: bus width reg */
557 bus_width = readl(&host->reg->bwr);
558 bus_width &= ~(FTSDC010_BWR_WIDE_8_BUS | FTSDC010_BWR_WIDE_4_BUS |
559 FTSDC010_BWR_SINGLE_BUS);
561 if (mmc->bus_width == 8)
562 bus_width |= FTSDC010_BWR_WIDE_8_BUS;
563 else if (mmc->bus_width == 4)
564 bus_width |= FTSDC010_BWR_WIDE_4_BUS;
566 bus_width |= FTSDC010_BWR_SINGLE_BUS;
568 writel(bus_width, &host->reg->bwr);
571 val = readl(&host->reg->feature);
572 host->fifo_len = FTSDC010_FEATURE_FIFO_DEPTH(val) * 4; /* 4 bytes */
574 /* set data timeout register */
576 writel(val, &host->reg->dtr);
579 static void ftsdc010_reset(struct mmc_host *host)
581 unsigned int timeout;
583 /* Do SDC_RST: Software reset for all register */
584 writel(FTSDC010_CMD_SDC_RST, &host->reg->cmd);
588 /* this hardware has no reset finish flag to read */
589 /* wait 100ms maximum */
592 /* hw clears the bit when it's done */
593 while (readl(&host->reg->dtr) != 0) {
595 printf("%s: reset timeout error\n", __func__);
599 udelay(10*FTSDC010_DELAY_UNIT);
603 static int ftsdc010_core_init(struct mmc *mmc)
605 struct mmc_host *host = mmc->priv;
607 unsigned int major, minor, revision;
609 /* get hardware version */
610 host->version = readl(&host->reg->rev);
612 major = FTSDC010_REV_MAJOR(host->version);
613 minor = FTSDC010_REV_MINOR(host->version);
614 revision = FTSDC010_REV_REVISION(host->version);
616 printf("ftsdc010 hardware ver: %d_%d_r%d\n", major, minor, revision);
618 /* Interrupt MASK register init - mask all */
619 writel(0x0, &host->reg->int_mask);
621 mask = FTSDC010_INT_MASK_CMD_SEND |
622 FTSDC010_INT_MASK_DATA_END |
623 FTSDC010_INT_MASK_CARD_CHANGE;
624 #ifdef CONFIG_FTSDC010_SDIO
625 mask |= FTSDC010_INT_MASK_CP_READY |
626 FTSDC010_INT_MASK_CP_BUF_READY |
627 FTSDC010_INT_MASK_PLAIN_TEXT_READY |
628 FTSDC010_INT_MASK_SDIO_IRPT;
631 writel(mask, &host->reg->int_mask);
636 int ftsdc010_mmc_init(int dev_index)
639 struct mmc_host *host;
641 mmc = &ftsdc010_dev[dev_index];
643 sprintf(mmc->name, "FTSDC010 SD/MMC");
644 mmc->priv = &ftsdc010_host[dev_index];
645 mmc->send_cmd = ftsdc010_request;
646 mmc->set_ios = ftsdc010_set_ios;
647 mmc->init = ftsdc010_core_init;
649 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
651 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
653 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
655 mmc->f_min = CONFIG_SYS_CLK_FREQ / 2 / (2*128);
656 mmc->f_max = CONFIG_SYS_CLK_FREQ / 2 / 2;
658 ftsdc010_host[dev_index].clock = 0;
659 ftsdc010_host[dev_index].reg = ftsdc010_get_base_mmc(dev_index);
663 host = (struct mmc_host *)mmc->priv;
664 ftsdc010_reset(host);