1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
6 * Yangbo Lu <yangbo.lu@nxp.com>
8 * Based vaguely on the pxa mmc code:
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
22 #include <dm/device_compat.h>
23 #include <linux/err.h>
24 #include <power/regulator.h>
26 #include <fsl_esdhc_imx.h>
27 #include <fdt_support.h>
30 #include <asm-generic/gpio.h>
31 #include <dm/pinctrl.h>
33 #if !CONFIG_IS_ENABLED(BLK)
34 #include "mmc_private.h"
37 DECLARE_GLOBAL_DATA_PTR;
39 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
41 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
42 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
43 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
45 #define MAX_TUNING_LOOP 40
46 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
49 uint dsaddr; /* SDMA system address register */
50 uint blkattr; /* Block attributes register */
51 uint cmdarg; /* Command argument register */
52 uint xfertyp; /* Transfer type register */
53 uint cmdrsp0; /* Command response 0 register */
54 uint cmdrsp1; /* Command response 1 register */
55 uint cmdrsp2; /* Command response 2 register */
56 uint cmdrsp3; /* Command response 3 register */
57 uint datport; /* Buffer data port register */
58 uint prsstat; /* Present state register */
59 uint proctl; /* Protocol control register */
60 uint sysctl; /* System Control Register */
61 uint irqstat; /* Interrupt status register */
62 uint irqstaten; /* Interrupt status enable register */
63 uint irqsigen; /* Interrupt signal enable register */
64 uint autoc12err; /* Auto CMD error status register */
65 uint hostcapblt; /* Host controller capabilities register */
66 uint wml; /* Watermark level register */
67 uint mixctrl; /* For USDHC */
68 char reserved1[4]; /* reserved */
69 uint fevt; /* Force event register */
70 uint admaes; /* ADMA error status register */
71 uint adsaddr; /* ADMA system address register */
75 uint clktunectrlstatus;
83 uint tuning_ctrl; /* on i.MX6/7/8/RT */
85 uint hostver; /* Host controller version register */
86 char reserved6[4]; /* reserved */
87 uint dmaerraddr; /* DMA error address register */
88 char reserved7[4]; /* reserved */
89 uint dmaerrattr; /* DMA error attribute register */
90 char reserved8[4]; /* reserved */
91 uint hostcapblt2; /* Host controller capabilities register 2 */
92 char reserved9[8]; /* reserved */
93 uint tcr; /* Tuning control register */
94 char reserved10[28]; /* reserved */
95 uint sddirctl; /* SD direction control register */
96 char reserved11[712];/* reserved */
97 uint scr; /* eSDHC control register */
100 struct fsl_esdhc_plat {
101 struct mmc_config cfg;
105 struct esdhc_soc_data {
110 * struct fsl_esdhc_priv
112 * @esdhc_regs: registers of the sdhc controller
113 * @sdhc_clk: Current clk of the sdhc controller
114 * @bus_width: bus width, 1bit, 4bit or 8bit
117 * Following is used when Driver Model is enabled for MMC
118 * @dev: pointer for the device
119 * @non_removable: 0: removable; 1: non-removable
120 * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
121 * @wp_enable: 1: enable checking wp; 0: no check
122 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
123 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
124 * @caps: controller capabilities
125 * @tuning_step: tuning step setting in tuning_ctrl register
126 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
127 * @strobe_dll_delay_target: settings in strobe_dllctrl
128 * @signal_voltage: indicating the current voltage
129 * @cd_gpio: gpio for card detection
130 * @wp_gpio: gpio for write protection
132 struct fsl_esdhc_priv {
133 struct fsl_esdhc *esdhc_regs;
134 unsigned int sdhc_clk;
138 unsigned int bus_width;
139 #if !CONFIG_IS_ENABLED(BLK)
150 u32 tuning_start_tap;
151 u32 strobe_dll_delay_target;
153 #if CONFIG_IS_ENABLED(DM_REGULATOR)
154 struct udevice *vqmmc_dev;
155 struct udevice *vmmc_dev;
157 #if CONFIG_IS_ENABLED(DM_GPIO)
158 struct gpio_desc cd_gpio;
159 struct gpio_desc wp_gpio;
163 /* Return the XFERTYP flags for a given command and data packet */
164 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
169 xfertyp |= XFERTYP_DPSEL;
170 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
171 xfertyp |= XFERTYP_DMAEN;
173 if (data->blocks > 1) {
174 xfertyp |= XFERTYP_MSBSEL;
175 xfertyp |= XFERTYP_BCEN;
176 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
177 xfertyp |= XFERTYP_AC12EN;
181 if (data->flags & MMC_DATA_READ)
182 xfertyp |= XFERTYP_DTDSEL;
185 if (cmd->resp_type & MMC_RSP_CRC)
186 xfertyp |= XFERTYP_CCCEN;
187 if (cmd->resp_type & MMC_RSP_OPCODE)
188 xfertyp |= XFERTYP_CICEN;
189 if (cmd->resp_type & MMC_RSP_136)
190 xfertyp |= XFERTYP_RSPTYP_136;
191 else if (cmd->resp_type & MMC_RSP_BUSY)
192 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
193 else if (cmd->resp_type & MMC_RSP_PRESENT)
194 xfertyp |= XFERTYP_RSPTYP_48;
196 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
197 xfertyp |= XFERTYP_CMDTYP_ABORT;
199 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
202 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
204 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
206 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
207 struct mmc_data *data)
209 struct fsl_esdhc *regs = priv->esdhc_regs;
217 if (data->flags & MMC_DATA_READ) {
218 blocks = data->blocks;
221 start = get_timer(0);
222 size = data->blocksize;
223 irqstat = esdhc_read32(®s->irqstat);
224 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
225 if (get_timer(start) > PIO_TIMEOUT) {
226 printf("\nData Read Failed in PIO Mode.");
230 while (size && (!(irqstat & IRQSTAT_TC))) {
231 udelay(100); /* Wait before last byte transfer complete */
232 irqstat = esdhc_read32(®s->irqstat);
233 databuf = in_le32(®s->datport);
234 *((uint *)buffer) = databuf;
241 blocks = data->blocks;
242 buffer = (char *)data->src;
244 start = get_timer(0);
245 size = data->blocksize;
246 irqstat = esdhc_read32(®s->irqstat);
247 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
248 if (get_timer(start) > PIO_TIMEOUT) {
249 printf("\nData Write Failed in PIO Mode.");
253 while (size && (!(irqstat & IRQSTAT_TC))) {
254 udelay(100); /* Wait before last byte transfer complete */
255 databuf = *((uint *)buffer);
258 irqstat = esdhc_read32(®s->irqstat);
259 out_le32(®s->datport, databuf);
267 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
268 struct mmc_data *data)
271 struct fsl_esdhc *regs = priv->esdhc_regs;
272 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
277 wml_value = data->blocksize/4;
279 if (data->flags & MMC_DATA_READ) {
280 if (wml_value > WML_RD_WML_MAX)
281 wml_value = WML_RD_WML_MAX_VAL;
283 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
284 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
285 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
286 addr = virt_to_phys((void *)(data->dest));
287 if (upper_32_bits(addr))
288 printf("Error found for upper 32 bits\n");
290 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
292 esdhc_write32(®s->dsaddr, (u32)data->dest);
296 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
297 flush_dcache_range((ulong)data->src,
298 (ulong)data->src+data->blocks
301 if (wml_value > WML_WR_WML_MAX)
302 wml_value = WML_WR_WML_MAX_VAL;
303 if (priv->wp_enable) {
304 if ((esdhc_read32(®s->prsstat) &
305 PRSSTAT_WPSPL) == 0) {
306 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
310 #if CONFIG_IS_ENABLED(DM_GPIO)
311 if (dm_gpio_is_valid(&priv->wp_gpio) &&
312 dm_gpio_get_value(&priv->wp_gpio)) {
313 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
319 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
321 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
322 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
323 addr = virt_to_phys((void *)(data->src));
324 if (upper_32_bits(addr))
325 printf("Error found for upper 32 bits\n");
327 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
329 esdhc_write32(®s->dsaddr, (u32)data->src);
334 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
336 /* Calculate the timeout period for data transactions */
338 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
339 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
340 * So, Number of SD Clock cycles for 0.25sec should be minimum
341 * (SD Clock/sec * 0.25 sec) SD Clock cycles
342 * = (mmc->clock * 1/4) SD Clock cycles
344 * => (2^(timeout+13)) >= mmc->clock * 1/4
345 * Taking log2 both the sides
346 * => timeout + 13 >= log2(mmc->clock/4)
347 * Rounding up to next power of 2
348 * => timeout + 13 = log2(mmc->clock/4) + 1
349 * => timeout + 13 = fls(mmc->clock/4)
351 * However, the MMC spec "It is strongly recommended for hosts to
352 * implement more than 500ms timeout value even if the card
353 * indicates the 250ms maximum busy length." Even the previous
354 * value of 300ms is known to be insufficient for some cards.
356 * => timeout + 13 = fls(mmc->clock/2)
358 timeout = fls(mmc->clock/2);
367 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
368 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
372 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
375 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
380 static void check_and_invalidate_dcache_range
381 (struct mmc_cmd *cmd,
382 struct mmc_data *data) {
385 unsigned size = roundup(ARCH_DMA_MINALIGN,
386 data->blocks*data->blocksize);
387 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
390 addr = virt_to_phys((void *)(data->dest));
391 if (upper_32_bits(addr))
392 printf("Error found for upper 32 bits\n");
394 start = lower_32_bits(addr);
396 start = (unsigned)data->dest;
399 invalidate_dcache_range(start, end);
402 #ifdef CONFIG_MCF5441x
404 * Swaps 32-bit words to little-endian byte order.
406 static inline void sd_swap_dma_buff(struct mmc_data *data)
408 int i, size = data->blocksize >> 2;
409 u32 *buffer = (u32 *)data->dest;
412 while (data->blocks--) {
413 for (i = 0; i < size; i++) {
414 sw = __sw32(*buffer);
422 * Sends a command out on the bus. Takes the mmc pointer,
423 * a command pointer, and an optional data pointer.
425 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
426 struct mmc_cmd *cmd, struct mmc_data *data)
431 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
432 struct fsl_esdhc *regs = priv->esdhc_regs;
435 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
436 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
440 esdhc_write32(®s->irqstat, -1);
444 /* Wait for the bus to be idle */
445 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
446 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
449 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
452 /* Wait at least 8 SD clock cycles before the next command */
454 * Note: This is way more than 8 cycles, but 1ms seems to
455 * resolve timing issues with some cards
459 /* Set up for a data transfer if we have one */
461 err = esdhc_setup_data(priv, mmc, data);
465 if (data->flags & MMC_DATA_READ)
466 check_and_invalidate_dcache_range(cmd, data);
469 /* Figure out the transfer arguments */
470 xfertyp = esdhc_xfertyp(cmd, data);
473 esdhc_write32(®s->irqsigen, 0);
475 /* Send the command */
476 esdhc_write32(®s->cmdarg, cmd->cmdarg);
477 #if defined(CONFIG_FSL_USDHC)
478 esdhc_write32(®s->mixctrl,
479 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
480 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
481 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
483 esdhc_write32(®s->xfertyp, xfertyp);
486 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
487 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
490 /* Wait for the command to complete */
491 start = get_timer(0);
492 while (!(esdhc_read32(®s->irqstat) & flags)) {
493 if (get_timer(start) > 1000) {
499 irqstat = esdhc_read32(®s->irqstat);
501 if (irqstat & CMD_ERR) {
506 if (irqstat & IRQSTAT_CTOE) {
511 /* Switch voltage to 1.8V if CMD11 succeeded */
512 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
513 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
515 printf("Run CMD11 1.8V switch\n");
516 /* Sleep for 5 ms - max time for card to switch to 1.8V */
520 /* Workaround for ESDHC errata ENGcm03648 */
521 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
524 /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
525 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
532 printf("Timeout waiting for DAT0 to go high!\n");
538 /* Copy the response to the response buffer */
539 if (cmd->resp_type & MMC_RSP_136) {
540 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
542 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
543 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
544 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
545 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
546 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
547 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
548 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
549 cmd->response[3] = (cmdrsp0 << 8);
551 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
553 /* Wait until all of the blocks are transferred */
555 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
556 esdhc_pio_read_write(priv, data);
558 flags = DATA_COMPLETE;
559 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
560 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
565 irqstat = esdhc_read32(®s->irqstat);
567 if (irqstat & IRQSTAT_DTOE) {
572 if (irqstat & DATA_ERR) {
576 } while ((irqstat & flags) != flags);
579 * Need invalidate the dcache here again to avoid any
580 * cache-fill during the DMA operations such as the
581 * speculative pre-fetching etc.
583 if (data->flags & MMC_DATA_READ) {
584 check_and_invalidate_dcache_range(cmd, data);
585 #ifdef CONFIG_MCF5441x
586 sd_swap_dma_buff(data);
593 /* Reset CMD and DATA portions on error */
595 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
597 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
601 esdhc_write32(®s->sysctl,
602 esdhc_read32(®s->sysctl) |
604 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
608 /* If this was CMD11, then notify that power cycle is needed */
609 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
610 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
613 esdhc_write32(®s->irqstat, -1);
618 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
620 struct fsl_esdhc *regs = priv->esdhc_regs;
624 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
625 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
632 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
633 int sdhc_clk = priv->sdhc_clk;
636 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
639 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
645 clk = (pre_div << 8) | (div << 4);
647 #ifdef CONFIG_FSL_USDHC
648 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
650 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
653 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
657 #ifdef CONFIG_FSL_USDHC
658 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
660 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
666 #ifdef MMC_SUPPORTS_TUNING
667 static int esdhc_change_pinstate(struct udevice *dev)
669 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
672 switch (priv->mode) {
675 ret = pinctrl_select_state(dev, "state_100mhz");
681 ret = pinctrl_select_state(dev, "state_200mhz");
684 ret = pinctrl_select_state(dev, "default");
689 printf("%s %d error\n", __func__, priv->mode);
694 static void esdhc_reset_tuning(struct mmc *mmc)
696 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
697 struct fsl_esdhc *regs = priv->esdhc_regs;
699 if (priv->flags & ESDHC_FLAG_USDHC) {
700 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
701 esdhc_clrbits32(®s->autoc12err,
702 MIX_CTRL_SMPCLK_SEL |
708 static void esdhc_set_strobe_dll(struct mmc *mmc)
710 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
711 struct fsl_esdhc *regs = priv->esdhc_regs;
714 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
715 writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
718 * enable strobe dll ctrl and adjust the delay target
719 * for the uSDHC loopback read clock
721 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
722 (priv->strobe_dll_delay_target <<
723 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
724 writel(val, ®s->strobe_dllctrl);
725 /* wait 1us to make sure strobe dll status register stable */
727 val = readl(®s->strobe_dllstat);
728 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
729 pr_warn("HS400 strobe DLL status REF not lock!\n");
730 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
731 pr_warn("HS400 strobe DLL status SLV not lock!\n");
735 static int esdhc_set_timing(struct mmc *mmc)
737 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
738 struct fsl_esdhc *regs = priv->esdhc_regs;
741 mixctrl = readl(®s->mixctrl);
742 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
744 switch (mmc->selected_mode) {
746 esdhc_reset_tuning(mmc);
747 writel(mixctrl, ®s->mixctrl);
751 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
752 writel(mixctrl, ®s->mixctrl);
753 esdhc_set_strobe_dll(mmc);
763 writel(mixctrl, ®s->mixctrl);
767 mixctrl |= MIX_CTRL_DDREN;
768 writel(mixctrl, ®s->mixctrl);
771 printf("Not supported %d\n", mmc->selected_mode);
775 priv->mode = mmc->selected_mode;
777 return esdhc_change_pinstate(mmc->dev);
780 static int esdhc_set_voltage(struct mmc *mmc)
782 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
783 struct fsl_esdhc *regs = priv->esdhc_regs;
786 priv->signal_voltage = mmc->signal_voltage;
787 switch (mmc->signal_voltage) {
788 case MMC_SIGNAL_VOLTAGE_330:
789 if (priv->vs18_enable)
791 #if CONFIG_IS_ENABLED(DM_REGULATOR)
792 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
793 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
795 printf("Setting to 3.3V error");
803 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
804 if (!(esdhc_read32(®s->vendorspec) &
805 ESDHC_VENDORSPEC_VSELECT))
809 case MMC_SIGNAL_VOLTAGE_180:
810 #if CONFIG_IS_ENABLED(DM_REGULATOR)
811 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
812 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
814 printf("Setting to 1.8V error");
819 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
820 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
824 case MMC_SIGNAL_VOLTAGE_120:
831 static void esdhc_stop_tuning(struct mmc *mmc)
835 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
837 cmd.resp_type = MMC_RSP_R1b;
839 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
842 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
844 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
845 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
846 struct fsl_esdhc *regs = priv->esdhc_regs;
847 struct mmc *mmc = &plat->mmc;
848 u32 irqstaten = readl(®s->irqstaten);
849 u32 irqsigen = readl(®s->irqsigen);
850 int i, ret = -ETIMEDOUT;
853 /* clock tuning is not needed for upto 52MHz */
854 if (mmc->clock <= 52000000)
857 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
858 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
859 val = readl(®s->autoc12err);
860 mixctrl = readl(®s->mixctrl);
861 val &= ~MIX_CTRL_SMPCLK_SEL;
862 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
864 val |= MIX_CTRL_EXE_TUNE;
865 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
867 writel(val, ®s->autoc12err);
868 writel(mixctrl, ®s->mixctrl);
871 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
872 mixctrl = readl(®s->mixctrl);
873 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
874 writel(mixctrl, ®s->mixctrl);
876 writel(IRQSTATEN_BRR, ®s->irqstaten);
877 writel(IRQSTATEN_BRR, ®s->irqsigen);
880 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
881 * of loops reaches 40 times.
883 for (i = 0; i < MAX_TUNING_LOOP; i++) {
886 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
887 if (mmc->bus_width == 8)
888 writel(0x7080, ®s->blkattr);
889 else if (mmc->bus_width == 4)
890 writel(0x7040, ®s->blkattr);
892 writel(0x7040, ®s->blkattr);
895 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
896 val = readl(®s->mixctrl);
897 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
898 writel(val, ®s->mixctrl);
900 /* We are using STD tuning, no need to check return value */
901 mmc_send_tuning(mmc, opcode, NULL);
903 ctrl = readl(®s->autoc12err);
904 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
905 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
907 * need to wait some time, make sure sd/mmc fininsh
908 * send out tuning data, otherwise, the sd/mmc can't
909 * response to any command when the card still out
910 * put the tuning data.
917 /* Add 1ms delay for SD and eMMC */
921 writel(irqstaten, ®s->irqstaten);
922 writel(irqsigen, ®s->irqsigen);
924 esdhc_stop_tuning(mmc);
930 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
932 struct fsl_esdhc *regs = priv->esdhc_regs;
933 int ret __maybe_unused;
936 /* Set the clock speed */
938 if (clock < mmc->cfg->f_min)
939 clock = mmc->cfg->f_min;
941 if (priv->clock != clock)
942 set_sysctl(priv, mmc, clock);
944 #ifdef MMC_SUPPORTS_TUNING
945 if (mmc->clk_disable) {
946 #ifdef CONFIG_FSL_USDHC
947 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
949 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
952 #ifdef CONFIG_FSL_USDHC
953 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
956 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
960 if (priv->mode != mmc->selected_mode) {
961 ret = esdhc_set_timing(mmc);
963 printf("esdhc_set_timing error %d\n", ret);
968 if (priv->signal_voltage != mmc->signal_voltage) {
969 ret = esdhc_set_voltage(mmc);
971 printf("esdhc_set_voltage error %d\n", ret);
977 /* Set the bus width */
978 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
980 if (mmc->bus_width == 4)
981 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
982 else if (mmc->bus_width == 8)
983 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
988 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
990 struct fsl_esdhc *regs = priv->esdhc_regs;
993 /* Reset the entire host controller */
994 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
996 /* Wait until the controller is available */
997 start = get_timer(0);
998 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
999 if (get_timer(start) > 1000)
1003 #if defined(CONFIG_FSL_USDHC)
1004 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1005 esdhc_write32(®s->mmcboot, 0x0);
1006 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1007 esdhc_write32(®s->mixctrl, 0x0);
1008 esdhc_write32(®s->clktunectrlstatus, 0x0);
1010 /* Put VEND_SPEC to default value */
1011 if (priv->vs18_enable)
1012 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1013 ESDHC_VENDORSPEC_VSELECT));
1015 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1017 /* Disable DLL_CTRL delay line */
1018 esdhc_write32(®s->dllctrl, 0x0);
1022 /* Enable cache snooping */
1023 esdhc_write32(®s->scr, 0x00000040);
1026 #ifndef CONFIG_FSL_USDHC
1027 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1029 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1032 /* Set the initial clock speed */
1033 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1035 /* Disable the BRR and BWR bits in IRQSTAT */
1036 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1038 #ifdef CONFIG_MCF5441x
1039 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1041 /* Put the PROCTL reg back to the default */
1042 esdhc_write32(®s->proctl, PROCTL_INIT);
1045 /* Set timout to the maximum value */
1046 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1051 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1053 struct fsl_esdhc *regs = priv->esdhc_regs;
1056 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1057 if (CONFIG_ESDHC_DETECT_QUIRK)
1061 #if CONFIG_IS_ENABLED(DM_MMC)
1062 if (priv->non_removable)
1065 if (priv->broken_cd)
1067 #if CONFIG_IS_ENABLED(DM_GPIO)
1068 if (dm_gpio_is_valid(&priv->cd_gpio))
1069 return dm_gpio_get_value(&priv->cd_gpio);
1073 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1079 static int esdhc_reset(struct fsl_esdhc *regs)
1083 /* reset the controller */
1084 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1086 /* hardware clears the bit when it is done */
1087 start = get_timer(0);
1088 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1089 if (get_timer(start) > 100) {
1090 printf("MMC/SD: Reset never completed.\n");
1098 #if !CONFIG_IS_ENABLED(DM_MMC)
1099 static int esdhc_getcd(struct mmc *mmc)
1101 struct fsl_esdhc_priv *priv = mmc->priv;
1103 return esdhc_getcd_common(priv);
1106 static int esdhc_init(struct mmc *mmc)
1108 struct fsl_esdhc_priv *priv = mmc->priv;
1110 return esdhc_init_common(priv, mmc);
1113 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1114 struct mmc_data *data)
1116 struct fsl_esdhc_priv *priv = mmc->priv;
1118 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1121 static int esdhc_set_ios(struct mmc *mmc)
1123 struct fsl_esdhc_priv *priv = mmc->priv;
1125 return esdhc_set_ios_common(priv, mmc);
1128 static const struct mmc_ops esdhc_ops = {
1129 .getcd = esdhc_getcd,
1131 .send_cmd = esdhc_send_cmd,
1132 .set_ios = esdhc_set_ios,
1136 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1137 struct fsl_esdhc_plat *plat)
1139 struct mmc_config *cfg;
1140 struct fsl_esdhc *regs;
1141 u32 caps, voltage_caps;
1147 regs = priv->esdhc_regs;
1149 /* First reset the eSDHC controller */
1150 ret = esdhc_reset(regs);
1154 #ifdef CONFIG_MCF5441x
1155 /* ColdFire, using SDHC_DATA[3] for card detection */
1156 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1159 #ifndef CONFIG_FSL_USDHC
1160 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1161 | SYSCTL_IPGEN | SYSCTL_CKEN);
1162 /* Clearing tuning bits in case ROM has set it already */
1163 esdhc_write32(®s->mixctrl, 0);
1164 esdhc_write32(®s->autoc12err, 0);
1165 esdhc_write32(®s->clktunectrlstatus, 0);
1167 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1168 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1171 if (priv->vs18_enable)
1172 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1174 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
1176 #ifndef CONFIG_DM_MMC
1177 memset(cfg, '\0', sizeof(*cfg));
1181 caps = esdhc_read32(®s->hostcapblt);
1183 #ifdef CONFIG_MCF5441x
1185 * MCF5441x RM declares in more points that sdhc clock speed must
1186 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1187 * from host capabilities.
1189 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1192 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1193 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1194 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1197 /* T4240 host controller capabilities register should have VS33 bit */
1198 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1199 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1202 if (caps & ESDHC_HOSTCAPBLT_VS18)
1203 voltage_caps |= MMC_VDD_165_195;
1204 if (caps & ESDHC_HOSTCAPBLT_VS30)
1205 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1206 if (caps & ESDHC_HOSTCAPBLT_VS33)
1207 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1209 cfg->name = "FSL_SDHC";
1210 #if !CONFIG_IS_ENABLED(DM_MMC)
1211 cfg->ops = &esdhc_ops;
1213 #ifdef CONFIG_SYS_SD_VOLTAGE
1214 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1216 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1218 if ((cfg->voltages & voltage_caps) == 0) {
1219 printf("voltage not supported by controller\n");
1223 if (priv->bus_width == 8)
1224 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1225 else if (priv->bus_width == 4)
1226 cfg->host_caps = MMC_MODE_4BIT;
1228 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1229 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1230 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1233 if (priv->bus_width > 0) {
1234 if (priv->bus_width < 8)
1235 cfg->host_caps &= ~MMC_MODE_8BIT;
1236 if (priv->bus_width < 4)
1237 cfg->host_caps &= ~MMC_MODE_4BIT;
1240 if (caps & ESDHC_HOSTCAPBLT_HSS)
1241 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1243 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1244 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1245 cfg->host_caps &= ~MMC_MODE_8BIT;
1248 cfg->host_caps |= priv->caps;
1250 cfg->f_min = 400000;
1251 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1253 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1255 writel(0, ®s->dllctrl);
1256 if (priv->flags & ESDHC_FLAG_USDHC) {
1257 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1258 u32 val = readl(®s->tuning_ctrl);
1260 val |= ESDHC_STD_TUNING_EN;
1261 val &= ~ESDHC_TUNING_START_TAP_MASK;
1262 val |= priv->tuning_start_tap;
1263 val &= ~ESDHC_TUNING_STEP_MASK;
1264 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1265 writel(val, ®s->tuning_ctrl);
1272 #if !CONFIG_IS_ENABLED(DM_MMC)
1273 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1274 struct fsl_esdhc_priv *priv)
1279 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1280 priv->bus_width = cfg->max_bus_width;
1281 priv->sdhc_clk = cfg->sdhc_clk;
1282 priv->wp_enable = cfg->wp_enable;
1283 priv->vs18_enable = cfg->vs18_enable;
1288 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1290 struct fsl_esdhc_plat *plat;
1291 struct fsl_esdhc_priv *priv;
1298 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1301 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1307 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1309 debug("%s xlate failure\n", __func__);
1315 ret = fsl_esdhc_init(priv, plat);
1317 debug("%s init failure\n", __func__);
1323 mmc = mmc_create(&plat->cfg, priv);
1332 int fsl_esdhc_mmc_init(bd_t *bis)
1334 struct fsl_esdhc_cfg *cfg;
1336 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1337 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1338 cfg->sdhc_clk = gd->arch.sdhc_clk;
1339 return fsl_esdhc_initialize(bis, cfg);
1343 #ifdef CONFIG_OF_LIBFDT
1344 __weak int esdhc_status_fixup(void *blob, const char *compat)
1346 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1347 if (!hwconfig("esdhc")) {
1348 do_fixup_by_compat(blob, compat, "status", "disabled",
1349 sizeof("disabled"), 1);
1356 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1358 const char *compat = "fsl,esdhc";
1360 if (esdhc_status_fixup(blob, compat))
1363 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1364 gd->arch.sdhc_clk, 1);
1368 #if CONFIG_IS_ENABLED(DM_MMC)
1369 #include <asm/arch/clock.h>
1370 __weak void init_clk_usdhc(u32 index)
1374 static int fsl_esdhc_probe(struct udevice *dev)
1376 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1377 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1378 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1379 const void *fdt = gd->fdt_blob;
1380 int node = dev_of_offset(dev);
1381 struct esdhc_soc_data *data =
1382 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1383 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1384 struct udevice *vqmmc_dev;
1389 #if !CONFIG_IS_ENABLED(BLK)
1390 struct blk_desc *bdesc;
1394 addr = dev_read_addr(dev);
1395 if (addr == FDT_ADDR_T_NONE)
1397 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1401 priv->flags = data->flags;
1403 val = dev_read_u32_default(dev, "bus-width", -1);
1405 priv->bus_width = 8;
1407 priv->bus_width = 4;
1409 priv->bus_width = 1;
1411 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1412 priv->tuning_step = val;
1413 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1414 ESDHC_TUNING_START_TAP_DEFAULT);
1415 priv->tuning_start_tap = val;
1416 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1417 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1418 priv->strobe_dll_delay_target = val;
1420 if (dev_read_bool(dev, "broken-cd"))
1421 priv->broken_cd = 1;
1423 if (dev_read_bool(dev, "non-removable")) {
1424 priv->non_removable = 1;
1426 priv->non_removable = 0;
1427 #if CONFIG_IS_ENABLED(DM_GPIO)
1428 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1433 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1434 priv->wp_enable = 1;
1436 priv->wp_enable = 0;
1437 #if CONFIG_IS_ENABLED(DM_GPIO)
1438 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1443 priv->vs18_enable = 0;
1445 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1447 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1448 * otherwise, emmc will work abnormally.
1450 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1452 dev_dbg(dev, "no vqmmc-supply\n");
1454 ret = regulator_set_enable(vqmmc_dev, true);
1456 dev_err(dev, "fail to enable vqmmc-supply\n");
1460 if (regulator_get_value(vqmmc_dev) == 1800000)
1461 priv->vs18_enable = 1;
1467 * Because lack of clk driver, if SDHC clk is not enabled,
1468 * need to enable it first before this driver is invoked.
1470 * we use MXC_ESDHC_CLK to get clk freq.
1471 * If one would like to make this function work,
1472 * the aliases should be provided in dts as this:
1480 * Then if your board only supports mmc2 and mmc3, but we can
1481 * correctly get the seq as 2 and 3, then let mxc_get_clock
1485 init_clk_usdhc(dev->seq);
1487 #if CONFIG_IS_ENABLED(CLK)
1488 /* Assigned clock already set clock */
1489 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1491 printf("Failed to get per_clk\n");
1494 ret = clk_enable(&priv->per_clk);
1496 printf("Failed to enable per_clk\n");
1500 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1502 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1503 if (priv->sdhc_clk <= 0) {
1504 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1509 ret = fsl_esdhc_init(priv, plat);
1511 dev_err(dev, "fsl_esdhc_init failure\n");
1515 ret = mmc_of_parse(dev, &plat->cfg);
1520 mmc->cfg = &plat->cfg;
1522 #if !CONFIG_IS_ENABLED(BLK)
1525 /* Setup dsr related values */
1527 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1528 /* Setup the universal parts of the block interface just once */
1529 bdesc = mmc_get_blk_desc(mmc);
1530 bdesc->if_type = IF_TYPE_MMC;
1531 bdesc->removable = 1;
1532 bdesc->devnum = mmc_get_next_devnum();
1533 bdesc->block_read = mmc_bread;
1534 bdesc->block_write = mmc_bwrite;
1535 bdesc->block_erase = mmc_berase;
1537 /* setup initial part type */
1538 bdesc->part_type = mmc->cfg->part_type;
1544 return esdhc_init_common(priv, mmc);
1547 #if CONFIG_IS_ENABLED(DM_MMC)
1548 static int fsl_esdhc_get_cd(struct udevice *dev)
1550 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1552 return esdhc_getcd_common(priv);
1555 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1556 struct mmc_data *data)
1558 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1559 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1561 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1564 static int fsl_esdhc_set_ios(struct udevice *dev)
1566 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1567 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1569 return esdhc_set_ios_common(priv, &plat->mmc);
1572 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1573 static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
1575 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1576 struct fsl_esdhc *regs = priv->esdhc_regs;
1579 m = readl(®s->mixctrl);
1580 m |= MIX_CTRL_HS400_ES;
1581 writel(m, ®s->mixctrl);
1587 static const struct dm_mmc_ops fsl_esdhc_ops = {
1588 .get_cd = fsl_esdhc_get_cd,
1589 .send_cmd = fsl_esdhc_send_cmd,
1590 .set_ios = fsl_esdhc_set_ios,
1591 #ifdef MMC_SUPPORTS_TUNING
1592 .execute_tuning = fsl_esdhc_execute_tuning,
1594 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1595 .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
1600 static struct esdhc_soc_data usdhc_imx7d_data = {
1601 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1602 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1606 static struct esdhc_soc_data usdhc_imx8qm_data = {
1607 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
1608 ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
1609 ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
1612 static const struct udevice_id fsl_esdhc_ids[] = {
1613 { .compatible = "fsl,imx53-esdhc", },
1614 { .compatible = "fsl,imx6ul-usdhc", },
1615 { .compatible = "fsl,imx6sx-usdhc", },
1616 { .compatible = "fsl,imx6sl-usdhc", },
1617 { .compatible = "fsl,imx6q-usdhc", },
1618 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1619 { .compatible = "fsl,imx7ulp-usdhc", },
1620 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1621 { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1622 { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1623 { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1624 { .compatible = "fsl,imxrt-usdhc", },
1625 { .compatible = "fsl,esdhc", },
1629 #if CONFIG_IS_ENABLED(BLK)
1630 static int fsl_esdhc_bind(struct udevice *dev)
1632 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1634 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1638 U_BOOT_DRIVER(fsl_esdhc) = {
1639 .name = "fsl-esdhc-mmc",
1641 .of_match = fsl_esdhc_ids,
1642 .ops = &fsl_esdhc_ops,
1643 #if CONFIG_IS_ENABLED(BLK)
1644 .bind = fsl_esdhc_bind,
1646 .probe = fsl_esdhc_probe,
1647 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1648 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),