2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <fsl_esdhc.h>
37 #include <fdt_support.h>
40 DECLARE_GLOBAL_DATA_PTR;
70 /* Return the XFERTYP flags for a given command and data packet */
71 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
76 xfertyp |= XFERTYP_DPSEL;
77 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
78 xfertyp |= XFERTYP_DMAEN;
80 if (data->blocks > 1) {
81 xfertyp |= XFERTYP_MSBSEL;
82 xfertyp |= XFERTYP_BCEN;
83 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
84 xfertyp |= XFERTYP_AC12EN;
88 if (data->flags & MMC_DATA_READ)
89 xfertyp |= XFERTYP_DTDSEL;
92 if (cmd->resp_type & MMC_RSP_CRC)
93 xfertyp |= XFERTYP_CCCEN;
94 if (cmd->resp_type & MMC_RSP_OPCODE)
95 xfertyp |= XFERTYP_CICEN;
96 if (cmd->resp_type & MMC_RSP_136)
97 xfertyp |= XFERTYP_RSPTYP_136;
98 else if (cmd->resp_type & MMC_RSP_BUSY)
99 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
100 else if (cmd->resp_type & MMC_RSP_PRESENT)
101 xfertyp |= XFERTYP_RSPTYP_48;
104 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
105 xfertyp |= XFERTYP_CMDTYP_ABORT;
107 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
110 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
112 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
115 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
117 struct fsl_esdhc *regs = mmc->priv;
125 if (data->flags & MMC_DATA_READ) {
126 blocks = data->blocks;
129 timeout = PIO_TIMEOUT;
130 size = data->blocksize;
131 irqstat = esdhc_read32(®s->irqstat);
132 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
135 printf("\nData Read Failed in PIO Mode.");
138 while (size && (!(irqstat & IRQSTAT_TC))) {
139 udelay(100); /* Wait before last byte transfer complete */
140 irqstat = esdhc_read32(®s->irqstat);
141 databuf = in_le32(®s->datport);
142 *((uint *)buffer) = databuf;
149 blocks = data->blocks;
150 buffer = (char *)data->src;
152 timeout = PIO_TIMEOUT;
153 size = data->blocksize;
154 irqstat = esdhc_read32(®s->irqstat);
155 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
158 printf("\nData Write Failed in PIO Mode.");
161 while (size && (!(irqstat & IRQSTAT_TC))) {
162 udelay(100); /* Wait before last byte transfer complete */
163 databuf = *((uint *)buffer);
166 irqstat = esdhc_read32(®s->irqstat);
167 out_le32(®s->datport, databuf);
175 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
178 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
179 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
180 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
183 wml_value = data->blocksize/4;
185 if (data->flags & MMC_DATA_READ) {
186 if (wml_value > WML_RD_WML_MAX)
187 wml_value = WML_RD_WML_MAX_VAL;
189 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
190 esdhc_write32(®s->dsaddr, (u32)data->dest);
192 if (wml_value > WML_WR_WML_MAX)
193 wml_value = WML_WR_WML_MAX_VAL;
194 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
195 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
199 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
201 esdhc_write32(®s->dsaddr, (u32)data->src);
203 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
204 if (!(data->flags & MMC_DATA_READ)) {
205 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
206 printf("\nThe SD card is locked. "
207 "Can not write to a locked card.\n\n");
210 esdhc_write32(®s->dsaddr, (u32)data->src);
212 esdhc_write32(®s->dsaddr, (u32)data->dest);
213 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
215 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
217 /* Calculate the timeout period for data transactions */
219 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
220 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
221 * So, Number of SD Clock cycles for 0.25sec should be minimum
222 * (SD Clock/sec * 0.25 sec) SD Clock cycles
223 * = (mmc->tran_speed * 1/4) SD Clock cycles
225 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
226 * Taking log2 both the sides
227 * => timeout + 13 >= log2(mmc->tran_speed/4)
228 * Rounding up to next power of 2
229 * => timeout + 13 = log2(mmc->tran_speed/4) + 1
230 * => timeout + 13 = fls(mmc->tran_speed/4)
232 timeout = fls(mmc->tran_speed/4);
241 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
242 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
246 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
253 * Sends a command out on the bus. Takes the mmc pointer,
254 * a command pointer, and an optional data pointer.
257 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
261 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
262 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
264 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
265 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
269 esdhc_write32(®s->irqstat, -1);
273 /* Wait for the bus to be idle */
274 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
275 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
278 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
281 /* Wait at least 8 SD clock cycles before the next command */
283 * Note: This is way more than 8 cycles, but 1ms seems to
284 * resolve timing issues with some cards
288 /* Set up for a data transfer if we have one */
292 err = esdhc_setup_data(mmc, data);
297 /* Figure out the transfer arguments */
298 xfertyp = esdhc_xfertyp(cmd, data);
300 /* Send the command */
301 esdhc_write32(®s->cmdarg, cmd->cmdarg);
302 #if defined(CONFIG_FSL_USDHC)
303 esdhc_write32(®s->mixctrl,
304 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
305 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
307 esdhc_write32(®s->xfertyp, xfertyp);
309 /* Wait for the command to complete */
310 while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC))
313 irqstat = esdhc_read32(®s->irqstat);
314 esdhc_write32(®s->irqstat, irqstat);
316 if (irqstat & CMD_ERR)
319 if (irqstat & IRQSTAT_CTOE)
322 /* Copy the response to the response buffer */
323 if (cmd->resp_type & MMC_RSP_136) {
324 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
326 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
327 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
328 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
329 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
330 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
331 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
332 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
333 cmd->response[3] = (cmdrsp0 << 8);
335 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
337 /* Wait until all of the blocks are transferred */
339 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
340 esdhc_pio_read_write(mmc, data);
343 irqstat = esdhc_read32(®s->irqstat);
345 if (irqstat & IRQSTAT_DTOE)
348 if (irqstat & DATA_ERR)
350 } while (!(irqstat & IRQSTAT_TC) &&
351 (esdhc_read32(®s->prsstat) & PRSSTAT_DLA));
355 esdhc_write32(®s->irqstat, -1);
360 void set_sysctl(struct mmc *mmc, uint clock)
362 int sdhc_clk = gd->sdhc_clk;
364 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
365 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
368 if (clock < mmc->f_min)
371 if (sdhc_clk / 16 > clock) {
372 for (pre_div = 2; pre_div < 256; pre_div *= 2)
373 if ((sdhc_clk / pre_div) <= (clock * 16))
378 for (div = 1; div <= 16; div++)
379 if ((sdhc_clk / (div * pre_div)) <= clock)
385 clk = (pre_div << 8) | (div << 4);
387 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
389 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
393 clk = SYSCTL_PEREN | SYSCTL_CKEN;
395 esdhc_setbits32(®s->sysctl, clk);
398 static void esdhc_set_ios(struct mmc *mmc)
400 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
401 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
403 /* Set the clock speed */
404 set_sysctl(mmc, mmc->clock);
406 /* Set the bus width */
407 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
409 if (mmc->bus_width == 4)
410 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
411 else if (mmc->bus_width == 8)
412 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
416 static int esdhc_init(struct mmc *mmc)
418 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
419 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
424 /* Reset the entire host controller */
425 esdhc_write32(®s->sysctl, SYSCTL_RSTA);
427 /* Wait until the controller is available */
428 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
431 /* Enable cache snooping */
432 if (cfg && !cfg->no_snoop)
433 esdhc_write32(®s->scr, 0x00000040);
435 esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
437 /* Set the initial clock speed */
438 mmc_set_clock(mmc, 400000);
440 /* Disable the BRR and BWR bits in IRQSTAT */
441 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
443 /* Put the PROCTL reg back to the default */
444 esdhc_write32(®s->proctl, PROCTL_INIT);
446 /* Set timout to the maximum value */
447 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
449 /* Check if there is a callback for detecting the card */
450 if (board_mmc_getcd(&card_absent, mmc)) {
452 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) &&
466 static void esdhc_reset(struct fsl_esdhc *regs)
468 unsigned long timeout = 100; /* wait max 100 ms */
470 /* reset the controller */
471 esdhc_write32(®s->sysctl, SYSCTL_RSTA);
473 /* hardware clears the bit when it is done */
474 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
477 printf("MMC/SD: Reset never completed.\n");
480 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
482 struct fsl_esdhc *regs;
484 u32 caps, voltage_caps;
489 mmc = malloc(sizeof(struct mmc));
491 sprintf(mmc->name, "FSL_SDHC");
492 regs = (struct fsl_esdhc *)cfg->esdhc_base;
494 /* First reset the eSDHC controller */
498 mmc->send_cmd = esdhc_send_cmd;
499 mmc->set_ios = esdhc_set_ios;
500 mmc->init = esdhc_init;
503 caps = regs->hostcapblt;
505 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
506 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
507 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
509 if (caps & ESDHC_HOSTCAPBLT_VS18)
510 voltage_caps |= MMC_VDD_165_195;
511 if (caps & ESDHC_HOSTCAPBLT_VS30)
512 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
513 if (caps & ESDHC_HOSTCAPBLT_VS33)
514 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
516 #ifdef CONFIG_SYS_SD_VOLTAGE
517 mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
519 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
521 if ((mmc->voltages & voltage_caps) == 0) {
522 printf("voltage not supported by controller\n");
526 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
528 if (caps & ESDHC_HOSTCAPBLT_HSS)
529 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
532 mmc->f_max = MIN(gd->sdhc_clk, 52000000);
540 int fsl_esdhc_mmc_init(bd_t *bis)
542 struct fsl_esdhc_cfg *cfg;
544 cfg = malloc(sizeof(struct fsl_esdhc_cfg));
545 memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
546 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
547 return fsl_esdhc_initialize(bis, cfg);
550 #ifdef CONFIG_OF_LIBFDT
551 void fdt_fixup_esdhc(void *blob, bd_t *bd)
553 const char *compat = "fsl,esdhc";
555 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
556 if (!hwconfig("esdhc")) {
557 do_fixup_by_compat(blob, compat, "status", "disabled",
563 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
566 do_fixup_by_compat(blob, compat, "status", "okay",