1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
7 * Based vaguely on the pxa mmc code:
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
26 DECLARE_GLOBAL_DATA_PTR;
29 uint dsaddr; /* SDMA system address register */
30 uint blkattr; /* Block attributes register */
31 uint cmdarg; /* Command argument register */
32 uint xfertyp; /* Transfer type register */
33 uint cmdrsp0; /* Command response 0 register */
34 uint cmdrsp1; /* Command response 1 register */
35 uint cmdrsp2; /* Command response 2 register */
36 uint cmdrsp3; /* Command response 3 register */
37 uint datport; /* Buffer data port register */
38 uint prsstat; /* Present state register */
39 uint proctl; /* Protocol control register */
40 uint sysctl; /* System Control Register */
41 uint irqstat; /* Interrupt status register */
42 uint irqstaten; /* Interrupt status enable register */
43 uint irqsigen; /* Interrupt signal enable register */
44 uint autoc12err; /* Auto CMD error status register */
45 uint hostcapblt; /* Host controller capabilities register */
46 uint wml; /* Watermark level register */
47 char reserved1[8]; /* reserved */
48 uint fevt; /* Force event register */
49 uint admaes; /* ADMA error status register */
50 uint adsaddr; /* ADMA system address register */
52 uint hostver; /* Host controller version register */
53 char reserved3[4]; /* reserved */
54 uint dmaerraddr; /* DMA error address register */
55 char reserved4[4]; /* reserved */
56 uint dmaerrattr; /* DMA error attribute register */
57 char reserved5[4]; /* reserved */
58 uint hostcapblt2; /* Host controller capabilities register 2 */
59 char reserved6[756]; /* reserved */
60 uint esdhcctl; /* eSDHC control register */
63 struct fsl_esdhc_plat {
64 struct mmc_config cfg;
69 * struct fsl_esdhc_priv
71 * @esdhc_regs: registers of the sdhc controller
72 * @sdhc_clk: Current clk of the sdhc controller
73 * @bus_width: bus width, 1bit, 4bit or 8bit
76 * Following is used when Driver Model is enabled for MMC
77 * @dev: pointer for the device
78 * @cd_gpio: gpio for card detection
79 * @wp_gpio: gpio for write protection
81 struct fsl_esdhc_priv {
82 struct fsl_esdhc *esdhc_regs;
83 unsigned int sdhc_clk;
86 #if !CONFIG_IS_ENABLED(DM_MMC)
92 /* Return the XFERTYP flags for a given command and data packet */
93 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
98 xfertyp |= XFERTYP_DPSEL;
99 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
100 xfertyp |= XFERTYP_DMAEN;
102 if (data->blocks > 1) {
103 xfertyp |= XFERTYP_MSBSEL;
104 xfertyp |= XFERTYP_BCEN;
105 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
106 xfertyp |= XFERTYP_AC12EN;
110 if (data->flags & MMC_DATA_READ)
111 xfertyp |= XFERTYP_DTDSEL;
114 if (cmd->resp_type & MMC_RSP_CRC)
115 xfertyp |= XFERTYP_CCCEN;
116 if (cmd->resp_type & MMC_RSP_OPCODE)
117 xfertyp |= XFERTYP_CICEN;
118 if (cmd->resp_type & MMC_RSP_136)
119 xfertyp |= XFERTYP_RSPTYP_136;
120 else if (cmd->resp_type & MMC_RSP_BUSY)
121 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
122 else if (cmd->resp_type & MMC_RSP_PRESENT)
123 xfertyp |= XFERTYP_RSPTYP_48;
125 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
126 xfertyp |= XFERTYP_CMDTYP_ABORT;
128 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
131 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
133 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
135 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
136 struct mmc_data *data)
138 struct fsl_esdhc *regs = priv->esdhc_regs;
146 if (data->flags & MMC_DATA_READ) {
147 blocks = data->blocks;
150 start = get_timer(0);
151 size = data->blocksize;
152 irqstat = esdhc_read32(®s->irqstat);
153 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
154 if (get_timer(start) > PIO_TIMEOUT) {
155 printf("\nData Read Failed in PIO Mode.");
159 while (size && (!(irqstat & IRQSTAT_TC))) {
160 udelay(100); /* Wait before last byte transfer complete */
161 irqstat = esdhc_read32(®s->irqstat);
162 databuf = in_le32(®s->datport);
163 *((uint *)buffer) = databuf;
170 blocks = data->blocks;
171 buffer = (char *)data->src;
173 start = get_timer(0);
174 size = data->blocksize;
175 irqstat = esdhc_read32(®s->irqstat);
176 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
177 if (get_timer(start) > PIO_TIMEOUT) {
178 printf("\nData Write Failed in PIO Mode.");
182 while (size && (!(irqstat & IRQSTAT_TC))) {
183 udelay(100); /* Wait before last byte transfer complete */
184 databuf = *((uint *)buffer);
187 irqstat = esdhc_read32(®s->irqstat);
188 out_le32(®s->datport, databuf);
196 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
197 struct mmc_data *data)
200 struct fsl_esdhc *regs = priv->esdhc_regs;
201 #if defined(CONFIG_FSL_LAYERSCAPE)
206 wml_value = data->blocksize/4;
208 if (data->flags & MMC_DATA_READ) {
209 if (wml_value > WML_RD_WML_MAX)
210 wml_value = WML_RD_WML_MAX_VAL;
212 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
213 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
214 #if defined(CONFIG_FSL_LAYERSCAPE)
215 addr = virt_to_phys((void *)(data->dest));
216 if (upper_32_bits(addr))
217 printf("Error found for upper 32 bits\n");
219 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
221 esdhc_write32(®s->dsaddr, (u32)data->dest);
225 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
226 flush_dcache_range((ulong)data->src,
227 (ulong)data->src+data->blocks
230 if (wml_value > WML_WR_WML_MAX)
231 wml_value = WML_WR_WML_MAX_VAL;
233 if (!(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) {
234 printf("Can not write to locked SD card.\n");
238 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
240 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
241 #if defined(CONFIG_FSL_LAYERSCAPE)
242 addr = virt_to_phys((void *)(data->src));
243 if (upper_32_bits(addr))
244 printf("Error found for upper 32 bits\n");
246 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
248 esdhc_write32(®s->dsaddr, (u32)data->src);
253 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
255 /* Calculate the timeout period for data transactions */
257 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
258 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
259 * So, Number of SD Clock cycles for 0.25sec should be minimum
260 * (SD Clock/sec * 0.25 sec) SD Clock cycles
261 * = (mmc->clock * 1/4) SD Clock cycles
263 * => (2^(timeout+13)) >= mmc->clock * 1/4
264 * Taking log2 both the sides
265 * => timeout + 13 >= log2(mmc->clock/4)
266 * Rounding up to next power of 2
267 * => timeout + 13 = log2(mmc->clock/4) + 1
268 * => timeout + 13 = fls(mmc->clock/4)
270 * However, the MMC spec "It is strongly recommended for hosts to
271 * implement more than 500ms timeout value even if the card
272 * indicates the 250ms maximum busy length." Even the previous
273 * value of 300ms is known to be insufficient for some cards.
275 * => timeout + 13 = fls(mmc->clock/2)
277 timeout = fls(mmc->clock/2);
286 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
287 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
291 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
294 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
299 static void check_and_invalidate_dcache_range
300 (struct mmc_cmd *cmd,
301 struct mmc_data *data) {
304 unsigned size = roundup(ARCH_DMA_MINALIGN,
305 data->blocks*data->blocksize);
306 #if defined(CONFIG_FSL_LAYERSCAPE)
309 addr = virt_to_phys((void *)(data->dest));
310 if (upper_32_bits(addr))
311 printf("Error found for upper 32 bits\n");
313 start = lower_32_bits(addr);
315 start = (unsigned)data->dest;
318 invalidate_dcache_range(start, end);
322 * Sends a command out on the bus. Takes the mmc pointer,
323 * a command pointer, and an optional data pointer.
325 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
326 struct mmc_cmd *cmd, struct mmc_data *data)
331 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
332 struct fsl_esdhc *regs = priv->esdhc_regs;
335 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
336 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
340 esdhc_write32(®s->irqstat, -1);
344 /* Wait for the bus to be idle */
345 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
346 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
349 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
352 /* Wait at least 8 SD clock cycles before the next command */
354 * Note: This is way more than 8 cycles, but 1ms seems to
355 * resolve timing issues with some cards
359 /* Set up for a data transfer if we have one */
361 err = esdhc_setup_data(priv, mmc, data);
365 if (data->flags & MMC_DATA_READ)
366 check_and_invalidate_dcache_range(cmd, data);
369 /* Figure out the transfer arguments */
370 xfertyp = esdhc_xfertyp(cmd, data);
373 esdhc_write32(®s->irqsigen, 0);
375 /* Send the command */
376 esdhc_write32(®s->cmdarg, cmd->cmdarg);
377 esdhc_write32(®s->xfertyp, xfertyp);
379 /* Wait for the command to complete */
380 start = get_timer(0);
381 while (!(esdhc_read32(®s->irqstat) & flags)) {
382 if (get_timer(start) > 1000) {
388 irqstat = esdhc_read32(®s->irqstat);
390 if (irqstat & CMD_ERR) {
395 if (irqstat & IRQSTAT_CTOE) {
400 /* Workaround for ESDHC errata ENGcm03648 */
401 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
404 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
405 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
412 printf("Timeout waiting for DAT0 to go high!\n");
418 /* Copy the response to the response buffer */
419 if (cmd->resp_type & MMC_RSP_136) {
420 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
422 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
423 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
424 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
425 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
426 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
427 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
428 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
429 cmd->response[3] = (cmdrsp0 << 8);
431 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
433 /* Wait until all of the blocks are transferred */
435 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
436 esdhc_pio_read_write(priv, data);
439 irqstat = esdhc_read32(®s->irqstat);
441 if (irqstat & IRQSTAT_DTOE) {
446 if (irqstat & DATA_ERR) {
450 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
453 * Need invalidate the dcache here again to avoid any
454 * cache-fill during the DMA operations such as the
455 * speculative pre-fetching etc.
457 if (data->flags & MMC_DATA_READ) {
458 check_and_invalidate_dcache_range(cmd, data);
464 /* Reset CMD and DATA portions on error */
466 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
468 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
472 esdhc_write32(®s->sysctl,
473 esdhc_read32(®s->sysctl) |
475 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
480 esdhc_write32(®s->irqstat, -1);
485 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
487 struct fsl_esdhc *regs = priv->esdhc_regs;
490 unsigned int sdhc_clk = priv->sdhc_clk;
495 if (clock < mmc->cfg->f_min)
496 clock = mmc->cfg->f_min;
498 while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
501 while (sdhc_clk / (div * pre_div) > clock && div < 16)
507 clk = (pre_div << 8) | (div << 4);
509 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
511 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
514 value = PRSSTAT_SDSTB;
515 while (!(esdhc_read32(®s->prsstat) & value)) {
517 printf("fsl_esdhc: Internal clock never stabilised.\n");
524 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
527 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
528 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
530 struct fsl_esdhc *regs = priv->esdhc_regs;
534 value = esdhc_read32(®s->sysctl);
537 value |= SYSCTL_CKEN;
539 value &= ~SYSCTL_CKEN;
541 esdhc_write32(®s->sysctl, value);
544 value = PRSSTAT_SDSTB;
545 while (!(esdhc_read32(®s->prsstat) & value)) {
547 printf("fsl_esdhc: Internal clock never stabilised.\n");
556 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
558 struct fsl_esdhc *regs = priv->esdhc_regs;
560 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
561 /* Select to use peripheral clock */
562 esdhc_clock_control(priv, false);
563 esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
564 esdhc_clock_control(priv, true);
566 /* Set the clock speed */
567 if (priv->clock != mmc->clock)
568 set_sysctl(priv, mmc, mmc->clock);
570 /* Set the bus width */
571 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
573 if (mmc->bus_width == 4)
574 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
575 else if (mmc->bus_width == 8)
576 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
581 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
583 struct fsl_esdhc *regs = priv->esdhc_regs;
586 /* Reset the entire host controller */
587 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
589 /* Wait until the controller is available */
590 start = get_timer(0);
591 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
592 if (get_timer(start) > 1000)
596 /* Enable cache snooping */
597 esdhc_write32(®s->esdhcctl, 0x00000040);
599 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
601 /* Set the initial clock speed */
602 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
604 /* Disable the BRR and BWR bits in IRQSTAT */
605 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
607 /* Put the PROCTL reg back to the default */
608 esdhc_write32(®s->proctl, PROCTL_INIT);
610 /* Set timout to the maximum value */
611 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
616 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
618 struct fsl_esdhc *regs = priv->esdhc_regs;
621 #ifdef CONFIG_ESDHC_DETECT_QUIRK
622 if (CONFIG_ESDHC_DETECT_QUIRK)
625 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
631 static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
632 struct mmc_config *cfg)
634 struct fsl_esdhc *regs = priv->esdhc_regs;
637 caps = esdhc_read32(®s->hostcapblt);
638 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
639 caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
641 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
642 caps |= HOSTCAPBLT_VS33;
644 if (caps & HOSTCAPBLT_VS18)
645 cfg->voltages |= MMC_VDD_165_195;
646 if (caps & HOSTCAPBLT_VS30)
647 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
648 if (caps & HOSTCAPBLT_VS33)
649 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
651 cfg->name = "FSL_SDHC";
653 if (caps & HOSTCAPBLT_HSS)
654 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
657 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
658 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
661 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
662 void mmc_adapter_card_type_ident(void)
667 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
668 gd->arch.sdhc_adapter = card_id;
671 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
672 value = QIXIS_READ(brdcfg[5]);
673 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
674 QIXIS_WRITE(brdcfg[5], value);
676 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
677 value = QIXIS_READ(pwr_ctl[1]);
678 value |= QIXIS_EVDD_BY_SDHC_VS;
679 QIXIS_WRITE(pwr_ctl[1], value);
681 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
682 value = QIXIS_READ(brdcfg[5]);
683 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
684 QIXIS_WRITE(brdcfg[5], value);
686 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
688 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
690 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
692 case QIXIS_ESDHC_NO_ADAPTER:
700 #ifdef CONFIG_OF_LIBFDT
701 __weak int esdhc_status_fixup(void *blob, const char *compat)
703 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
704 if (!hwconfig("esdhc")) {
705 do_fixup_by_compat(blob, compat, "status", "disabled",
706 sizeof("disabled"), 1);
713 void fdt_fixup_esdhc(void *blob, bd_t *bd)
715 const char *compat = "fsl,esdhc";
717 if (esdhc_status_fixup(blob, compat))
720 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
721 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
722 gd->arch.sdhc_clk, 1);
724 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
725 gd->arch.sdhc_clk, 1);
727 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
728 do_fixup_by_compat_u32(blob, compat, "adapter-type",
729 (u32)(gd->arch.sdhc_adapter), 1);
734 #if !CONFIG_IS_ENABLED(DM_MMC)
735 static int esdhc_getcd(struct mmc *mmc)
737 struct fsl_esdhc_priv *priv = mmc->priv;
739 return esdhc_getcd_common(priv);
742 static int esdhc_init(struct mmc *mmc)
744 struct fsl_esdhc_priv *priv = mmc->priv;
746 return esdhc_init_common(priv, mmc);
749 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
750 struct mmc_data *data)
752 struct fsl_esdhc_priv *priv = mmc->priv;
754 return esdhc_send_cmd_common(priv, mmc, cmd, data);
757 static int esdhc_set_ios(struct mmc *mmc)
759 struct fsl_esdhc_priv *priv = mmc->priv;
761 return esdhc_set_ios_common(priv, mmc);
764 static const struct mmc_ops esdhc_ops = {
765 .getcd = esdhc_getcd,
767 .send_cmd = esdhc_send_cmd,
768 .set_ios = esdhc_set_ios,
771 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
773 struct fsl_esdhc_plat *plat;
774 struct fsl_esdhc_priv *priv;
775 struct mmc_config *mmc_cfg;
781 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
784 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
790 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
791 priv->sdhc_clk = cfg->sdhc_clk;
793 mmc_cfg = &plat->cfg;
795 if (cfg->max_bus_width == 8) {
796 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
798 } else if (cfg->max_bus_width == 4) {
799 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
800 } else if (cfg->max_bus_width == 1) {
801 mmc_cfg->host_caps |= MMC_MODE_1BIT;
803 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
805 printf("No max bus width provided. Assume 8-bit supported.\n");
808 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
809 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
810 mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
812 mmc_cfg->ops = &esdhc_ops;
814 fsl_esdhc_get_cfg_common(priv, mmc_cfg);
816 mmc = mmc_create(mmc_cfg, priv);
824 int fsl_esdhc_mmc_init(bd_t *bis)
826 struct fsl_esdhc_cfg *cfg;
828 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
829 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
830 cfg->sdhc_clk = gd->arch.sdhc_clk;
831 return fsl_esdhc_initialize(bis, cfg);
835 #include <asm/arch/clock.h>
837 static int fsl_esdhc_probe(struct udevice *dev)
839 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
840 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
841 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
846 addr = dev_read_addr(dev);
847 if (addr == FDT_ADDR_T_NONE)
850 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
852 priv->esdhc_regs = (struct fsl_esdhc *)addr;
856 if (IS_ENABLED(CONFIG_CLK)) {
857 /* Assigned clock already set clock */
858 ret = clk_get_by_name(dev, "per", &priv->per_clk);
860 printf("Failed to get per_clk\n");
863 ret = clk_enable(&priv->per_clk);
865 printf("Failed to enable per_clk\n");
869 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
872 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
874 priv->sdhc_clk = gd->arch.sdhc_clk;
876 if (priv->sdhc_clk <= 0) {
877 dev_err(dev, "Unable to get clk for %s\n", dev->name);
882 fsl_esdhc_get_cfg_common(priv, &plat->cfg);
884 mmc_of_parse(dev, &plat->cfg);
887 mmc->cfg = &plat->cfg;
892 return esdhc_init_common(priv, mmc);
895 static int fsl_esdhc_get_cd(struct udevice *dev)
897 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
898 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
900 if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
903 return esdhc_getcd_common(priv);
906 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
907 struct mmc_data *data)
909 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
910 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
912 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
915 static int fsl_esdhc_set_ios(struct udevice *dev)
917 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
918 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
920 return esdhc_set_ios_common(priv, &plat->mmc);
923 static const struct dm_mmc_ops fsl_esdhc_ops = {
924 .get_cd = fsl_esdhc_get_cd,
925 .send_cmd = fsl_esdhc_send_cmd,
926 .set_ios = fsl_esdhc_set_ios,
927 #ifdef MMC_SUPPORTS_TUNING
928 .execute_tuning = fsl_esdhc_execute_tuning,
932 static const struct udevice_id fsl_esdhc_ids[] = {
933 { .compatible = "fsl,esdhc", },
937 static int fsl_esdhc_bind(struct udevice *dev)
939 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
941 return mmc_bind(dev, &plat->mmc, &plat->cfg);
944 U_BOOT_DRIVER(fsl_esdhc) = {
945 .name = "fsl-esdhc-mmc",
947 .of_match = fsl_esdhc_ids,
948 .ops = &fsl_esdhc_ops,
949 .bind = fsl_esdhc_bind,
950 .probe = fsl_esdhc_probe,
951 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
952 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),