2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
19 #include <power/regulator.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
25 #include <asm-generic/gpio.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
31 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
32 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
33 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
37 uint dsaddr; /* SDMA system address register */
38 uint blkattr; /* Block attributes register */
39 uint cmdarg; /* Command argument register */
40 uint xfertyp; /* Transfer type register */
41 uint cmdrsp0; /* Command response 0 register */
42 uint cmdrsp1; /* Command response 1 register */
43 uint cmdrsp2; /* Command response 2 register */
44 uint cmdrsp3; /* Command response 3 register */
45 uint datport; /* Buffer data port register */
46 uint prsstat; /* Present state register */
47 uint proctl; /* Protocol control register */
48 uint sysctl; /* System Control Register */
49 uint irqstat; /* Interrupt status register */
50 uint irqstaten; /* Interrupt status enable register */
51 uint irqsigen; /* Interrupt signal enable register */
52 uint autoc12err; /* Auto CMD error status register */
53 uint hostcapblt; /* Host controller capabilities register */
54 uint wml; /* Watermark level register */
55 uint mixctrl; /* For USDHC */
56 char reserved1[4]; /* reserved */
57 uint fevt; /* Force event register */
58 uint admaes; /* ADMA error status register */
59 uint adsaddr; /* ADMA system address register */
63 uint clktunectrlstatus;
69 uint hostver; /* Host controller version register */
70 char reserved5[4]; /* reserved */
71 uint dmaerraddr; /* DMA error address register */
72 char reserved6[4]; /* reserved */
73 uint dmaerrattr; /* DMA error attribute register */
74 char reserved7[4]; /* reserved */
75 uint hostcapblt2; /* Host controller capabilities register 2 */
76 char reserved8[8]; /* reserved */
77 uint tcr; /* Tuning control register */
78 char reserved9[28]; /* reserved */
79 uint sddirctl; /* SD direction control register */
80 char reserved10[712];/* reserved */
81 uint scr; /* eSDHC control register */
84 struct fsl_esdhc_plat {
85 struct mmc_config cfg;
90 * struct fsl_esdhc_priv
92 * @esdhc_regs: registers of the sdhc controller
93 * @sdhc_clk: Current clk of the sdhc controller
94 * @bus_width: bus width, 1bit, 4bit or 8bit
97 * Following is used when Driver Model is enabled for MMC
98 * @dev: pointer for the device
99 * @non_removable: 0: removable; 1: non-removable
100 * @wp_enable: 1: enable checking wp; 0: no check
101 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
102 * @cd_gpio: gpio for card detection
103 * @wp_gpio: gpio for write protection
105 struct fsl_esdhc_priv {
106 struct fsl_esdhc *esdhc_regs;
107 unsigned int sdhc_clk;
108 unsigned int bus_width;
109 #if !CONFIG_IS_ENABLED(BLK)
116 #ifdef CONFIG_DM_GPIO
117 struct gpio_desc cd_gpio;
118 struct gpio_desc wp_gpio;
122 /* Return the XFERTYP flags for a given command and data packet */
123 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
128 xfertyp |= XFERTYP_DPSEL;
129 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
130 xfertyp |= XFERTYP_DMAEN;
132 if (data->blocks > 1) {
133 xfertyp |= XFERTYP_MSBSEL;
134 xfertyp |= XFERTYP_BCEN;
135 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
136 xfertyp |= XFERTYP_AC12EN;
140 if (data->flags & MMC_DATA_READ)
141 xfertyp |= XFERTYP_DTDSEL;
144 if (cmd->resp_type & MMC_RSP_CRC)
145 xfertyp |= XFERTYP_CCCEN;
146 if (cmd->resp_type & MMC_RSP_OPCODE)
147 xfertyp |= XFERTYP_CICEN;
148 if (cmd->resp_type & MMC_RSP_136)
149 xfertyp |= XFERTYP_RSPTYP_136;
150 else if (cmd->resp_type & MMC_RSP_BUSY)
151 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
152 else if (cmd->resp_type & MMC_RSP_PRESENT)
153 xfertyp |= XFERTYP_RSPTYP_48;
155 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
156 xfertyp |= XFERTYP_CMDTYP_ABORT;
158 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
161 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
163 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
165 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
166 struct mmc_data *data)
168 struct fsl_esdhc *regs = priv->esdhc_regs;
176 if (data->flags & MMC_DATA_READ) {
177 blocks = data->blocks;
180 start = get_timer(0);
181 size = data->blocksize;
182 irqstat = esdhc_read32(®s->irqstat);
183 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
184 if (get_timer(start) > PIO_TIMEOUT) {
185 printf("\nData Read Failed in PIO Mode.");
189 while (size && (!(irqstat & IRQSTAT_TC))) {
190 udelay(100); /* Wait before last byte transfer complete */
191 irqstat = esdhc_read32(®s->irqstat);
192 databuf = in_le32(®s->datport);
193 *((uint *)buffer) = databuf;
200 blocks = data->blocks;
201 buffer = (char *)data->src;
203 start = get_timer(0);
204 size = data->blocksize;
205 irqstat = esdhc_read32(®s->irqstat);
206 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
207 if (get_timer(start) > PIO_TIMEOUT) {
208 printf("\nData Write Failed in PIO Mode.");
212 while (size && (!(irqstat & IRQSTAT_TC))) {
213 udelay(100); /* Wait before last byte transfer complete */
214 databuf = *((uint *)buffer);
217 irqstat = esdhc_read32(®s->irqstat);
218 out_le32(®s->datport, databuf);
226 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
227 struct mmc_data *data)
230 struct fsl_esdhc *regs = priv->esdhc_regs;
231 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
236 wml_value = data->blocksize/4;
238 if (data->flags & MMC_DATA_READ) {
239 if (wml_value > WML_RD_WML_MAX)
240 wml_value = WML_RD_WML_MAX_VAL;
242 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
243 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
244 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
245 addr = virt_to_phys((void *)(data->dest));
246 if (upper_32_bits(addr))
247 printf("Error found for upper 32 bits\n");
249 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
251 esdhc_write32(®s->dsaddr, (u32)data->dest);
255 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
256 flush_dcache_range((ulong)data->src,
257 (ulong)data->src+data->blocks
260 if (wml_value > WML_WR_WML_MAX)
261 wml_value = WML_WR_WML_MAX_VAL;
262 if (priv->wp_enable) {
263 if ((esdhc_read32(®s->prsstat) &
264 PRSSTAT_WPSPL) == 0) {
265 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
270 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
272 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
273 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
274 addr = virt_to_phys((void *)(data->src));
275 if (upper_32_bits(addr))
276 printf("Error found for upper 32 bits\n");
278 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
280 esdhc_write32(®s->dsaddr, (u32)data->src);
285 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
287 /* Calculate the timeout period for data transactions */
289 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
290 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
291 * So, Number of SD Clock cycles for 0.25sec should be minimum
292 * (SD Clock/sec * 0.25 sec) SD Clock cycles
293 * = (mmc->clock * 1/4) SD Clock cycles
295 * => (2^(timeout+13)) >= mmc->clock * 1/4
296 * Taking log2 both the sides
297 * => timeout + 13 >= log2(mmc->clock/4)
298 * Rounding up to next power of 2
299 * => timeout + 13 = log2(mmc->clock/4) + 1
300 * => timeout + 13 = fls(mmc->clock/4)
302 * However, the MMC spec "It is strongly recommended for hosts to
303 * implement more than 500ms timeout value even if the card
304 * indicates the 250ms maximum busy length." Even the previous
305 * value of 300ms is known to be insufficient for some cards.
307 * => timeout + 13 = fls(mmc->clock/2)
309 timeout = fls(mmc->clock/2);
318 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
319 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
323 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
326 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
331 static void check_and_invalidate_dcache_range
332 (struct mmc_cmd *cmd,
333 struct mmc_data *data) {
336 unsigned size = roundup(ARCH_DMA_MINALIGN,
337 data->blocks*data->blocksize);
338 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
341 addr = virt_to_phys((void *)(data->dest));
342 if (upper_32_bits(addr))
343 printf("Error found for upper 32 bits\n");
345 start = lower_32_bits(addr);
347 start = (unsigned)data->dest;
350 invalidate_dcache_range(start, end);
354 * Sends a command out on the bus. Takes the mmc pointer,
355 * a command pointer, and an optional data pointer.
357 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
358 struct mmc_cmd *cmd, struct mmc_data *data)
363 struct fsl_esdhc *regs = priv->esdhc_regs;
365 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
366 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
370 esdhc_write32(®s->irqstat, -1);
374 /* Wait for the bus to be idle */
375 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
376 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
379 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
382 /* Wait at least 8 SD clock cycles before the next command */
384 * Note: This is way more than 8 cycles, but 1ms seems to
385 * resolve timing issues with some cards
389 /* Set up for a data transfer if we have one */
391 err = esdhc_setup_data(priv, mmc, data);
395 if (data->flags & MMC_DATA_READ)
396 check_and_invalidate_dcache_range(cmd, data);
399 /* Figure out the transfer arguments */
400 xfertyp = esdhc_xfertyp(cmd, data);
403 esdhc_write32(®s->irqsigen, 0);
405 /* Send the command */
406 esdhc_write32(®s->cmdarg, cmd->cmdarg);
407 #if defined(CONFIG_FSL_USDHC)
408 esdhc_write32(®s->mixctrl,
409 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
410 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
411 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
413 esdhc_write32(®s->xfertyp, xfertyp);
416 /* Wait for the command to complete */
417 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
420 irqstat = esdhc_read32(®s->irqstat);
422 if (irqstat & CMD_ERR) {
427 if (irqstat & IRQSTAT_CTOE) {
432 /* Switch voltage to 1.8V if CMD11 succeeded */
433 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
434 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
436 printf("Run CMD11 1.8V switch\n");
437 /* Sleep for 5 ms - max time for card to switch to 1.8V */
441 /* Workaround for ESDHC errata ENGcm03648 */
442 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
445 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
446 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
453 printf("Timeout waiting for DAT0 to go high!\n");
459 /* Copy the response to the response buffer */
460 if (cmd->resp_type & MMC_RSP_136) {
461 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
463 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
464 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
465 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
466 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
467 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
468 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
469 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
470 cmd->response[3] = (cmdrsp0 << 8);
472 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
474 /* Wait until all of the blocks are transferred */
476 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
477 esdhc_pio_read_write(priv, data);
480 irqstat = esdhc_read32(®s->irqstat);
482 if (irqstat & IRQSTAT_DTOE) {
487 if (irqstat & DATA_ERR) {
491 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
494 * Need invalidate the dcache here again to avoid any
495 * cache-fill during the DMA operations such as the
496 * speculative pre-fetching etc.
498 if (data->flags & MMC_DATA_READ)
499 check_and_invalidate_dcache_range(cmd, data);
504 /* Reset CMD and DATA portions on error */
506 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
508 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
512 esdhc_write32(®s->sysctl,
513 esdhc_read32(®s->sysctl) |
515 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
519 /* If this was CMD11, then notify that power cycle is needed */
520 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
521 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
524 esdhc_write32(®s->irqstat, -1);
529 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
531 struct fsl_esdhc *regs = priv->esdhc_regs;
535 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
536 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
543 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
544 int sdhc_clk = priv->sdhc_clk;
547 if (clock < mmc->cfg->f_min)
548 clock = mmc->cfg->f_min;
550 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
553 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
559 clk = (pre_div << 8) | (div << 4);
561 #ifdef CONFIG_FSL_USDHC
562 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
564 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
567 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
571 #ifdef CONFIG_FSL_USDHC
572 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
574 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
579 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
580 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
582 struct fsl_esdhc *regs = priv->esdhc_regs;
586 value = esdhc_read32(®s->sysctl);
589 value |= SYSCTL_CKEN;
591 value &= ~SYSCTL_CKEN;
593 esdhc_write32(®s->sysctl, value);
596 value = PRSSTAT_SDSTB;
597 while (!(esdhc_read32(®s->prsstat) & value)) {
599 printf("fsl_esdhc: Internal clock never stabilised.\n");
608 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
610 struct fsl_esdhc *regs = priv->esdhc_regs;
612 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
613 /* Select to use peripheral clock */
614 esdhc_clock_control(priv, false);
615 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
616 esdhc_clock_control(priv, true);
618 /* Set the clock speed */
619 set_sysctl(priv, mmc, mmc->clock);
621 /* Set the bus width */
622 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
624 if (mmc->bus_width == 4)
625 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
626 else if (mmc->bus_width == 8)
627 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
632 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
634 struct fsl_esdhc *regs = priv->esdhc_regs;
637 /* Reset the entire host controller */
638 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
640 /* Wait until the controller is available */
641 start = get_timer(0);
642 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
643 if (get_timer(start) > 1000)
647 #if defined(CONFIG_FSL_USDHC)
648 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
649 esdhc_write32(®s->mmcboot, 0x0);
650 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
651 esdhc_write32(®s->mixctrl, 0x0);
652 esdhc_write32(®s->clktunectrlstatus, 0x0);
654 /* Put VEND_SPEC to default value */
655 if (priv->vs18_enable)
656 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
657 ESDHC_VENDORSPEC_VSELECT));
659 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
661 /* Disable DLL_CTRL delay line */
662 esdhc_write32(®s->dllctrl, 0x0);
666 /* Enable cache snooping */
667 esdhc_write32(®s->scr, 0x00000040);
670 #ifndef CONFIG_FSL_USDHC
671 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
673 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
676 /* Set the initial clock speed */
677 mmc_set_clock(mmc, 400000, false);
679 /* Disable the BRR and BWR bits in IRQSTAT */
680 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
682 /* Put the PROCTL reg back to the default */
683 esdhc_write32(®s->proctl, PROCTL_INIT);
685 /* Set timout to the maximum value */
686 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
691 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
693 struct fsl_esdhc *regs = priv->esdhc_regs;
696 #ifdef CONFIG_ESDHC_DETECT_QUIRK
697 if (CONFIG_ESDHC_DETECT_QUIRK)
701 #if CONFIG_IS_ENABLED(DM_MMC)
702 if (priv->non_removable)
704 #ifdef CONFIG_DM_GPIO
705 if (dm_gpio_is_valid(&priv->cd_gpio))
706 return dm_gpio_get_value(&priv->cd_gpio);
710 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
716 static int esdhc_reset(struct fsl_esdhc *regs)
720 /* reset the controller */
721 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
723 /* hardware clears the bit when it is done */
724 start = get_timer(0);
725 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
726 if (get_timer(start) > 100) {
727 printf("MMC/SD: Reset never completed.\n");
735 #if !CONFIG_IS_ENABLED(DM_MMC)
736 static int esdhc_getcd(struct mmc *mmc)
738 struct fsl_esdhc_priv *priv = mmc->priv;
740 return esdhc_getcd_common(priv);
743 static int esdhc_init(struct mmc *mmc)
745 struct fsl_esdhc_priv *priv = mmc->priv;
747 return esdhc_init_common(priv, mmc);
750 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
751 struct mmc_data *data)
753 struct fsl_esdhc_priv *priv = mmc->priv;
755 return esdhc_send_cmd_common(priv, mmc, cmd, data);
758 static int esdhc_set_ios(struct mmc *mmc)
760 struct fsl_esdhc_priv *priv = mmc->priv;
762 return esdhc_set_ios_common(priv, mmc);
765 static const struct mmc_ops esdhc_ops = {
766 .getcd = esdhc_getcd,
768 .send_cmd = esdhc_send_cmd,
769 .set_ios = esdhc_set_ios,
773 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
774 struct fsl_esdhc_plat *plat)
776 struct mmc_config *cfg;
777 struct fsl_esdhc *regs;
778 u32 caps, voltage_caps;
784 regs = priv->esdhc_regs;
786 /* First reset the eSDHC controller */
787 ret = esdhc_reset(regs);
791 #ifndef CONFIG_FSL_USDHC
792 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
793 | SYSCTL_IPGEN | SYSCTL_CKEN);
795 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
796 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
799 if (priv->vs18_enable)
800 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
802 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
804 #ifndef CONFIG_DM_MMC
805 memset(cfg, '\0', sizeof(*cfg));
809 caps = esdhc_read32(®s->hostcapblt);
811 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
812 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
813 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
816 /* T4240 host controller capabilities register should have VS33 bit */
817 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
818 caps = caps | ESDHC_HOSTCAPBLT_VS33;
821 if (caps & ESDHC_HOSTCAPBLT_VS18)
822 voltage_caps |= MMC_VDD_165_195;
823 if (caps & ESDHC_HOSTCAPBLT_VS30)
824 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
825 if (caps & ESDHC_HOSTCAPBLT_VS33)
826 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
828 cfg->name = "FSL_SDHC";
829 #if !CONFIG_IS_ENABLED(DM_MMC)
830 cfg->ops = &esdhc_ops;
832 #ifdef CONFIG_SYS_SD_VOLTAGE
833 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
835 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
837 if ((cfg->voltages & voltage_caps) == 0) {
838 printf("voltage not supported by controller\n");
842 if (priv->bus_width == 8)
843 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
844 else if (priv->bus_width == 4)
845 cfg->host_caps = MMC_MODE_4BIT;
847 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
848 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
849 cfg->host_caps |= MMC_MODE_DDR_52MHz;
852 if (priv->bus_width > 0) {
853 if (priv->bus_width < 8)
854 cfg->host_caps &= ~MMC_MODE_8BIT;
855 if (priv->bus_width < 4)
856 cfg->host_caps &= ~MMC_MODE_4BIT;
859 if (caps & ESDHC_HOSTCAPBLT_HSS)
860 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
862 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
863 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
864 cfg->host_caps &= ~MMC_MODE_8BIT;
868 cfg->f_max = min(priv->sdhc_clk, (u32)52000000);
870 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
875 #if !CONFIG_IS_ENABLED(DM_MMC)
876 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
877 struct fsl_esdhc_priv *priv)
882 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
883 priv->bus_width = cfg->max_bus_width;
884 priv->sdhc_clk = cfg->sdhc_clk;
885 priv->wp_enable = cfg->wp_enable;
886 priv->vs18_enable = cfg->vs18_enable;
891 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
893 struct fsl_esdhc_plat *plat;
894 struct fsl_esdhc_priv *priv;
901 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
904 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
910 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
912 debug("%s xlate failure\n", __func__);
918 ret = fsl_esdhc_init(priv, plat);
920 debug("%s init failure\n", __func__);
926 mmc = mmc_create(&plat->cfg, priv);
935 int fsl_esdhc_mmc_init(bd_t *bis)
937 struct fsl_esdhc_cfg *cfg;
939 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
940 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
941 cfg->sdhc_clk = gd->arch.sdhc_clk;
942 return fsl_esdhc_initialize(bis, cfg);
946 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
947 void mmc_adapter_card_type_ident(void)
952 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
953 gd->arch.sdhc_adapter = card_id;
956 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
957 value = QIXIS_READ(brdcfg[5]);
958 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
959 QIXIS_WRITE(brdcfg[5], value);
961 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
962 value = QIXIS_READ(pwr_ctl[1]);
963 value |= QIXIS_EVDD_BY_SDHC_VS;
964 QIXIS_WRITE(pwr_ctl[1], value);
966 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
967 value = QIXIS_READ(brdcfg[5]);
968 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
969 QIXIS_WRITE(brdcfg[5], value);
971 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
973 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
975 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
977 case QIXIS_ESDHC_NO_ADAPTER:
985 #ifdef CONFIG_OF_LIBFDT
986 __weak int esdhc_status_fixup(void *blob, const char *compat)
988 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
989 if (!hwconfig("esdhc")) {
990 do_fixup_by_compat(blob, compat, "status", "disabled",
991 sizeof("disabled"), 1);
998 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1000 const char *compat = "fsl,esdhc";
1002 if (esdhc_status_fixup(blob, compat))
1005 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1006 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1007 gd->arch.sdhc_clk, 1);
1009 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1010 gd->arch.sdhc_clk, 1);
1012 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1013 do_fixup_by_compat_u32(blob, compat, "adapter-type",
1014 (u32)(gd->arch.sdhc_adapter), 1);
1019 #if CONFIG_IS_ENABLED(DM_MMC)
1020 #include <asm/arch/clock.h>
1021 __weak void init_clk_usdhc(u32 index)
1025 static int fsl_esdhc_probe(struct udevice *dev)
1027 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1028 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1029 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1030 #ifdef CONFIG_DM_REGULATOR
1031 struct udevice *vqmmc_dev;
1038 addr = dev_read_addr(dev);
1039 if (addr == FDT_ADDR_T_NONE)
1042 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1045 val = dev_read_u32_default(dev, "bus-width", -1);
1047 priv->bus_width = 8;
1049 priv->bus_width = 4;
1051 priv->bus_width = 1;
1053 if (dev_read_bool(dev, "non-removable")) {
1054 priv->non_removable = 1;
1056 priv->non_removable = 0;
1057 #ifdef CONFIG_DM_GPIO
1058 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1063 priv->wp_enable = 1;
1065 #ifdef CONFIG_DM_GPIO
1066 ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1069 priv->wp_enable = 0;
1072 priv->vs18_enable = 0;
1074 #ifdef CONFIG_DM_REGULATOR
1076 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1077 * otherwise, emmc will work abnormally.
1079 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1081 dev_dbg(dev, "no vqmmc-supply\n");
1083 ret = regulator_set_enable(vqmmc_dev, true);
1085 dev_err(dev, "fail to enable vqmmc-supply\n");
1089 if (regulator_get_value(vqmmc_dev) == 1800000)
1090 priv->vs18_enable = 1;
1096 * Because lack of clk driver, if SDHC clk is not enabled,
1097 * need to enable it first before this driver is invoked.
1099 * we use MXC_ESDHC_CLK to get clk freq.
1100 * If one would like to make this function work,
1101 * the aliases should be provided in dts as this:
1109 * Then if your board only supports mmc2 and mmc3, but we can
1110 * correctly get the seq as 2 and 3, then let mxc_get_clock
1114 init_clk_usdhc(dev->seq);
1116 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1117 if (priv->sdhc_clk <= 0) {
1118 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1122 ret = fsl_esdhc_init(priv, plat);
1124 dev_err(dev, "fsl_esdhc_init failure\n");
1129 mmc->cfg = &plat->cfg;
1133 return esdhc_init_common(priv, mmc);
1136 #if CONFIG_IS_ENABLED(DM_MMC)
1137 static int fsl_esdhc_get_cd(struct udevice *dev)
1139 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1142 return esdhc_getcd_common(priv);
1145 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1146 struct mmc_data *data)
1148 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1149 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1151 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1154 static int fsl_esdhc_set_ios(struct udevice *dev)
1156 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1157 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1159 return esdhc_set_ios_common(priv, &plat->mmc);
1162 static const struct dm_mmc_ops fsl_esdhc_ops = {
1163 .get_cd = fsl_esdhc_get_cd,
1164 .send_cmd = fsl_esdhc_send_cmd,
1165 .set_ios = fsl_esdhc_set_ios,
1169 static const struct udevice_id fsl_esdhc_ids[] = {
1170 { .compatible = "fsl,imx6ul-usdhc", },
1171 { .compatible = "fsl,imx6sx-usdhc", },
1172 { .compatible = "fsl,imx6sl-usdhc", },
1173 { .compatible = "fsl,imx6q-usdhc", },
1174 { .compatible = "fsl,imx7d-usdhc", },
1175 { .compatible = "fsl,imx7ulp-usdhc", },
1176 { .compatible = "fsl,esdhc", },
1180 #if CONFIG_IS_ENABLED(BLK)
1181 static int fsl_esdhc_bind(struct udevice *dev)
1183 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1185 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1189 U_BOOT_DRIVER(fsl_esdhc) = {
1190 .name = "fsl-esdhc-mmc",
1192 .of_match = fsl_esdhc_ids,
1193 .ops = &fsl_esdhc_ops,
1194 #if CONFIG_IS_ENABLED(BLK)
1195 .bind = fsl_esdhc_bind,
1197 .probe = fsl_esdhc_probe,
1198 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1199 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),