2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
19 #include <fsl_esdhc.h>
20 #include <fdt_support.h>
23 #include <asm-generic/gpio.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
29 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
30 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
31 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
35 uint dsaddr; /* SDMA system address register */
36 uint blkattr; /* Block attributes register */
37 uint cmdarg; /* Command argument register */
38 uint xfertyp; /* Transfer type register */
39 uint cmdrsp0; /* Command response 0 register */
40 uint cmdrsp1; /* Command response 1 register */
41 uint cmdrsp2; /* Command response 2 register */
42 uint cmdrsp3; /* Command response 3 register */
43 uint datport; /* Buffer data port register */
44 uint prsstat; /* Present state register */
45 uint proctl; /* Protocol control register */
46 uint sysctl; /* System Control Register */
47 uint irqstat; /* Interrupt status register */
48 uint irqstaten; /* Interrupt status enable register */
49 uint irqsigen; /* Interrupt signal enable register */
50 uint autoc12err; /* Auto CMD error status register */
51 uint hostcapblt; /* Host controller capabilities register */
52 uint wml; /* Watermark level register */
53 uint mixctrl; /* For USDHC */
54 char reserved1[4]; /* reserved */
55 uint fevt; /* Force event register */
56 uint admaes; /* ADMA error status register */
57 uint adsaddr; /* ADMA system address register */
61 uint clktunectrlstatus;
67 uint hostver; /* Host controller version register */
68 char reserved5[4]; /* reserved */
69 uint dmaerraddr; /* DMA error address register */
70 char reserved6[4]; /* reserved */
71 uint dmaerrattr; /* DMA error attribute register */
72 char reserved7[4]; /* reserved */
73 uint hostcapblt2; /* Host controller capabilities register 2 */
74 char reserved8[8]; /* reserved */
75 uint tcr; /* Tuning control register */
76 char reserved9[28]; /* reserved */
77 uint sddirctl; /* SD direction control register */
78 char reserved10[712];/* reserved */
79 uint scr; /* eSDHC control register */
83 * struct fsl_esdhc_priv
85 * @esdhc_regs: registers of the sdhc controller
86 * @sdhc_clk: Current clk of the sdhc controller
87 * @bus_width: bus width, 1bit, 4bit or 8bit
90 * Following is used when Driver Model is enabled for MMC
91 * @dev: pointer for the device
92 * @non_removable: 0: removable; 1: non-removable
93 * @wp_enable: 1: enable checking wp; 0: no check
94 * @cd_gpio: gpio for card detection
95 * @wp_gpio: gpio for write protection
97 struct fsl_esdhc_priv {
98 struct fsl_esdhc *esdhc_regs;
99 unsigned int sdhc_clk;
100 unsigned int bus_width;
101 struct mmc_config cfg;
106 struct gpio_desc cd_gpio;
107 struct gpio_desc wp_gpio;
110 /* Return the XFERTYP flags for a given command and data packet */
111 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
116 xfertyp |= XFERTYP_DPSEL;
117 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
118 xfertyp |= XFERTYP_DMAEN;
120 if (data->blocks > 1) {
121 xfertyp |= XFERTYP_MSBSEL;
122 xfertyp |= XFERTYP_BCEN;
123 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
124 xfertyp |= XFERTYP_AC12EN;
128 if (data->flags & MMC_DATA_READ)
129 xfertyp |= XFERTYP_DTDSEL;
132 if (cmd->resp_type & MMC_RSP_CRC)
133 xfertyp |= XFERTYP_CCCEN;
134 if (cmd->resp_type & MMC_RSP_OPCODE)
135 xfertyp |= XFERTYP_CICEN;
136 if (cmd->resp_type & MMC_RSP_136)
137 xfertyp |= XFERTYP_RSPTYP_136;
138 else if (cmd->resp_type & MMC_RSP_BUSY)
139 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
140 else if (cmd->resp_type & MMC_RSP_PRESENT)
141 xfertyp |= XFERTYP_RSPTYP_48;
143 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
144 xfertyp |= XFERTYP_CMDTYP_ABORT;
146 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
149 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
151 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
154 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
156 struct fsl_esdhc_priv *priv = mmc->priv;
157 struct fsl_esdhc *regs = priv->esdhc_regs;
165 if (data->flags & MMC_DATA_READ) {
166 blocks = data->blocks;
169 timeout = PIO_TIMEOUT;
170 size = data->blocksize;
171 irqstat = esdhc_read32(®s->irqstat);
172 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
175 printf("\nData Read Failed in PIO Mode.");
178 while (size && (!(irqstat & IRQSTAT_TC))) {
179 udelay(100); /* Wait before last byte transfer complete */
180 irqstat = esdhc_read32(®s->irqstat);
181 databuf = in_le32(®s->datport);
182 *((uint *)buffer) = databuf;
189 blocks = data->blocks;
190 buffer = (char *)data->src;
192 timeout = PIO_TIMEOUT;
193 size = data->blocksize;
194 irqstat = esdhc_read32(®s->irqstat);
195 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
198 printf("\nData Write Failed in PIO Mode.");
201 while (size && (!(irqstat & IRQSTAT_TC))) {
202 udelay(100); /* Wait before last byte transfer complete */
203 databuf = *((uint *)buffer);
206 irqstat = esdhc_read32(®s->irqstat);
207 out_le32(®s->datport, databuf);
215 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
218 struct fsl_esdhc_priv *priv = mmc->priv;
219 struct fsl_esdhc *regs = priv->esdhc_regs;
220 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
225 wml_value = data->blocksize/4;
227 if (data->flags & MMC_DATA_READ) {
228 if (wml_value > WML_RD_WML_MAX)
229 wml_value = WML_RD_WML_MAX_VAL;
231 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
232 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
233 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
234 addr = virt_to_phys((void *)(data->dest));
235 if (upper_32_bits(addr))
236 printf("Error found for upper 32 bits\n");
238 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
240 esdhc_write32(®s->dsaddr, (u32)data->dest);
244 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
245 flush_dcache_range((ulong)data->src,
246 (ulong)data->src+data->blocks
249 if (wml_value > WML_WR_WML_MAX)
250 wml_value = WML_WR_WML_MAX_VAL;
251 if (priv->wp_enable) {
252 if ((esdhc_read32(®s->prsstat) &
253 PRSSTAT_WPSPL) == 0) {
254 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
259 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
261 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
262 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
263 addr = virt_to_phys((void *)(data->src));
264 if (upper_32_bits(addr))
265 printf("Error found for upper 32 bits\n");
267 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
269 esdhc_write32(®s->dsaddr, (u32)data->src);
274 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
276 /* Calculate the timeout period for data transactions */
278 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
279 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
280 * So, Number of SD Clock cycles for 0.25sec should be minimum
281 * (SD Clock/sec * 0.25 sec) SD Clock cycles
282 * = (mmc->clock * 1/4) SD Clock cycles
284 * => (2^(timeout+13)) >= mmc->clock * 1/4
285 * Taking log2 both the sides
286 * => timeout + 13 >= log2(mmc->clock/4)
287 * Rounding up to next power of 2
288 * => timeout + 13 = log2(mmc->clock/4) + 1
289 * => timeout + 13 = fls(mmc->clock/4)
291 * However, the MMC spec "It is strongly recommended for hosts to
292 * implement more than 500ms timeout value even if the card
293 * indicates the 250ms maximum busy length." Even the previous
294 * value of 300ms is known to be insufficient for some cards.
296 * => timeout + 13 = fls(mmc->clock/2)
298 timeout = fls(mmc->clock/2);
307 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
308 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
312 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
315 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
320 static void check_and_invalidate_dcache_range
321 (struct mmc_cmd *cmd,
322 struct mmc_data *data) {
325 unsigned size = roundup(ARCH_DMA_MINALIGN,
326 data->blocks*data->blocksize);
327 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
330 addr = virt_to_phys((void *)(data->dest));
331 if (upper_32_bits(addr))
332 printf("Error found for upper 32 bits\n");
334 start = lower_32_bits(addr);
336 start = (unsigned)data->dest;
339 invalidate_dcache_range(start, end);
343 * Sends a command out on the bus. Takes the mmc pointer,
344 * a command pointer, and an optional data pointer.
347 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
352 struct fsl_esdhc_priv *priv = mmc->priv;
353 struct fsl_esdhc *regs = priv->esdhc_regs;
355 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
356 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
360 esdhc_write32(®s->irqstat, -1);
364 /* Wait for the bus to be idle */
365 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
366 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
369 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
372 /* Wait at least 8 SD clock cycles before the next command */
374 * Note: This is way more than 8 cycles, but 1ms seems to
375 * resolve timing issues with some cards
379 /* Set up for a data transfer if we have one */
381 err = esdhc_setup_data(mmc, data);
385 if (data->flags & MMC_DATA_READ)
386 check_and_invalidate_dcache_range(cmd, data);
389 /* Figure out the transfer arguments */
390 xfertyp = esdhc_xfertyp(cmd, data);
393 esdhc_write32(®s->irqsigen, 0);
395 /* Send the command */
396 esdhc_write32(®s->cmdarg, cmd->cmdarg);
397 #if defined(CONFIG_FSL_USDHC)
398 esdhc_write32(®s->mixctrl,
399 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
400 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
401 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
403 esdhc_write32(®s->xfertyp, xfertyp);
406 /* Wait for the command to complete */
407 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
410 irqstat = esdhc_read32(®s->irqstat);
412 if (irqstat & CMD_ERR) {
417 if (irqstat & IRQSTAT_CTOE) {
422 /* Switch voltage to 1.8V if CMD11 succeeded */
423 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
424 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
426 printf("Run CMD11 1.8V switch\n");
427 /* Sleep for 5 ms - max time for card to switch to 1.8V */
431 /* Workaround for ESDHC errata ENGcm03648 */
432 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
435 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
436 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
443 printf("Timeout waiting for DAT0 to go high!\n");
449 /* Copy the response to the response buffer */
450 if (cmd->resp_type & MMC_RSP_136) {
451 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
453 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
454 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
455 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
456 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
457 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
458 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
459 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
460 cmd->response[3] = (cmdrsp0 << 8);
462 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
464 /* Wait until all of the blocks are transferred */
466 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
467 esdhc_pio_read_write(mmc, data);
470 irqstat = esdhc_read32(®s->irqstat);
472 if (irqstat & IRQSTAT_DTOE) {
477 if (irqstat & DATA_ERR) {
481 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
484 * Need invalidate the dcache here again to avoid any
485 * cache-fill during the DMA operations such as the
486 * speculative pre-fetching etc.
488 if (data->flags & MMC_DATA_READ)
489 check_and_invalidate_dcache_range(cmd, data);
494 /* Reset CMD and DATA portions on error */
496 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
498 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
502 esdhc_write32(®s->sysctl,
503 esdhc_read32(®s->sysctl) |
505 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
509 /* If this was CMD11, then notify that power cycle is needed */
510 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
511 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
514 esdhc_write32(®s->irqstat, -1);
519 static void set_sysctl(struct mmc *mmc, uint clock)
522 struct fsl_esdhc_priv *priv = mmc->priv;
523 struct fsl_esdhc *regs = priv->esdhc_regs;
524 int sdhc_clk = priv->sdhc_clk;
527 if (clock < mmc->cfg->f_min)
528 clock = mmc->cfg->f_min;
530 if (sdhc_clk / 16 > clock) {
531 for (pre_div = 2; pre_div < 256; pre_div *= 2)
532 if ((sdhc_clk / pre_div) <= (clock * 16))
537 for (div = 1; div <= 16; div++)
538 if ((sdhc_clk / (div * pre_div)) <= clock)
541 pre_div >>= mmc->ddr_mode ? 2 : 1;
544 clk = (pre_div << 8) | (div << 4);
546 #ifdef CONFIG_FSL_USDHC
547 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
549 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
552 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
556 #ifdef CONFIG_FSL_USDHC
557 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
559 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
564 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
565 static void esdhc_clock_control(struct mmc *mmc, bool enable)
567 struct fsl_esdhc_priv *priv = mmc->priv;
568 struct fsl_esdhc *regs = priv->esdhc_regs;
572 value = esdhc_read32(®s->sysctl);
575 value |= SYSCTL_CKEN;
577 value &= ~SYSCTL_CKEN;
579 esdhc_write32(®s->sysctl, value);
582 value = PRSSTAT_SDSTB;
583 while (!(esdhc_read32(®s->prsstat) & value)) {
585 printf("fsl_esdhc: Internal clock never stabilised.\n");
594 static void esdhc_set_ios(struct mmc *mmc)
596 struct fsl_esdhc_priv *priv = mmc->priv;
597 struct fsl_esdhc *regs = priv->esdhc_regs;
599 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
600 /* Select to use peripheral clock */
601 esdhc_clock_control(mmc, false);
602 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
603 esdhc_clock_control(mmc, true);
605 /* Set the clock speed */
606 set_sysctl(mmc, mmc->clock);
608 /* Set the bus width */
609 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
611 if (mmc->bus_width == 4)
612 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
613 else if (mmc->bus_width == 8)
614 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
618 static int esdhc_init(struct mmc *mmc)
620 struct fsl_esdhc_priv *priv = mmc->priv;
621 struct fsl_esdhc *regs = priv->esdhc_regs;
624 /* Reset the entire host controller */
625 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
627 /* Wait until the controller is available */
628 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
631 #if defined(CONFIG_FSL_USDHC)
632 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
633 esdhc_write32(®s->mmcboot, 0x0);
634 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
635 esdhc_write32(®s->mixctrl, 0x0);
636 esdhc_write32(®s->clktunectrlstatus, 0x0);
638 /* Put VEND_SPEC to default value */
639 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
641 /* Disable DLL_CTRL delay line */
642 esdhc_write32(®s->dllctrl, 0x0);
646 /* Enable cache snooping */
647 esdhc_write32(®s->scr, 0x00000040);
650 #ifndef CONFIG_FSL_USDHC
651 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
653 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
656 /* Set the initial clock speed */
657 mmc_set_clock(mmc, 400000);
659 /* Disable the BRR and BWR bits in IRQSTAT */
660 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
662 /* Put the PROCTL reg back to the default */
663 esdhc_write32(®s->proctl, PROCTL_INIT);
665 /* Set timout to the maximum value */
666 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
668 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
669 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
675 static int esdhc_getcd(struct mmc *mmc)
677 struct fsl_esdhc_priv *priv = mmc->priv;
678 struct fsl_esdhc *regs = priv->esdhc_regs;
681 #ifdef CONFIG_ESDHC_DETECT_QUIRK
682 if (CONFIG_ESDHC_DETECT_QUIRK)
687 if (priv->non_removable)
690 if (dm_gpio_is_valid(&priv->cd_gpio))
691 return dm_gpio_get_value(&priv->cd_gpio);
694 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
700 static void esdhc_reset(struct fsl_esdhc *regs)
702 unsigned long timeout = 100; /* wait max 100 ms */
704 /* reset the controller */
705 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
707 /* hardware clears the bit when it is done */
708 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
711 printf("MMC/SD: Reset never completed.\n");
714 static const struct mmc_ops esdhc_ops = {
715 .send_cmd = esdhc_send_cmd,
716 .set_ios = esdhc_set_ios,
718 .getcd = esdhc_getcd,
721 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
722 struct fsl_esdhc_priv *priv)
727 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
728 priv->bus_width = cfg->max_bus_width;
729 priv->sdhc_clk = cfg->sdhc_clk;
730 priv->wp_enable = cfg->wp_enable;
735 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
737 struct fsl_esdhc *regs;
739 u32 caps, voltage_caps;
744 regs = priv->esdhc_regs;
746 /* First reset the eSDHC controller */
749 #ifndef CONFIG_FSL_USDHC
750 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
751 | SYSCTL_IPGEN | SYSCTL_CKEN);
753 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
754 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
757 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
758 memset(&priv->cfg, 0, sizeof(priv->cfg));
761 caps = esdhc_read32(®s->hostcapblt);
763 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
764 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
765 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
768 /* T4240 host controller capabilities register should have VS33 bit */
769 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
770 caps = caps | ESDHC_HOSTCAPBLT_VS33;
773 if (caps & ESDHC_HOSTCAPBLT_VS18)
774 voltage_caps |= MMC_VDD_165_195;
775 if (caps & ESDHC_HOSTCAPBLT_VS30)
776 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
777 if (caps & ESDHC_HOSTCAPBLT_VS33)
778 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
780 priv->cfg.name = "FSL_SDHC";
781 priv->cfg.ops = &esdhc_ops;
782 #ifdef CONFIG_SYS_SD_VOLTAGE
783 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
785 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
787 if ((priv->cfg.voltages & voltage_caps) == 0) {
788 printf("voltage not supported by controller\n");
792 if (priv->bus_width == 8)
793 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
794 else if (priv->bus_width == 4)
795 priv->cfg.host_caps = MMC_MODE_4BIT;
797 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
798 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
799 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
802 if (priv->bus_width > 0) {
803 if (priv->bus_width < 8)
804 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
805 if (priv->bus_width < 4)
806 priv->cfg.host_caps &= ~MMC_MODE_4BIT;
809 if (caps & ESDHC_HOSTCAPBLT_HSS)
810 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
812 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
813 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
814 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
817 priv->cfg.f_min = 400000;
818 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
820 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
822 mmc = mmc_create(&priv->cfg, priv);
831 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
833 struct fsl_esdhc_priv *priv;
839 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
843 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
845 debug("%s xlate failure\n", __func__);
850 ret = fsl_esdhc_init(priv);
852 debug("%s init failure\n", __func__);
860 int fsl_esdhc_mmc_init(bd_t *bis)
862 struct fsl_esdhc_cfg *cfg;
864 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
865 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
866 cfg->sdhc_clk = gd->arch.sdhc_clk;
867 return fsl_esdhc_initialize(bis, cfg);
870 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
871 void mmc_adapter_card_type_ident(void)
876 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
877 gd->arch.sdhc_adapter = card_id;
880 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
881 value = QIXIS_READ(brdcfg[5]);
882 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
883 QIXIS_WRITE(brdcfg[5], value);
885 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
886 value = QIXIS_READ(pwr_ctl[1]);
887 value |= QIXIS_EVDD_BY_SDHC_VS;
888 QIXIS_WRITE(pwr_ctl[1], value);
890 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
891 value = QIXIS_READ(brdcfg[5]);
892 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
893 QIXIS_WRITE(brdcfg[5], value);
895 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
897 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
899 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
901 case QIXIS_ESDHC_NO_ADAPTER:
909 #ifdef CONFIG_OF_LIBFDT
910 void fdt_fixup_esdhc(void *blob, bd_t *bd)
912 const char *compat = "fsl,esdhc";
914 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
915 if (!hwconfig("esdhc")) {
916 do_fixup_by_compat(blob, compat, "status", "disabled",
922 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
923 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
924 gd->arch.sdhc_clk, 1);
926 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
927 gd->arch.sdhc_clk, 1);
929 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
930 do_fixup_by_compat_u32(blob, compat, "adapter-type",
931 (u32)(gd->arch.sdhc_adapter), 1);
933 do_fixup_by_compat(blob, compat, "status", "okay",
939 #include <asm/arch/clock.h>
940 static int fsl_esdhc_probe(struct udevice *dev)
942 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
943 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
944 const void *fdt = gd->fdt_blob;
945 int node = dev->of_offset;
950 addr = dev_get_addr(dev);
951 if (addr == FDT_ADDR_T_NONE)
954 priv->esdhc_regs = (struct fsl_esdhc *)addr;
957 val = fdtdec_get_int(fdt, node, "bus-width", -1);
965 if (fdt_get_property(fdt, node, "non-removable", NULL)) {
966 priv->non_removable = 1;
968 priv->non_removable = 0;
969 gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0,
970 &priv->cd_gpio, GPIOD_IS_IN);
975 ret = gpio_request_by_name_nodev(fdt, node, "wp-gpios", 0,
976 &priv->wp_gpio, GPIOD_IS_IN);
982 * Because lack of clk driver, if SDHC clk is not enabled,
983 * need to enable it first before this driver is invoked.
985 * we use MXC_ESDHC_CLK to get clk freq.
986 * If one would like to make this function work,
987 * the aliases should be provided in dts as this:
995 * Then if your board only supports mmc2 and mmc3, but we can
996 * correctly get the seq as 2 and 3, then let mxc_get_clock
999 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1000 if (priv->sdhc_clk <= 0) {
1001 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1005 ret = fsl_esdhc_init(priv);
1007 dev_err(dev, "fsl_esdhc_init failure\n");
1011 upriv->mmc = priv->mmc;
1016 static const struct udevice_id fsl_esdhc_ids[] = {
1017 { .compatible = "fsl,imx6ul-usdhc", },
1018 { .compatible = "fsl,imx6sx-usdhc", },
1019 { .compatible = "fsl,imx6sl-usdhc", },
1020 { .compatible = "fsl,imx6q-usdhc", },
1021 { .compatible = "fsl,imx7d-usdhc", },
1025 U_BOOT_DRIVER(fsl_esdhc) = {
1026 .name = "fsl-esdhc-mmc",
1028 .of_match = fsl_esdhc_ids,
1029 .probe = fsl_esdhc_probe,
1030 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),