1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
6 * Based vaguely on the pxa mmc code:
8 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
19 #include <power/regulator.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
25 #include <asm-generic/gpio.h>
26 #include <dm/pinctrl.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
32 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
33 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
34 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
36 #define MAX_TUNING_LOOP 40
39 uint dsaddr; /* SDMA system address register */
40 uint blkattr; /* Block attributes register */
41 uint cmdarg; /* Command argument register */
42 uint xfertyp; /* Transfer type register */
43 uint cmdrsp0; /* Command response 0 register */
44 uint cmdrsp1; /* Command response 1 register */
45 uint cmdrsp2; /* Command response 2 register */
46 uint cmdrsp3; /* Command response 3 register */
47 uint datport; /* Buffer data port register */
48 uint prsstat; /* Present state register */
49 uint proctl; /* Protocol control register */
50 uint sysctl; /* System Control Register */
51 uint irqstat; /* Interrupt status register */
52 uint irqstaten; /* Interrupt status enable register */
53 uint irqsigen; /* Interrupt signal enable register */
54 uint autoc12err; /* Auto CMD error status register */
55 uint hostcapblt; /* Host controller capabilities register */
56 uint wml; /* Watermark level register */
57 uint mixctrl; /* For USDHC */
58 char reserved1[4]; /* reserved */
59 uint fevt; /* Force event register */
60 uint admaes; /* ADMA error status register */
61 uint adsaddr; /* ADMA system address register */
65 uint clktunectrlstatus;
73 uint tuning_ctrl; /* on i.MX6/7/8 */
75 uint hostver; /* Host controller version register */
76 char reserved6[4]; /* reserved */
77 uint dmaerraddr; /* DMA error address register */
78 char reserved7[4]; /* reserved */
79 uint dmaerrattr; /* DMA error attribute register */
80 char reserved8[4]; /* reserved */
81 uint hostcapblt2; /* Host controller capabilities register 2 */
82 char reserved9[8]; /* reserved */
83 uint tcr; /* Tuning control register */
84 char reserved10[28]; /* reserved */
85 uint sddirctl; /* SD direction control register */
86 char reserved11[712];/* reserved */
87 uint scr; /* eSDHC control register */
90 struct fsl_esdhc_plat {
91 struct mmc_config cfg;
95 struct esdhc_soc_data {
101 * struct fsl_esdhc_priv
103 * @esdhc_regs: registers of the sdhc controller
104 * @sdhc_clk: Current clk of the sdhc controller
105 * @bus_width: bus width, 1bit, 4bit or 8bit
108 * Following is used when Driver Model is enabled for MMC
109 * @dev: pointer for the device
110 * @non_removable: 0: removable; 1: non-removable
111 * @wp_enable: 1: enable checking wp; 0: no check
112 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
113 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
114 * @caps: controller capabilities
115 * @tuning_step: tuning step setting in tuning_ctrl register
116 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
117 * @strobe_dll_delay_target: settings in strobe_dllctrl
118 * @signal_voltage: indicating the current voltage
119 * @cd_gpio: gpio for card detection
120 * @wp_gpio: gpio for write protection
122 struct fsl_esdhc_priv {
123 struct fsl_esdhc *esdhc_regs;
124 unsigned int sdhc_clk;
128 unsigned int bus_width;
129 #if !CONFIG_IS_ENABLED(BLK)
139 u32 tuning_start_tap;
140 u32 strobe_dll_delay_target;
142 #if IS_ENABLED(CONFIG_DM_REGULATOR)
143 struct udevice *vqmmc_dev;
144 struct udevice *vmmc_dev;
146 #ifdef CONFIG_DM_GPIO
147 struct gpio_desc cd_gpio;
148 struct gpio_desc wp_gpio;
152 /* Return the XFERTYP flags for a given command and data packet */
153 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
158 xfertyp |= XFERTYP_DPSEL;
159 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
160 xfertyp |= XFERTYP_DMAEN;
162 if (data->blocks > 1) {
163 xfertyp |= XFERTYP_MSBSEL;
164 xfertyp |= XFERTYP_BCEN;
165 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
166 xfertyp |= XFERTYP_AC12EN;
170 if (data->flags & MMC_DATA_READ)
171 xfertyp |= XFERTYP_DTDSEL;
174 if (cmd->resp_type & MMC_RSP_CRC)
175 xfertyp |= XFERTYP_CCCEN;
176 if (cmd->resp_type & MMC_RSP_OPCODE)
177 xfertyp |= XFERTYP_CICEN;
178 if (cmd->resp_type & MMC_RSP_136)
179 xfertyp |= XFERTYP_RSPTYP_136;
180 else if (cmd->resp_type & MMC_RSP_BUSY)
181 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
182 else if (cmd->resp_type & MMC_RSP_PRESENT)
183 xfertyp |= XFERTYP_RSPTYP_48;
185 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
186 xfertyp |= XFERTYP_CMDTYP_ABORT;
188 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
191 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
193 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
195 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
196 struct mmc_data *data)
198 struct fsl_esdhc *regs = priv->esdhc_regs;
206 if (data->flags & MMC_DATA_READ) {
207 blocks = data->blocks;
210 start = get_timer(0);
211 size = data->blocksize;
212 irqstat = esdhc_read32(®s->irqstat);
213 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
214 if (get_timer(start) > PIO_TIMEOUT) {
215 printf("\nData Read Failed in PIO Mode.");
219 while (size && (!(irqstat & IRQSTAT_TC))) {
220 udelay(100); /* Wait before last byte transfer complete */
221 irqstat = esdhc_read32(®s->irqstat);
222 databuf = in_le32(®s->datport);
223 *((uint *)buffer) = databuf;
230 blocks = data->blocks;
231 buffer = (char *)data->src;
233 start = get_timer(0);
234 size = data->blocksize;
235 irqstat = esdhc_read32(®s->irqstat);
236 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
237 if (get_timer(start) > PIO_TIMEOUT) {
238 printf("\nData Write Failed in PIO Mode.");
242 while (size && (!(irqstat & IRQSTAT_TC))) {
243 udelay(100); /* Wait before last byte transfer complete */
244 databuf = *((uint *)buffer);
247 irqstat = esdhc_read32(®s->irqstat);
248 out_le32(®s->datport, databuf);
256 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
257 struct mmc_data *data)
260 struct fsl_esdhc *regs = priv->esdhc_regs;
261 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
262 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
267 wml_value = data->blocksize/4;
269 if (data->flags & MMC_DATA_READ) {
270 if (wml_value > WML_RD_WML_MAX)
271 wml_value = WML_RD_WML_MAX_VAL;
273 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
274 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
275 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
276 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
277 addr = virt_to_phys((void *)(data->dest));
278 if (upper_32_bits(addr))
279 printf("Error found for upper 32 bits\n");
281 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
283 esdhc_write32(®s->dsaddr, (u32)data->dest);
287 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
288 flush_dcache_range((ulong)data->src,
289 (ulong)data->src+data->blocks
292 if (wml_value > WML_WR_WML_MAX)
293 wml_value = WML_WR_WML_MAX_VAL;
294 if (priv->wp_enable) {
295 if ((esdhc_read32(®s->prsstat) &
296 PRSSTAT_WPSPL) == 0) {
297 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
301 #ifdef CONFIG_DM_GPIO
302 if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
303 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
309 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
311 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
312 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
313 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
314 addr = virt_to_phys((void *)(data->src));
315 if (upper_32_bits(addr))
316 printf("Error found for upper 32 bits\n");
318 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
320 esdhc_write32(®s->dsaddr, (u32)data->src);
325 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
327 /* Calculate the timeout period for data transactions */
329 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
330 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
331 * So, Number of SD Clock cycles for 0.25sec should be minimum
332 * (SD Clock/sec * 0.25 sec) SD Clock cycles
333 * = (mmc->clock * 1/4) SD Clock cycles
335 * => (2^(timeout+13)) >= mmc->clock * 1/4
336 * Taking log2 both the sides
337 * => timeout + 13 >= log2(mmc->clock/4)
338 * Rounding up to next power of 2
339 * => timeout + 13 = log2(mmc->clock/4) + 1
340 * => timeout + 13 = fls(mmc->clock/4)
342 * However, the MMC spec "It is strongly recommended for hosts to
343 * implement more than 500ms timeout value even if the card
344 * indicates the 250ms maximum busy length." Even the previous
345 * value of 300ms is known to be insufficient for some cards.
347 * => timeout + 13 = fls(mmc->clock/2)
349 timeout = fls(mmc->clock/2);
358 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
359 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
363 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
366 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
371 static void check_and_invalidate_dcache_range
372 (struct mmc_cmd *cmd,
373 struct mmc_data *data) {
376 unsigned size = roundup(ARCH_DMA_MINALIGN,
377 data->blocks*data->blocksize);
378 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
379 defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
382 addr = virt_to_phys((void *)(data->dest));
383 if (upper_32_bits(addr))
384 printf("Error found for upper 32 bits\n");
386 start = lower_32_bits(addr);
388 start = (unsigned)data->dest;
391 invalidate_dcache_range(start, end);
394 #ifdef CONFIG_MCF5441x
396 * Swaps 32-bit words to little-endian byte order.
398 static inline void sd_swap_dma_buff(struct mmc_data *data)
400 int i, size = data->blocksize >> 2;
401 u32 *buffer = (u32 *)data->dest;
404 while (data->blocks--) {
405 for (i = 0; i < size; i++) {
406 sw = __sw32(*buffer);
414 * Sends a command out on the bus. Takes the mmc pointer,
415 * a command pointer, and an optional data pointer.
417 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
418 struct mmc_cmd *cmd, struct mmc_data *data)
423 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
424 struct fsl_esdhc *regs = priv->esdhc_regs;
427 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
428 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
432 esdhc_write32(®s->irqstat, -1);
436 /* Wait for the bus to be idle */
437 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
438 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
441 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
444 /* Wait at least 8 SD clock cycles before the next command */
446 * Note: This is way more than 8 cycles, but 1ms seems to
447 * resolve timing issues with some cards
451 /* Set up for a data transfer if we have one */
453 err = esdhc_setup_data(priv, mmc, data);
457 if (data->flags & MMC_DATA_READ)
458 check_and_invalidate_dcache_range(cmd, data);
461 /* Figure out the transfer arguments */
462 xfertyp = esdhc_xfertyp(cmd, data);
465 esdhc_write32(®s->irqsigen, 0);
467 /* Send the command */
468 esdhc_write32(®s->cmdarg, cmd->cmdarg);
469 #if defined(CONFIG_FSL_USDHC)
470 esdhc_write32(®s->mixctrl,
471 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
472 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
473 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
475 esdhc_write32(®s->xfertyp, xfertyp);
478 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
479 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
482 /* Wait for the command to complete */
483 start = get_timer(0);
484 while (!(esdhc_read32(®s->irqstat) & flags)) {
485 if (get_timer(start) > 1000) {
491 irqstat = esdhc_read32(®s->irqstat);
493 if (irqstat & CMD_ERR) {
498 if (irqstat & IRQSTAT_CTOE) {
503 /* Switch voltage to 1.8V if CMD11 succeeded */
504 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
505 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
507 printf("Run CMD11 1.8V switch\n");
508 /* Sleep for 5 ms - max time for card to switch to 1.8V */
512 /* Workaround for ESDHC errata ENGcm03648 */
513 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
516 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
517 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
524 printf("Timeout waiting for DAT0 to go high!\n");
530 /* Copy the response to the response buffer */
531 if (cmd->resp_type & MMC_RSP_136) {
532 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
534 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
535 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
536 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
537 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
538 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
539 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
540 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
541 cmd->response[3] = (cmdrsp0 << 8);
543 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
545 /* Wait until all of the blocks are transferred */
547 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
548 esdhc_pio_read_write(priv, data);
550 flags = DATA_COMPLETE;
551 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
552 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
557 irqstat = esdhc_read32(®s->irqstat);
559 if (irqstat & IRQSTAT_DTOE) {
564 if (irqstat & DATA_ERR) {
568 } while ((irqstat & flags) != flags);
571 * Need invalidate the dcache here again to avoid any
572 * cache-fill during the DMA operations such as the
573 * speculative pre-fetching etc.
575 if (data->flags & MMC_DATA_READ) {
576 check_and_invalidate_dcache_range(cmd, data);
577 #ifdef CONFIG_MCF5441x
578 sd_swap_dma_buff(data);
585 /* Reset CMD and DATA portions on error */
587 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
589 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
593 esdhc_write32(®s->sysctl,
594 esdhc_read32(®s->sysctl) |
596 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
600 /* If this was CMD11, then notify that power cycle is needed */
601 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
602 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
605 esdhc_write32(®s->irqstat, -1);
610 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
612 struct fsl_esdhc *regs = priv->esdhc_regs;
616 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
617 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
624 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
625 int sdhc_clk = priv->sdhc_clk;
628 if (clock < mmc->cfg->f_min)
629 clock = mmc->cfg->f_min;
631 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
634 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
640 clk = (pre_div << 8) | (div << 4);
642 #ifdef CONFIG_FSL_USDHC
643 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
645 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
648 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
652 #ifdef CONFIG_FSL_USDHC
653 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
655 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
661 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
662 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
664 struct fsl_esdhc *regs = priv->esdhc_regs;
668 value = esdhc_read32(®s->sysctl);
671 value |= SYSCTL_CKEN;
673 value &= ~SYSCTL_CKEN;
675 esdhc_write32(®s->sysctl, value);
678 value = PRSSTAT_SDSTB;
679 while (!(esdhc_read32(®s->prsstat) & value)) {
681 printf("fsl_esdhc: Internal clock never stabilised.\n");
690 #ifdef MMC_SUPPORTS_TUNING
691 static int esdhc_change_pinstate(struct udevice *dev)
693 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
696 switch (priv->mode) {
699 ret = pinctrl_select_state(dev, "state_100mhz");
704 ret = pinctrl_select_state(dev, "state_200mhz");
707 ret = pinctrl_select_state(dev, "default");
712 printf("%s %d error\n", __func__, priv->mode);
717 static void esdhc_reset_tuning(struct mmc *mmc)
719 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
720 struct fsl_esdhc *regs = priv->esdhc_regs;
722 if (priv->flags & ESDHC_FLAG_USDHC) {
723 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
724 esdhc_clrbits32(®s->autoc12err,
725 MIX_CTRL_SMPCLK_SEL |
731 static void esdhc_set_strobe_dll(struct mmc *mmc)
733 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
734 struct fsl_esdhc *regs = priv->esdhc_regs;
737 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
738 writel(ESDHC_STROBE_DLL_CTRL_RESET, ®s->strobe_dllctrl);
741 * enable strobe dll ctrl and adjust the delay target
742 * for the uSDHC loopback read clock
744 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
745 (priv->strobe_dll_delay_target <<
746 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
747 writel(val, ®s->strobe_dllctrl);
748 /* wait 1us to make sure strobe dll status register stable */
750 val = readl(®s->strobe_dllstat);
751 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
752 pr_warn("HS400 strobe DLL status REF not lock!\n");
753 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
754 pr_warn("HS400 strobe DLL status SLV not lock!\n");
758 static int esdhc_set_timing(struct mmc *mmc)
760 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
761 struct fsl_esdhc *regs = priv->esdhc_regs;
764 mixctrl = readl(®s->mixctrl);
765 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
767 switch (mmc->selected_mode) {
770 esdhc_reset_tuning(mmc);
771 writel(mixctrl, ®s->mixctrl);
774 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
775 writel(mixctrl, ®s->mixctrl);
776 esdhc_set_strobe_dll(mmc);
786 writel(mixctrl, ®s->mixctrl);
790 mixctrl |= MIX_CTRL_DDREN;
791 writel(mixctrl, ®s->mixctrl);
794 printf("Not supported %d\n", mmc->selected_mode);
798 priv->mode = mmc->selected_mode;
800 return esdhc_change_pinstate(mmc->dev);
803 static int esdhc_set_voltage(struct mmc *mmc)
805 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
806 struct fsl_esdhc *regs = priv->esdhc_regs;
809 priv->signal_voltage = mmc->signal_voltage;
810 switch (mmc->signal_voltage) {
811 case MMC_SIGNAL_VOLTAGE_330:
812 if (priv->vs18_enable)
814 #if CONFIG_IS_ENABLED(DM_REGULATOR)
815 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
816 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
818 printf("Setting to 3.3V error");
826 esdhc_clrbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
827 if (!(esdhc_read32(®s->vendorspec) &
828 ESDHC_VENDORSPEC_VSELECT))
832 case MMC_SIGNAL_VOLTAGE_180:
833 #if CONFIG_IS_ENABLED(DM_REGULATOR)
834 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
835 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
837 printf("Setting to 1.8V error");
842 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
843 if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
847 case MMC_SIGNAL_VOLTAGE_120:
854 static void esdhc_stop_tuning(struct mmc *mmc)
858 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
860 cmd.resp_type = MMC_RSP_R1b;
862 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
865 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
867 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
868 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
869 struct fsl_esdhc *regs = priv->esdhc_regs;
870 struct mmc *mmc = &plat->mmc;
871 u32 irqstaten = readl(®s->irqstaten);
872 u32 irqsigen = readl(®s->irqsigen);
873 int i, ret = -ETIMEDOUT;
876 /* clock tuning is not needed for upto 52MHz */
877 if (mmc->clock <= 52000000)
880 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
881 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
882 val = readl(®s->autoc12err);
883 mixctrl = readl(®s->mixctrl);
884 val &= ~MIX_CTRL_SMPCLK_SEL;
885 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
887 val |= MIX_CTRL_EXE_TUNE;
888 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
890 writel(val, ®s->autoc12err);
891 writel(mixctrl, ®s->mixctrl);
894 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
895 mixctrl = readl(®s->mixctrl);
896 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
897 writel(mixctrl, ®s->mixctrl);
899 writel(IRQSTATEN_BRR, ®s->irqstaten);
900 writel(IRQSTATEN_BRR, ®s->irqsigen);
903 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
904 * of loops reaches 40 times.
906 for (i = 0; i < MAX_TUNING_LOOP; i++) {
909 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
910 if (mmc->bus_width == 8)
911 writel(0x7080, ®s->blkattr);
912 else if (mmc->bus_width == 4)
913 writel(0x7040, ®s->blkattr);
915 writel(0x7040, ®s->blkattr);
918 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
919 val = readl(®s->mixctrl);
920 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
921 writel(val, ®s->mixctrl);
923 /* We are using STD tuning, no need to check return value */
924 mmc_send_tuning(mmc, opcode, NULL);
926 ctrl = readl(®s->autoc12err);
927 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
928 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
930 * need to wait some time, make sure sd/mmc fininsh
931 * send out tuning data, otherwise, the sd/mmc can't
932 * response to any command when the card still out
933 * put the tuning data.
940 /* Add 1ms delay for SD and eMMC */
944 writel(irqstaten, ®s->irqstaten);
945 writel(irqsigen, ®s->irqsigen);
947 esdhc_stop_tuning(mmc);
953 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
955 struct fsl_esdhc *regs = priv->esdhc_regs;
956 int ret __maybe_unused;
958 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
959 /* Select to use peripheral clock */
960 esdhc_clock_control(priv, false);
961 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
962 esdhc_clock_control(priv, true);
964 /* Set the clock speed */
965 if (priv->clock != mmc->clock)
966 set_sysctl(priv, mmc, mmc->clock);
968 #ifdef MMC_SUPPORTS_TUNING
969 if (mmc->clk_disable) {
970 #ifdef CONFIG_FSL_USDHC
971 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
973 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
976 #ifdef CONFIG_FSL_USDHC
977 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
980 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
984 if (priv->mode != mmc->selected_mode) {
985 ret = esdhc_set_timing(mmc);
987 printf("esdhc_set_timing error %d\n", ret);
992 if (priv->signal_voltage != mmc->signal_voltage) {
993 ret = esdhc_set_voltage(mmc);
995 printf("esdhc_set_voltage error %d\n", ret);
1001 /* Set the bus width */
1002 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
1004 if (mmc->bus_width == 4)
1005 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
1006 else if (mmc->bus_width == 8)
1007 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
1012 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1014 struct fsl_esdhc *regs = priv->esdhc_regs;
1017 /* Reset the entire host controller */
1018 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1020 /* Wait until the controller is available */
1021 start = get_timer(0);
1022 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1023 if (get_timer(start) > 1000)
1027 #if defined(CONFIG_FSL_USDHC)
1028 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1029 esdhc_write32(®s->mmcboot, 0x0);
1030 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1031 esdhc_write32(®s->mixctrl, 0x0);
1032 esdhc_write32(®s->clktunectrlstatus, 0x0);
1034 /* Put VEND_SPEC to default value */
1035 if (priv->vs18_enable)
1036 esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT |
1037 ESDHC_VENDORSPEC_VSELECT));
1039 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
1041 /* Disable DLL_CTRL delay line */
1042 esdhc_write32(®s->dllctrl, 0x0);
1046 /* Enable cache snooping */
1047 esdhc_write32(®s->scr, 0x00000040);
1050 #ifndef CONFIG_FSL_USDHC
1051 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1053 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1056 /* Set the initial clock speed */
1057 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1059 /* Disable the BRR and BWR bits in IRQSTAT */
1060 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1062 #ifdef CONFIG_MCF5441x
1063 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1065 /* Put the PROCTL reg back to the default */
1066 esdhc_write32(®s->proctl, PROCTL_INIT);
1069 /* Set timout to the maximum value */
1070 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1075 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1077 struct fsl_esdhc *regs = priv->esdhc_regs;
1080 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1081 if (CONFIG_ESDHC_DETECT_QUIRK)
1085 #if CONFIG_IS_ENABLED(DM_MMC)
1086 if (priv->non_removable)
1088 #ifdef CONFIG_DM_GPIO
1089 if (dm_gpio_is_valid(&priv->cd_gpio))
1090 return dm_gpio_get_value(&priv->cd_gpio);
1094 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
1100 static int esdhc_reset(struct fsl_esdhc *regs)
1104 /* reset the controller */
1105 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
1107 /* hardware clears the bit when it is done */
1108 start = get_timer(0);
1109 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
1110 if (get_timer(start) > 100) {
1111 printf("MMC/SD: Reset never completed.\n");
1119 #if !CONFIG_IS_ENABLED(DM_MMC)
1120 static int esdhc_getcd(struct mmc *mmc)
1122 struct fsl_esdhc_priv *priv = mmc->priv;
1124 return esdhc_getcd_common(priv);
1127 static int esdhc_init(struct mmc *mmc)
1129 struct fsl_esdhc_priv *priv = mmc->priv;
1131 return esdhc_init_common(priv, mmc);
1134 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1135 struct mmc_data *data)
1137 struct fsl_esdhc_priv *priv = mmc->priv;
1139 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1142 static int esdhc_set_ios(struct mmc *mmc)
1144 struct fsl_esdhc_priv *priv = mmc->priv;
1146 return esdhc_set_ios_common(priv, mmc);
1149 static const struct mmc_ops esdhc_ops = {
1150 .getcd = esdhc_getcd,
1152 .send_cmd = esdhc_send_cmd,
1153 .set_ios = esdhc_set_ios,
1157 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1158 struct fsl_esdhc_plat *plat)
1160 struct mmc_config *cfg;
1161 struct fsl_esdhc *regs;
1162 u32 caps, voltage_caps;
1168 regs = priv->esdhc_regs;
1170 /* First reset the eSDHC controller */
1171 ret = esdhc_reset(regs);
1175 #ifdef CONFIG_MCF5441x
1176 /* ColdFire, using SDHC_DATA[3] for card detection */
1177 esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
1180 #ifndef CONFIG_FSL_USDHC
1181 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1182 | SYSCTL_IPGEN | SYSCTL_CKEN);
1183 /* Clearing tuning bits in case ROM has set it already */
1184 esdhc_write32(®s->mixctrl, 0);
1185 esdhc_write32(®s->autoc12err, 0);
1186 esdhc_write32(®s->clktunectrlstatus, 0);
1188 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
1189 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1192 if (priv->vs18_enable)
1193 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1195 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
1197 #ifndef CONFIG_DM_MMC
1198 memset(cfg, '\0', sizeof(*cfg));
1202 caps = esdhc_read32(®s->hostcapblt);
1204 #ifdef CONFIG_MCF5441x
1206 * MCF5441x RM declares in more points that sdhc clock speed must
1207 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1208 * from host capabilities.
1210 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1213 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1214 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1215 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1218 /* T4240 host controller capabilities register should have VS33 bit */
1219 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1220 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1223 if (caps & ESDHC_HOSTCAPBLT_VS18)
1224 voltage_caps |= MMC_VDD_165_195;
1225 if (caps & ESDHC_HOSTCAPBLT_VS30)
1226 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1227 if (caps & ESDHC_HOSTCAPBLT_VS33)
1228 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1230 cfg->name = "FSL_SDHC";
1231 #if !CONFIG_IS_ENABLED(DM_MMC)
1232 cfg->ops = &esdhc_ops;
1234 #ifdef CONFIG_SYS_SD_VOLTAGE
1235 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1237 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1239 if ((cfg->voltages & voltage_caps) == 0) {
1240 printf("voltage not supported by controller\n");
1244 if (priv->bus_width == 8)
1245 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1246 else if (priv->bus_width == 4)
1247 cfg->host_caps = MMC_MODE_4BIT;
1249 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1250 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1251 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1254 if (priv->bus_width > 0) {
1255 if (priv->bus_width < 8)
1256 cfg->host_caps &= ~MMC_MODE_8BIT;
1257 if (priv->bus_width < 4)
1258 cfg->host_caps &= ~MMC_MODE_4BIT;
1261 if (caps & ESDHC_HOSTCAPBLT_HSS)
1262 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1264 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1265 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1266 cfg->host_caps &= ~MMC_MODE_8BIT;
1269 cfg->host_caps |= priv->caps;
1271 cfg->f_min = 400000;
1272 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1274 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1276 writel(0, ®s->dllctrl);
1277 if (priv->flags & ESDHC_FLAG_USDHC) {
1278 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1279 u32 val = readl(®s->tuning_ctrl);
1281 val |= ESDHC_STD_TUNING_EN;
1282 val &= ~ESDHC_TUNING_START_TAP_MASK;
1283 val |= priv->tuning_start_tap;
1284 val &= ~ESDHC_TUNING_STEP_MASK;
1285 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1286 writel(val, ®s->tuning_ctrl);
1293 #if !CONFIG_IS_ENABLED(DM_MMC)
1294 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1295 struct fsl_esdhc_priv *priv)
1300 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1301 priv->bus_width = cfg->max_bus_width;
1302 priv->sdhc_clk = cfg->sdhc_clk;
1303 priv->wp_enable = cfg->wp_enable;
1304 priv->vs18_enable = cfg->vs18_enable;
1309 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1311 struct fsl_esdhc_plat *plat;
1312 struct fsl_esdhc_priv *priv;
1319 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1322 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1328 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1330 debug("%s xlate failure\n", __func__);
1336 ret = fsl_esdhc_init(priv, plat);
1338 debug("%s init failure\n", __func__);
1344 mmc = mmc_create(&plat->cfg, priv);
1353 int fsl_esdhc_mmc_init(bd_t *bis)
1355 struct fsl_esdhc_cfg *cfg;
1357 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1358 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1359 cfg->sdhc_clk = gd->arch.sdhc_clk;
1360 return fsl_esdhc_initialize(bis, cfg);
1364 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1365 void mmc_adapter_card_type_ident(void)
1370 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
1371 gd->arch.sdhc_adapter = card_id;
1374 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
1375 value = QIXIS_READ(brdcfg[5]);
1376 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
1377 QIXIS_WRITE(brdcfg[5], value);
1379 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
1380 value = QIXIS_READ(pwr_ctl[1]);
1381 value |= QIXIS_EVDD_BY_SDHC_VS;
1382 QIXIS_WRITE(pwr_ctl[1], value);
1384 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
1385 value = QIXIS_READ(brdcfg[5]);
1386 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
1387 QIXIS_WRITE(brdcfg[5], value);
1389 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
1391 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
1393 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
1395 case QIXIS_ESDHC_NO_ADAPTER:
1403 #ifdef CONFIG_OF_LIBFDT
1404 __weak int esdhc_status_fixup(void *blob, const char *compat)
1406 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1407 if (!hwconfig("esdhc")) {
1408 do_fixup_by_compat(blob, compat, "status", "disabled",
1409 sizeof("disabled"), 1);
1416 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1418 const char *compat = "fsl,esdhc";
1420 if (esdhc_status_fixup(blob, compat))
1423 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1424 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1425 gd->arch.sdhc_clk, 1);
1427 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1428 gd->arch.sdhc_clk, 1);
1430 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1431 do_fixup_by_compat_u32(blob, compat, "adapter-type",
1432 (u32)(gd->arch.sdhc_adapter), 1);
1437 #if CONFIG_IS_ENABLED(DM_MMC)
1439 #include <asm/arch/clock.h>
1441 __weak void init_clk_usdhc(u32 index)
1445 static int fsl_esdhc_probe(struct udevice *dev)
1447 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1448 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1449 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1450 const void *fdt = gd->fdt_blob;
1451 int node = dev_of_offset(dev);
1452 struct esdhc_soc_data *data =
1453 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1454 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1455 struct udevice *vqmmc_dev;
1462 addr = dev_read_addr(dev);
1463 if (addr == FDT_ADDR_T_NONE)
1466 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
1468 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1473 priv->flags = data->flags;
1474 priv->caps = data->caps;
1477 val = dev_read_u32_default(dev, "bus-width", -1);
1479 priv->bus_width = 8;
1481 priv->bus_width = 4;
1483 priv->bus_width = 1;
1485 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1486 priv->tuning_step = val;
1487 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1488 ESDHC_TUNING_START_TAP_DEFAULT);
1489 priv->tuning_start_tap = val;
1490 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1491 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1492 priv->strobe_dll_delay_target = val;
1494 if (dev_read_bool(dev, "non-removable")) {
1495 priv->non_removable = 1;
1497 priv->non_removable = 0;
1498 #ifdef CONFIG_DM_GPIO
1499 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1504 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1505 priv->wp_enable = 1;
1507 priv->wp_enable = 0;
1508 #ifdef CONFIG_DM_GPIO
1509 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1514 priv->vs18_enable = 0;
1516 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1518 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1519 * otherwise, emmc will work abnormally.
1521 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1523 dev_dbg(dev, "no vqmmc-supply\n");
1525 ret = regulator_set_enable(vqmmc_dev, true);
1527 dev_err(dev, "fail to enable vqmmc-supply\n");
1531 if (regulator_get_value(vqmmc_dev) == 1800000)
1532 priv->vs18_enable = 1;
1536 if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
1537 priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);
1541 * Because lack of clk driver, if SDHC clk is not enabled,
1542 * need to enable it first before this driver is invoked.
1544 * we use MXC_ESDHC_CLK to get clk freq.
1545 * If one would like to make this function work,
1546 * the aliases should be provided in dts as this:
1554 * Then if your board only supports mmc2 and mmc3, but we can
1555 * correctly get the seq as 2 and 3, then let mxc_get_clock
1559 init_clk_usdhc(dev->seq);
1561 if (IS_ENABLED(CONFIG_CLK)) {
1562 /* Assigned clock already set clock */
1563 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1565 printf("Failed to get per_clk\n");
1568 ret = clk_enable(&priv->per_clk);
1570 printf("Failed to enable per_clk\n");
1574 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1577 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1579 priv->sdhc_clk = gd->arch.sdhc_clk;
1581 if (priv->sdhc_clk <= 0) {
1582 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1587 ret = fsl_esdhc_init(priv, plat);
1589 dev_err(dev, "fsl_esdhc_init failure\n");
1594 mmc->cfg = &plat->cfg;
1598 return esdhc_init_common(priv, mmc);
1601 #if CONFIG_IS_ENABLED(DM_MMC)
1602 static int fsl_esdhc_get_cd(struct udevice *dev)
1604 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1606 return esdhc_getcd_common(priv);
1609 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1610 struct mmc_data *data)
1612 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1613 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1615 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1618 static int fsl_esdhc_set_ios(struct udevice *dev)
1620 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1621 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1623 return esdhc_set_ios_common(priv, &plat->mmc);
1626 static const struct dm_mmc_ops fsl_esdhc_ops = {
1627 .get_cd = fsl_esdhc_get_cd,
1628 .send_cmd = fsl_esdhc_send_cmd,
1629 .set_ios = fsl_esdhc_set_ios,
1630 #ifdef MMC_SUPPORTS_TUNING
1631 .execute_tuning = fsl_esdhc_execute_tuning,
1636 static struct esdhc_soc_data usdhc_imx7d_data = {
1637 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1638 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1640 .caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
1641 MMC_MODE_HS_52MHz | MMC_MODE_HS,
1644 static const struct udevice_id fsl_esdhc_ids[] = {
1645 { .compatible = "fsl,imx53-esdhc", },
1646 { .compatible = "fsl,imx6ul-usdhc", },
1647 { .compatible = "fsl,imx6sx-usdhc", },
1648 { .compatible = "fsl,imx6sl-usdhc", },
1649 { .compatible = "fsl,imx6q-usdhc", },
1650 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1651 { .compatible = "fsl,imx7ulp-usdhc", },
1652 { .compatible = "fsl,esdhc", },
1656 #if CONFIG_IS_ENABLED(BLK)
1657 static int fsl_esdhc_bind(struct udevice *dev)
1659 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1661 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1665 U_BOOT_DRIVER(fsl_esdhc) = {
1666 .name = "fsl-esdhc-mmc",
1668 .of_match = fsl_esdhc_ids,
1669 .ops = &fsl_esdhc_ops,
1670 #if CONFIG_IS_ENABLED(BLK)
1671 .bind = fsl_esdhc_bind,
1673 .probe = fsl_esdhc_probe,
1674 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1675 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),