1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
7 * Based vaguely on the pxa mmc code:
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
26 #if !CONFIG_IS_ENABLED(BLK)
27 #include "mmc_private.h"
30 DECLARE_GLOBAL_DATA_PTR;
32 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
34 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
35 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
36 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
38 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
41 uint dsaddr; /* SDMA system address register */
42 uint blkattr; /* Block attributes register */
43 uint cmdarg; /* Command argument register */
44 uint xfertyp; /* Transfer type register */
45 uint cmdrsp0; /* Command response 0 register */
46 uint cmdrsp1; /* Command response 1 register */
47 uint cmdrsp2; /* Command response 2 register */
48 uint cmdrsp3; /* Command response 3 register */
49 uint datport; /* Buffer data port register */
50 uint prsstat; /* Present state register */
51 uint proctl; /* Protocol control register */
52 uint sysctl; /* System Control Register */
53 uint irqstat; /* Interrupt status register */
54 uint irqstaten; /* Interrupt status enable register */
55 uint irqsigen; /* Interrupt signal enable register */
56 uint autoc12err; /* Auto CMD error status register */
57 uint hostcapblt; /* Host controller capabilities register */
58 uint wml; /* Watermark level register */
59 char reserved1[8]; /* reserved */
60 uint fevt; /* Force event register */
61 uint admaes; /* ADMA error status register */
62 uint adsaddr; /* ADMA system address register */
64 uint hostver; /* Host controller version register */
65 char reserved3[4]; /* reserved */
66 uint dmaerraddr; /* DMA error address register */
67 char reserved4[4]; /* reserved */
68 uint dmaerrattr; /* DMA error attribute register */
69 char reserved5[4]; /* reserved */
70 uint hostcapblt2; /* Host controller capabilities register 2 */
71 char reserved6[756]; /* reserved */
72 uint esdhcctl; /* eSDHC control register */
75 struct fsl_esdhc_plat {
76 struct mmc_config cfg;
81 * struct fsl_esdhc_priv
83 * @esdhc_regs: registers of the sdhc controller
84 * @sdhc_clk: Current clk of the sdhc controller
85 * @bus_width: bus width, 1bit, 4bit or 8bit
88 * Following is used when Driver Model is enabled for MMC
89 * @dev: pointer for the device
90 * @non_removable: 0: removable; 1: non-removable
91 * @wp_enable: 1: enable checking wp; 0: no check
92 * @cd_gpio: gpio for card detection
93 * @wp_gpio: gpio for write protection
95 struct fsl_esdhc_priv {
96 struct fsl_esdhc *esdhc_regs;
97 unsigned int sdhc_clk;
100 unsigned int bus_width;
101 #if !CONFIG_IS_ENABLED(BLK)
109 /* Return the XFERTYP flags for a given command and data packet */
110 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
115 xfertyp |= XFERTYP_DPSEL;
116 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
117 xfertyp |= XFERTYP_DMAEN;
119 if (data->blocks > 1) {
120 xfertyp |= XFERTYP_MSBSEL;
121 xfertyp |= XFERTYP_BCEN;
122 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
123 xfertyp |= XFERTYP_AC12EN;
127 if (data->flags & MMC_DATA_READ)
128 xfertyp |= XFERTYP_DTDSEL;
131 if (cmd->resp_type & MMC_RSP_CRC)
132 xfertyp |= XFERTYP_CCCEN;
133 if (cmd->resp_type & MMC_RSP_OPCODE)
134 xfertyp |= XFERTYP_CICEN;
135 if (cmd->resp_type & MMC_RSP_136)
136 xfertyp |= XFERTYP_RSPTYP_136;
137 else if (cmd->resp_type & MMC_RSP_BUSY)
138 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
139 else if (cmd->resp_type & MMC_RSP_PRESENT)
140 xfertyp |= XFERTYP_RSPTYP_48;
142 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
143 xfertyp |= XFERTYP_CMDTYP_ABORT;
145 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
148 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
150 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
152 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
153 struct mmc_data *data)
155 struct fsl_esdhc *regs = priv->esdhc_regs;
163 if (data->flags & MMC_DATA_READ) {
164 blocks = data->blocks;
167 start = get_timer(0);
168 size = data->blocksize;
169 irqstat = esdhc_read32(®s->irqstat);
170 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
171 if (get_timer(start) > PIO_TIMEOUT) {
172 printf("\nData Read Failed in PIO Mode.");
176 while (size && (!(irqstat & IRQSTAT_TC))) {
177 udelay(100); /* Wait before last byte transfer complete */
178 irqstat = esdhc_read32(®s->irqstat);
179 databuf = in_le32(®s->datport);
180 *((uint *)buffer) = databuf;
187 blocks = data->blocks;
188 buffer = (char *)data->src;
190 start = get_timer(0);
191 size = data->blocksize;
192 irqstat = esdhc_read32(®s->irqstat);
193 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
194 if (get_timer(start) > PIO_TIMEOUT) {
195 printf("\nData Write Failed in PIO Mode.");
199 while (size && (!(irqstat & IRQSTAT_TC))) {
200 udelay(100); /* Wait before last byte transfer complete */
201 databuf = *((uint *)buffer);
204 irqstat = esdhc_read32(®s->irqstat);
205 out_le32(®s->datport, databuf);
213 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
214 struct mmc_data *data)
217 struct fsl_esdhc *regs = priv->esdhc_regs;
218 #if defined(CONFIG_FSL_LAYERSCAPE)
223 wml_value = data->blocksize/4;
225 if (data->flags & MMC_DATA_READ) {
226 if (wml_value > WML_RD_WML_MAX)
227 wml_value = WML_RD_WML_MAX_VAL;
229 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
230 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
231 #if defined(CONFIG_FSL_LAYERSCAPE)
232 addr = virt_to_phys((void *)(data->dest));
233 if (upper_32_bits(addr))
234 printf("Error found for upper 32 bits\n");
236 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
238 esdhc_write32(®s->dsaddr, (u32)data->dest);
242 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
243 flush_dcache_range((ulong)data->src,
244 (ulong)data->src+data->blocks
247 if (wml_value > WML_WR_WML_MAX)
248 wml_value = WML_WR_WML_MAX_VAL;
249 if (priv->wp_enable) {
250 if ((esdhc_read32(®s->prsstat) &
251 PRSSTAT_WPSPL) == 0) {
252 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
257 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
259 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
260 #if defined(CONFIG_FSL_LAYERSCAPE)
261 addr = virt_to_phys((void *)(data->src));
262 if (upper_32_bits(addr))
263 printf("Error found for upper 32 bits\n");
265 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
267 esdhc_write32(®s->dsaddr, (u32)data->src);
272 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
274 /* Calculate the timeout period for data transactions */
276 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
277 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
278 * So, Number of SD Clock cycles for 0.25sec should be minimum
279 * (SD Clock/sec * 0.25 sec) SD Clock cycles
280 * = (mmc->clock * 1/4) SD Clock cycles
282 * => (2^(timeout+13)) >= mmc->clock * 1/4
283 * Taking log2 both the sides
284 * => timeout + 13 >= log2(mmc->clock/4)
285 * Rounding up to next power of 2
286 * => timeout + 13 = log2(mmc->clock/4) + 1
287 * => timeout + 13 = fls(mmc->clock/4)
289 * However, the MMC spec "It is strongly recommended for hosts to
290 * implement more than 500ms timeout value even if the card
291 * indicates the 250ms maximum busy length." Even the previous
292 * value of 300ms is known to be insufficient for some cards.
294 * => timeout + 13 = fls(mmc->clock/2)
296 timeout = fls(mmc->clock/2);
305 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
306 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
310 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
313 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
318 static void check_and_invalidate_dcache_range
319 (struct mmc_cmd *cmd,
320 struct mmc_data *data) {
323 unsigned size = roundup(ARCH_DMA_MINALIGN,
324 data->blocks*data->blocksize);
325 #if defined(CONFIG_FSL_LAYERSCAPE)
328 addr = virt_to_phys((void *)(data->dest));
329 if (upper_32_bits(addr))
330 printf("Error found for upper 32 bits\n");
332 start = lower_32_bits(addr);
334 start = (unsigned)data->dest;
337 invalidate_dcache_range(start, end);
341 * Sends a command out on the bus. Takes the mmc pointer,
342 * a command pointer, and an optional data pointer.
344 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
345 struct mmc_cmd *cmd, struct mmc_data *data)
350 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
351 struct fsl_esdhc *regs = priv->esdhc_regs;
354 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
355 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
359 esdhc_write32(®s->irqstat, -1);
363 /* Wait for the bus to be idle */
364 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
365 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
368 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
371 /* Wait at least 8 SD clock cycles before the next command */
373 * Note: This is way more than 8 cycles, but 1ms seems to
374 * resolve timing issues with some cards
378 /* Set up for a data transfer if we have one */
380 err = esdhc_setup_data(priv, mmc, data);
384 if (data->flags & MMC_DATA_READ)
385 check_and_invalidate_dcache_range(cmd, data);
388 /* Figure out the transfer arguments */
389 xfertyp = esdhc_xfertyp(cmd, data);
392 esdhc_write32(®s->irqsigen, 0);
394 /* Send the command */
395 esdhc_write32(®s->cmdarg, cmd->cmdarg);
396 esdhc_write32(®s->xfertyp, xfertyp);
398 /* Wait for the command to complete */
399 start = get_timer(0);
400 while (!(esdhc_read32(®s->irqstat) & flags)) {
401 if (get_timer(start) > 1000) {
407 irqstat = esdhc_read32(®s->irqstat);
409 if (irqstat & CMD_ERR) {
414 if (irqstat & IRQSTAT_CTOE) {
419 /* Workaround for ESDHC errata ENGcm03648 */
420 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
423 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
424 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
431 printf("Timeout waiting for DAT0 to go high!\n");
437 /* Copy the response to the response buffer */
438 if (cmd->resp_type & MMC_RSP_136) {
439 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
441 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
442 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
443 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
444 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
445 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
446 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
447 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
448 cmd->response[3] = (cmdrsp0 << 8);
450 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
452 /* Wait until all of the blocks are transferred */
454 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
455 esdhc_pio_read_write(priv, data);
458 irqstat = esdhc_read32(®s->irqstat);
460 if (irqstat & IRQSTAT_DTOE) {
465 if (irqstat & DATA_ERR) {
469 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
472 * Need invalidate the dcache here again to avoid any
473 * cache-fill during the DMA operations such as the
474 * speculative pre-fetching etc.
476 if (data->flags & MMC_DATA_READ) {
477 check_and_invalidate_dcache_range(cmd, data);
483 /* Reset CMD and DATA portions on error */
485 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
487 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
491 esdhc_write32(®s->sysctl,
492 esdhc_read32(®s->sysctl) |
494 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
499 esdhc_write32(®s->irqstat, -1);
504 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
506 struct fsl_esdhc *regs = priv->esdhc_regs;
509 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
510 unsigned int sdhc_clk = priv->sdhc_clk;
515 if (clock < mmc->cfg->f_min)
516 clock = mmc->cfg->f_min;
518 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
521 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
527 clk = (pre_div << 8) | (div << 4);
529 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
531 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
534 value = PRSSTAT_SDSTB;
535 while (!(esdhc_read32(®s->prsstat) & value)) {
537 printf("fsl_esdhc: Internal clock never stabilised.\n");
544 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
547 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
548 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
550 struct fsl_esdhc *regs = priv->esdhc_regs;
554 value = esdhc_read32(®s->sysctl);
557 value |= SYSCTL_CKEN;
559 value &= ~SYSCTL_CKEN;
561 esdhc_write32(®s->sysctl, value);
564 value = PRSSTAT_SDSTB;
565 while (!(esdhc_read32(®s->prsstat) & value)) {
567 printf("fsl_esdhc: Internal clock never stabilised.\n");
576 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
578 struct fsl_esdhc *regs = priv->esdhc_regs;
580 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
581 /* Select to use peripheral clock */
582 esdhc_clock_control(priv, false);
583 esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
584 esdhc_clock_control(priv, true);
586 /* Set the clock speed */
587 if (priv->clock != mmc->clock)
588 set_sysctl(priv, mmc, mmc->clock);
590 /* Set the bus width */
591 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
593 if (mmc->bus_width == 4)
594 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
595 else if (mmc->bus_width == 8)
596 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
601 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
603 struct fsl_esdhc *regs = priv->esdhc_regs;
606 /* Reset the entire host controller */
607 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
609 /* Wait until the controller is available */
610 start = get_timer(0);
611 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
612 if (get_timer(start) > 1000)
616 /* Enable cache snooping */
617 esdhc_write32(®s->esdhcctl, 0x00000040);
619 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
621 /* Set the initial clock speed */
622 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
624 /* Disable the BRR and BWR bits in IRQSTAT */
625 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
627 /* Put the PROCTL reg back to the default */
628 esdhc_write32(®s->proctl, PROCTL_INIT);
630 /* Set timout to the maximum value */
631 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
636 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
638 struct fsl_esdhc *regs = priv->esdhc_regs;
641 #ifdef CONFIG_ESDHC_DETECT_QUIRK
642 if (CONFIG_ESDHC_DETECT_QUIRK)
646 #if CONFIG_IS_ENABLED(DM_MMC)
647 if (priv->non_removable)
651 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
657 static int esdhc_reset(struct fsl_esdhc *regs)
661 /* reset the controller */
662 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
664 /* hardware clears the bit when it is done */
665 start = get_timer(0);
666 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
667 if (get_timer(start) > 100) {
668 printf("MMC/SD: Reset never completed.\n");
676 #if !CONFIG_IS_ENABLED(DM_MMC)
677 static int esdhc_getcd(struct mmc *mmc)
679 struct fsl_esdhc_priv *priv = mmc->priv;
681 return esdhc_getcd_common(priv);
684 static int esdhc_init(struct mmc *mmc)
686 struct fsl_esdhc_priv *priv = mmc->priv;
688 return esdhc_init_common(priv, mmc);
691 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
692 struct mmc_data *data)
694 struct fsl_esdhc_priv *priv = mmc->priv;
696 return esdhc_send_cmd_common(priv, mmc, cmd, data);
699 static int esdhc_set_ios(struct mmc *mmc)
701 struct fsl_esdhc_priv *priv = mmc->priv;
703 return esdhc_set_ios_common(priv, mmc);
706 static const struct mmc_ops esdhc_ops = {
707 .getcd = esdhc_getcd,
709 .send_cmd = esdhc_send_cmd,
710 .set_ios = esdhc_set_ios,
714 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
715 struct fsl_esdhc_plat *plat)
717 struct mmc_config *cfg;
718 struct fsl_esdhc *regs;
719 u32 caps, voltage_caps;
725 regs = priv->esdhc_regs;
727 /* First reset the eSDHC controller */
728 ret = esdhc_reset(regs);
732 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
733 SYSCTL_IPGEN | SYSCTL_CKEN);
735 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
737 #ifndef CONFIG_DM_MMC
738 memset(cfg, '\0', sizeof(*cfg));
742 caps = esdhc_read32(®s->hostcapblt);
744 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
745 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
746 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
749 /* T4240 host controller capabilities register should have VS33 bit */
750 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
751 caps = caps | ESDHC_HOSTCAPBLT_VS33;
754 if (caps & ESDHC_HOSTCAPBLT_VS18)
755 voltage_caps |= MMC_VDD_165_195;
756 if (caps & ESDHC_HOSTCAPBLT_VS30)
757 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
758 if (caps & ESDHC_HOSTCAPBLT_VS33)
759 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
761 cfg->name = "FSL_SDHC";
762 #if !CONFIG_IS_ENABLED(DM_MMC)
763 cfg->ops = &esdhc_ops;
765 #ifdef CONFIG_SYS_SD_VOLTAGE
766 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
768 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
770 if ((cfg->voltages & voltage_caps) == 0) {
771 printf("voltage not supported by controller\n");
775 if (priv->bus_width == 8)
776 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
777 else if (priv->bus_width == 4)
778 cfg->host_caps = MMC_MODE_4BIT;
780 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
781 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
782 cfg->host_caps |= MMC_MODE_DDR_52MHz;
785 if (priv->bus_width > 0) {
786 if (priv->bus_width < 8)
787 cfg->host_caps &= ~MMC_MODE_8BIT;
788 if (priv->bus_width < 4)
789 cfg->host_caps &= ~MMC_MODE_4BIT;
792 if (caps & ESDHC_HOSTCAPBLT_HSS)
793 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
795 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
796 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
797 cfg->host_caps &= ~MMC_MODE_8BIT;
801 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
803 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
808 #if !CONFIG_IS_ENABLED(DM_MMC)
809 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
810 struct fsl_esdhc_priv *priv)
815 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
816 priv->bus_width = cfg->max_bus_width;
817 priv->sdhc_clk = cfg->sdhc_clk;
818 priv->wp_enable = cfg->wp_enable;
823 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
825 struct fsl_esdhc_plat *plat;
826 struct fsl_esdhc_priv *priv;
833 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
836 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
842 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
844 debug("%s xlate failure\n", __func__);
850 ret = fsl_esdhc_init(priv, plat);
852 debug("%s init failure\n", __func__);
858 mmc = mmc_create(&plat->cfg, priv);
867 int fsl_esdhc_mmc_init(bd_t *bis)
869 struct fsl_esdhc_cfg *cfg;
871 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
872 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
873 cfg->sdhc_clk = gd->arch.sdhc_clk;
874 return fsl_esdhc_initialize(bis, cfg);
878 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
879 void mmc_adapter_card_type_ident(void)
884 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
885 gd->arch.sdhc_adapter = card_id;
888 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
889 value = QIXIS_READ(brdcfg[5]);
890 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
891 QIXIS_WRITE(brdcfg[5], value);
893 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
894 value = QIXIS_READ(pwr_ctl[1]);
895 value |= QIXIS_EVDD_BY_SDHC_VS;
896 QIXIS_WRITE(pwr_ctl[1], value);
898 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
899 value = QIXIS_READ(brdcfg[5]);
900 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
901 QIXIS_WRITE(brdcfg[5], value);
903 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
905 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
907 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
909 case QIXIS_ESDHC_NO_ADAPTER:
917 #ifdef CONFIG_OF_LIBFDT
918 __weak int esdhc_status_fixup(void *blob, const char *compat)
920 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
921 if (!hwconfig("esdhc")) {
922 do_fixup_by_compat(blob, compat, "status", "disabled",
923 sizeof("disabled"), 1);
930 void fdt_fixup_esdhc(void *blob, bd_t *bd)
932 const char *compat = "fsl,esdhc";
934 if (esdhc_status_fixup(blob, compat))
937 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
938 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
939 gd->arch.sdhc_clk, 1);
941 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
942 gd->arch.sdhc_clk, 1);
944 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
945 do_fixup_by_compat_u32(blob, compat, "adapter-type",
946 (u32)(gd->arch.sdhc_adapter), 1);
951 #if CONFIG_IS_ENABLED(DM_MMC)
953 #include <asm/arch/clock.h>
955 static int fsl_esdhc_probe(struct udevice *dev)
957 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
958 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
959 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
963 #if !CONFIG_IS_ENABLED(BLK)
964 struct blk_desc *bdesc;
968 addr = dev_read_addr(dev);
969 if (addr == FDT_ADDR_T_NONE)
972 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
974 priv->esdhc_regs = (struct fsl_esdhc *)addr;
978 val = dev_read_u32_default(dev, "bus-width", -1);
986 if (dev_read_bool(dev, "non-removable")) {
987 priv->non_removable = 1;
989 priv->non_removable = 0;
994 if (IS_ENABLED(CONFIG_CLK)) {
995 /* Assigned clock already set clock */
996 ret = clk_get_by_name(dev, "per", &priv->per_clk);
998 printf("Failed to get per_clk\n");
1001 ret = clk_enable(&priv->per_clk);
1003 printf("Failed to enable per_clk\n");
1007 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1010 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1012 priv->sdhc_clk = gd->arch.sdhc_clk;
1014 if (priv->sdhc_clk <= 0) {
1015 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1020 ret = fsl_esdhc_init(priv, plat);
1022 dev_err(dev, "fsl_esdhc_init failure\n");
1026 mmc_of_parse(dev, &plat->cfg);
1029 mmc->cfg = &plat->cfg;
1031 #if !CONFIG_IS_ENABLED(BLK)
1034 /* Setup dsr related values */
1036 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1037 /* Setup the universal parts of the block interface just once */
1038 bdesc = mmc_get_blk_desc(mmc);
1039 bdesc->if_type = IF_TYPE_MMC;
1040 bdesc->removable = 1;
1041 bdesc->devnum = mmc_get_next_devnum();
1042 bdesc->block_read = mmc_bread;
1043 bdesc->block_write = mmc_bwrite;
1044 bdesc->block_erase = mmc_berase;
1046 /* setup initial part type */
1047 bdesc->part_type = mmc->cfg->part_type;
1053 return esdhc_init_common(priv, mmc);
1056 #if CONFIG_IS_ENABLED(DM_MMC)
1057 static int fsl_esdhc_get_cd(struct udevice *dev)
1059 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1061 return esdhc_getcd_common(priv);
1064 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1065 struct mmc_data *data)
1067 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1068 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1070 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1073 static int fsl_esdhc_set_ios(struct udevice *dev)
1075 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1076 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1078 return esdhc_set_ios_common(priv, &plat->mmc);
1081 static const struct dm_mmc_ops fsl_esdhc_ops = {
1082 .get_cd = fsl_esdhc_get_cd,
1083 .send_cmd = fsl_esdhc_send_cmd,
1084 .set_ios = fsl_esdhc_set_ios,
1085 #ifdef MMC_SUPPORTS_TUNING
1086 .execute_tuning = fsl_esdhc_execute_tuning,
1091 static const struct udevice_id fsl_esdhc_ids[] = {
1092 { .compatible = "fsl,esdhc", },
1096 #if CONFIG_IS_ENABLED(BLK)
1097 static int fsl_esdhc_bind(struct udevice *dev)
1099 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1101 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1105 U_BOOT_DRIVER(fsl_esdhc) = {
1106 .name = "fsl-esdhc-mmc",
1108 .of_match = fsl_esdhc_ids,
1109 .ops = &fsl_esdhc_ops,
1110 #if CONFIG_IS_ENABLED(BLK)
1111 .bind = fsl_esdhc_bind,
1113 .probe = fsl_esdhc_probe,
1114 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1115 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),