2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
24 #include <asm-generic/gpio.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
30 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
31 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
32 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
36 uint dsaddr; /* SDMA system address register */
37 uint blkattr; /* Block attributes register */
38 uint cmdarg; /* Command argument register */
39 uint xfertyp; /* Transfer type register */
40 uint cmdrsp0; /* Command response 0 register */
41 uint cmdrsp1; /* Command response 1 register */
42 uint cmdrsp2; /* Command response 2 register */
43 uint cmdrsp3; /* Command response 3 register */
44 uint datport; /* Buffer data port register */
45 uint prsstat; /* Present state register */
46 uint proctl; /* Protocol control register */
47 uint sysctl; /* System Control Register */
48 uint irqstat; /* Interrupt status register */
49 uint irqstaten; /* Interrupt status enable register */
50 uint irqsigen; /* Interrupt signal enable register */
51 uint autoc12err; /* Auto CMD error status register */
52 uint hostcapblt; /* Host controller capabilities register */
53 uint wml; /* Watermark level register */
54 uint mixctrl; /* For USDHC */
55 char reserved1[4]; /* reserved */
56 uint fevt; /* Force event register */
57 uint admaes; /* ADMA error status register */
58 uint adsaddr; /* ADMA system address register */
62 uint clktunectrlstatus;
68 uint hostver; /* Host controller version register */
69 char reserved5[4]; /* reserved */
70 uint dmaerraddr; /* DMA error address register */
71 char reserved6[4]; /* reserved */
72 uint dmaerrattr; /* DMA error attribute register */
73 char reserved7[4]; /* reserved */
74 uint hostcapblt2; /* Host controller capabilities register 2 */
75 char reserved8[8]; /* reserved */
76 uint tcr; /* Tuning control register */
77 char reserved9[28]; /* reserved */
78 uint sddirctl; /* SD direction control register */
79 char reserved10[712];/* reserved */
80 uint scr; /* eSDHC control register */
84 * struct fsl_esdhc_priv
86 * @esdhc_regs: registers of the sdhc controller
87 * @sdhc_clk: Current clk of the sdhc controller
88 * @bus_width: bus width, 1bit, 4bit or 8bit
91 * Following is used when Driver Model is enabled for MMC
92 * @dev: pointer for the device
93 * @non_removable: 0: removable; 1: non-removable
94 * @wp_enable: 1: enable checking wp; 0: no check
95 * @cd_gpio: gpio for card detection
96 * @wp_gpio: gpio for write protection
98 struct fsl_esdhc_priv {
99 struct fsl_esdhc *esdhc_regs;
100 unsigned int sdhc_clk;
101 unsigned int bus_width;
102 struct mmc_config cfg;
107 #ifdef CONFIG_DM_GPIO
108 struct gpio_desc cd_gpio;
109 struct gpio_desc wp_gpio;
113 /* Return the XFERTYP flags for a given command and data packet */
114 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
119 xfertyp |= XFERTYP_DPSEL;
120 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
121 xfertyp |= XFERTYP_DMAEN;
123 if (data->blocks > 1) {
124 xfertyp |= XFERTYP_MSBSEL;
125 xfertyp |= XFERTYP_BCEN;
126 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
127 xfertyp |= XFERTYP_AC12EN;
131 if (data->flags & MMC_DATA_READ)
132 xfertyp |= XFERTYP_DTDSEL;
135 if (cmd->resp_type & MMC_RSP_CRC)
136 xfertyp |= XFERTYP_CCCEN;
137 if (cmd->resp_type & MMC_RSP_OPCODE)
138 xfertyp |= XFERTYP_CICEN;
139 if (cmd->resp_type & MMC_RSP_136)
140 xfertyp |= XFERTYP_RSPTYP_136;
141 else if (cmd->resp_type & MMC_RSP_BUSY)
142 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
143 else if (cmd->resp_type & MMC_RSP_PRESENT)
144 xfertyp |= XFERTYP_RSPTYP_48;
146 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
147 xfertyp |= XFERTYP_CMDTYP_ABORT;
149 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
152 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
154 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
157 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
159 struct fsl_esdhc_priv *priv = mmc->priv;
160 struct fsl_esdhc *regs = priv->esdhc_regs;
168 if (data->flags & MMC_DATA_READ) {
169 blocks = data->blocks;
172 timeout = PIO_TIMEOUT;
173 size = data->blocksize;
174 irqstat = esdhc_read32(®s->irqstat);
175 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
178 printf("\nData Read Failed in PIO Mode.");
181 while (size && (!(irqstat & IRQSTAT_TC))) {
182 udelay(100); /* Wait before last byte transfer complete */
183 irqstat = esdhc_read32(®s->irqstat);
184 databuf = in_le32(®s->datport);
185 *((uint *)buffer) = databuf;
192 blocks = data->blocks;
193 buffer = (char *)data->src;
195 timeout = PIO_TIMEOUT;
196 size = data->blocksize;
197 irqstat = esdhc_read32(®s->irqstat);
198 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
201 printf("\nData Write Failed in PIO Mode.");
204 while (size && (!(irqstat & IRQSTAT_TC))) {
205 udelay(100); /* Wait before last byte transfer complete */
206 databuf = *((uint *)buffer);
209 irqstat = esdhc_read32(®s->irqstat);
210 out_le32(®s->datport, databuf);
218 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
221 struct fsl_esdhc_priv *priv = mmc->priv;
222 struct fsl_esdhc *regs = priv->esdhc_regs;
223 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
228 wml_value = data->blocksize/4;
230 if (data->flags & MMC_DATA_READ) {
231 if (wml_value > WML_RD_WML_MAX)
232 wml_value = WML_RD_WML_MAX_VAL;
234 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
235 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
236 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
237 addr = virt_to_phys((void *)(data->dest));
238 if (upper_32_bits(addr))
239 printf("Error found for upper 32 bits\n");
241 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
243 esdhc_write32(®s->dsaddr, (u32)data->dest);
247 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
248 flush_dcache_range((ulong)data->src,
249 (ulong)data->src+data->blocks
252 if (wml_value > WML_WR_WML_MAX)
253 wml_value = WML_WR_WML_MAX_VAL;
254 if (priv->wp_enable) {
255 if ((esdhc_read32(®s->prsstat) &
256 PRSSTAT_WPSPL) == 0) {
257 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
262 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
264 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
265 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
266 addr = virt_to_phys((void *)(data->src));
267 if (upper_32_bits(addr))
268 printf("Error found for upper 32 bits\n");
270 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
272 esdhc_write32(®s->dsaddr, (u32)data->src);
277 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
279 /* Calculate the timeout period for data transactions */
281 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
282 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
283 * So, Number of SD Clock cycles for 0.25sec should be minimum
284 * (SD Clock/sec * 0.25 sec) SD Clock cycles
285 * = (mmc->clock * 1/4) SD Clock cycles
287 * => (2^(timeout+13)) >= mmc->clock * 1/4
288 * Taking log2 both the sides
289 * => timeout + 13 >= log2(mmc->clock/4)
290 * Rounding up to next power of 2
291 * => timeout + 13 = log2(mmc->clock/4) + 1
292 * => timeout + 13 = fls(mmc->clock/4)
294 * However, the MMC spec "It is strongly recommended for hosts to
295 * implement more than 500ms timeout value even if the card
296 * indicates the 250ms maximum busy length." Even the previous
297 * value of 300ms is known to be insufficient for some cards.
299 * => timeout + 13 = fls(mmc->clock/2)
301 timeout = fls(mmc->clock/2);
310 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
311 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
315 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
318 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
323 static void check_and_invalidate_dcache_range
324 (struct mmc_cmd *cmd,
325 struct mmc_data *data) {
328 unsigned size = roundup(ARCH_DMA_MINALIGN,
329 data->blocks*data->blocksize);
330 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
333 addr = virt_to_phys((void *)(data->dest));
334 if (upper_32_bits(addr))
335 printf("Error found for upper 32 bits\n");
337 start = lower_32_bits(addr);
339 start = (unsigned)data->dest;
342 invalidate_dcache_range(start, end);
346 * Sends a command out on the bus. Takes the mmc pointer,
347 * a command pointer, and an optional data pointer.
350 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
355 struct fsl_esdhc_priv *priv = mmc->priv;
356 struct fsl_esdhc *regs = priv->esdhc_regs;
358 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
359 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
363 esdhc_write32(®s->irqstat, -1);
367 /* Wait for the bus to be idle */
368 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
369 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
372 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
375 /* Wait at least 8 SD clock cycles before the next command */
377 * Note: This is way more than 8 cycles, but 1ms seems to
378 * resolve timing issues with some cards
382 /* Set up for a data transfer if we have one */
384 err = esdhc_setup_data(mmc, data);
388 if (data->flags & MMC_DATA_READ)
389 check_and_invalidate_dcache_range(cmd, data);
392 /* Figure out the transfer arguments */
393 xfertyp = esdhc_xfertyp(cmd, data);
396 esdhc_write32(®s->irqsigen, 0);
398 /* Send the command */
399 esdhc_write32(®s->cmdarg, cmd->cmdarg);
400 #if defined(CONFIG_FSL_USDHC)
401 esdhc_write32(®s->mixctrl,
402 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
403 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
404 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
406 esdhc_write32(®s->xfertyp, xfertyp);
409 /* Wait for the command to complete */
410 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
413 irqstat = esdhc_read32(®s->irqstat);
415 if (irqstat & CMD_ERR) {
420 if (irqstat & IRQSTAT_CTOE) {
425 /* Switch voltage to 1.8V if CMD11 succeeded */
426 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
427 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
429 printf("Run CMD11 1.8V switch\n");
430 /* Sleep for 5 ms - max time for card to switch to 1.8V */
434 /* Workaround for ESDHC errata ENGcm03648 */
435 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
438 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
439 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
446 printf("Timeout waiting for DAT0 to go high!\n");
452 /* Copy the response to the response buffer */
453 if (cmd->resp_type & MMC_RSP_136) {
454 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
456 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
457 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
458 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
459 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
460 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
461 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
462 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
463 cmd->response[3] = (cmdrsp0 << 8);
465 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
467 /* Wait until all of the blocks are transferred */
469 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
470 esdhc_pio_read_write(mmc, data);
473 irqstat = esdhc_read32(®s->irqstat);
475 if (irqstat & IRQSTAT_DTOE) {
480 if (irqstat & DATA_ERR) {
484 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
487 * Need invalidate the dcache here again to avoid any
488 * cache-fill during the DMA operations such as the
489 * speculative pre-fetching etc.
491 if (data->flags & MMC_DATA_READ)
492 check_and_invalidate_dcache_range(cmd, data);
497 /* Reset CMD and DATA portions on error */
499 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
501 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
505 esdhc_write32(®s->sysctl,
506 esdhc_read32(®s->sysctl) |
508 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
512 /* If this was CMD11, then notify that power cycle is needed */
513 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
514 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
517 esdhc_write32(®s->irqstat, -1);
522 static void set_sysctl(struct mmc *mmc, uint clock)
525 struct fsl_esdhc_priv *priv = mmc->priv;
526 struct fsl_esdhc *regs = priv->esdhc_regs;
527 int sdhc_clk = priv->sdhc_clk;
530 if (clock < mmc->cfg->f_min)
531 clock = mmc->cfg->f_min;
533 if (sdhc_clk / 16 > clock) {
534 for (pre_div = 2; pre_div < 256; pre_div *= 2)
535 if ((sdhc_clk / pre_div) <= (clock * 16))
540 for (div = 1; div <= 16; div++)
541 if ((sdhc_clk / (div * pre_div)) <= clock)
544 pre_div >>= mmc->ddr_mode ? 2 : 1;
547 clk = (pre_div << 8) | (div << 4);
549 #ifdef CONFIG_FSL_USDHC
550 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
552 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
555 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
559 #ifdef CONFIG_FSL_USDHC
560 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
562 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
567 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
568 static void esdhc_clock_control(struct mmc *mmc, bool enable)
570 struct fsl_esdhc_priv *priv = mmc->priv;
571 struct fsl_esdhc *regs = priv->esdhc_regs;
575 value = esdhc_read32(®s->sysctl);
578 value |= SYSCTL_CKEN;
580 value &= ~SYSCTL_CKEN;
582 esdhc_write32(®s->sysctl, value);
585 value = PRSSTAT_SDSTB;
586 while (!(esdhc_read32(®s->prsstat) & value)) {
588 printf("fsl_esdhc: Internal clock never stabilised.\n");
597 static void esdhc_set_ios(struct mmc *mmc)
599 struct fsl_esdhc_priv *priv = mmc->priv;
600 struct fsl_esdhc *regs = priv->esdhc_regs;
602 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
603 /* Select to use peripheral clock */
604 esdhc_clock_control(mmc, false);
605 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
606 esdhc_clock_control(mmc, true);
608 /* Set the clock speed */
609 set_sysctl(mmc, mmc->clock);
611 /* Set the bus width */
612 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
614 if (mmc->bus_width == 4)
615 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
616 else if (mmc->bus_width == 8)
617 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
621 static int esdhc_init(struct mmc *mmc)
623 struct fsl_esdhc_priv *priv = mmc->priv;
624 struct fsl_esdhc *regs = priv->esdhc_regs;
627 /* Reset the entire host controller */
628 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
630 /* Wait until the controller is available */
631 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
634 #if defined(CONFIG_FSL_USDHC)
635 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
636 esdhc_write32(®s->mmcboot, 0x0);
637 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
638 esdhc_write32(®s->mixctrl, 0x0);
639 esdhc_write32(®s->clktunectrlstatus, 0x0);
641 /* Put VEND_SPEC to default value */
642 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
644 /* Disable DLL_CTRL delay line */
645 esdhc_write32(®s->dllctrl, 0x0);
649 /* Enable cache snooping */
650 esdhc_write32(®s->scr, 0x00000040);
653 #ifndef CONFIG_FSL_USDHC
654 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
656 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
659 /* Set the initial clock speed */
660 mmc_set_clock(mmc, 400000);
662 /* Disable the BRR and BWR bits in IRQSTAT */
663 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
665 /* Put the PROCTL reg back to the default */
666 esdhc_write32(®s->proctl, PROCTL_INIT);
668 /* Set timout to the maximum value */
669 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
671 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
672 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
678 static int esdhc_getcd(struct mmc *mmc)
680 struct fsl_esdhc_priv *priv = mmc->priv;
681 struct fsl_esdhc *regs = priv->esdhc_regs;
684 #ifdef CONFIG_ESDHC_DETECT_QUIRK
685 if (CONFIG_ESDHC_DETECT_QUIRK)
690 if (priv->non_removable)
692 #ifdef CONFIG_DM_GPIO
693 if (dm_gpio_is_valid(&priv->cd_gpio))
694 return dm_gpio_get_value(&priv->cd_gpio);
698 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
704 static void esdhc_reset(struct fsl_esdhc *regs)
706 unsigned long timeout = 100; /* wait max 100 ms */
708 /* reset the controller */
709 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
711 /* hardware clears the bit when it is done */
712 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
715 printf("MMC/SD: Reset never completed.\n");
718 static const struct mmc_ops esdhc_ops = {
719 .send_cmd = esdhc_send_cmd,
720 .set_ios = esdhc_set_ios,
722 .getcd = esdhc_getcd,
725 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
726 struct fsl_esdhc_priv *priv)
731 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
732 priv->bus_width = cfg->max_bus_width;
733 priv->sdhc_clk = cfg->sdhc_clk;
734 priv->wp_enable = cfg->wp_enable;
739 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
741 struct fsl_esdhc *regs;
743 u32 caps, voltage_caps;
748 regs = priv->esdhc_regs;
750 /* First reset the eSDHC controller */
753 #ifndef CONFIG_FSL_USDHC
754 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
755 | SYSCTL_IPGEN | SYSCTL_CKEN);
757 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
758 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
761 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
762 memset(&priv->cfg, 0, sizeof(priv->cfg));
765 caps = esdhc_read32(®s->hostcapblt);
767 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
768 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
769 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
772 /* T4240 host controller capabilities register should have VS33 bit */
773 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
774 caps = caps | ESDHC_HOSTCAPBLT_VS33;
777 if (caps & ESDHC_HOSTCAPBLT_VS18)
778 voltage_caps |= MMC_VDD_165_195;
779 if (caps & ESDHC_HOSTCAPBLT_VS30)
780 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
781 if (caps & ESDHC_HOSTCAPBLT_VS33)
782 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
784 priv->cfg.name = "FSL_SDHC";
785 priv->cfg.ops = &esdhc_ops;
786 #ifdef CONFIG_SYS_SD_VOLTAGE
787 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
789 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
791 if ((priv->cfg.voltages & voltage_caps) == 0) {
792 printf("voltage not supported by controller\n");
796 if (priv->bus_width == 8)
797 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
798 else if (priv->bus_width == 4)
799 priv->cfg.host_caps = MMC_MODE_4BIT;
801 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
802 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
803 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
806 if (priv->bus_width > 0) {
807 if (priv->bus_width < 8)
808 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
809 if (priv->bus_width < 4)
810 priv->cfg.host_caps &= ~MMC_MODE_4BIT;
813 if (caps & ESDHC_HOSTCAPBLT_HSS)
814 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
816 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
817 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
818 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
821 priv->cfg.f_min = 400000;
822 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
824 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
826 mmc = mmc_create(&priv->cfg, priv);
835 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
837 struct fsl_esdhc_priv *priv;
843 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
847 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
849 debug("%s xlate failure\n", __func__);
854 ret = fsl_esdhc_init(priv);
856 debug("%s init failure\n", __func__);
864 int fsl_esdhc_mmc_init(bd_t *bis)
866 struct fsl_esdhc_cfg *cfg;
868 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
869 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
870 cfg->sdhc_clk = gd->arch.sdhc_clk;
871 return fsl_esdhc_initialize(bis, cfg);
874 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
875 void mmc_adapter_card_type_ident(void)
880 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
881 gd->arch.sdhc_adapter = card_id;
884 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
885 value = QIXIS_READ(brdcfg[5]);
886 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
887 QIXIS_WRITE(brdcfg[5], value);
889 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
890 value = QIXIS_READ(pwr_ctl[1]);
891 value |= QIXIS_EVDD_BY_SDHC_VS;
892 QIXIS_WRITE(pwr_ctl[1], value);
894 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
895 value = QIXIS_READ(brdcfg[5]);
896 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
897 QIXIS_WRITE(brdcfg[5], value);
899 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
901 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
903 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
905 case QIXIS_ESDHC_NO_ADAPTER:
913 #ifdef CONFIG_OF_LIBFDT
914 void fdt_fixup_esdhc(void *blob, bd_t *bd)
916 const char *compat = "fsl,esdhc";
918 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
919 if (!hwconfig("esdhc")) {
920 do_fixup_by_compat(blob, compat, "status", "disabled",
926 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
927 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
928 gd->arch.sdhc_clk, 1);
930 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
931 gd->arch.sdhc_clk, 1);
933 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
934 do_fixup_by_compat_u32(blob, compat, "adapter-type",
935 (u32)(gd->arch.sdhc_adapter), 1);
937 do_fixup_by_compat(blob, compat, "status", "okay",
943 #include <asm/arch/clock.h>
944 static int fsl_esdhc_probe(struct udevice *dev)
946 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
947 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
948 const void *fdt = gd->fdt_blob;
949 int node = dev->of_offset;
954 addr = dev_get_addr(dev);
955 if (addr == FDT_ADDR_T_NONE)
958 priv->esdhc_regs = (struct fsl_esdhc *)addr;
961 val = fdtdec_get_int(fdt, node, "bus-width", -1);
969 if (fdt_get_property(fdt, node, "non-removable", NULL)) {
970 priv->non_removable = 1;
972 priv->non_removable = 0;
973 #ifdef CONFIG_DM_GPIO
974 gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0,
975 &priv->cd_gpio, GPIOD_IS_IN);
981 #ifdef CONFIG_DM_GPIO
982 ret = gpio_request_by_name_nodev(fdt, node, "wp-gpios", 0,
983 &priv->wp_gpio, GPIOD_IS_IN);
989 * Because lack of clk driver, if SDHC clk is not enabled,
990 * need to enable it first before this driver is invoked.
992 * we use MXC_ESDHC_CLK to get clk freq.
993 * If one would like to make this function work,
994 * the aliases should be provided in dts as this:
1002 * Then if your board only supports mmc2 and mmc3, but we can
1003 * correctly get the seq as 2 and 3, then let mxc_get_clock
1006 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1007 if (priv->sdhc_clk <= 0) {
1008 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1012 ret = fsl_esdhc_init(priv);
1014 dev_err(dev, "fsl_esdhc_init failure\n");
1018 upriv->mmc = priv->mmc;
1019 priv->mmc->dev = dev;
1024 static const struct udevice_id fsl_esdhc_ids[] = {
1025 { .compatible = "fsl,imx6ul-usdhc", },
1026 { .compatible = "fsl,imx6sx-usdhc", },
1027 { .compatible = "fsl,imx6sl-usdhc", },
1028 { .compatible = "fsl,imx6q-usdhc", },
1029 { .compatible = "fsl,imx7d-usdhc", },
1030 { .compatible = "fsl,esdhc", },
1034 U_BOOT_DRIVER(fsl_esdhc) = {
1035 .name = "fsl-esdhc-mmc",
1037 .of_match = fsl_esdhc_ids,
1038 .probe = fsl_esdhc_probe,
1039 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),