1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
7 * Based vaguely on the pxa mmc code:
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
25 DECLARE_GLOBAL_DATA_PTR;
28 uint dsaddr; /* SDMA system address register */
29 uint blkattr; /* Block attributes register */
30 uint cmdarg; /* Command argument register */
31 uint xfertyp; /* Transfer type register */
32 uint cmdrsp0; /* Command response 0 register */
33 uint cmdrsp1; /* Command response 1 register */
34 uint cmdrsp2; /* Command response 2 register */
35 uint cmdrsp3; /* Command response 3 register */
36 uint datport; /* Buffer data port register */
37 uint prsstat; /* Present state register */
38 uint proctl; /* Protocol control register */
39 uint sysctl; /* System Control Register */
40 uint irqstat; /* Interrupt status register */
41 uint irqstaten; /* Interrupt status enable register */
42 uint irqsigen; /* Interrupt signal enable register */
43 uint autoc12err; /* Auto CMD error status register */
44 uint hostcapblt; /* Host controller capabilities register */
45 uint wml; /* Watermark level register */
46 char reserved1[8]; /* reserved */
47 uint fevt; /* Force event register */
48 uint admaes; /* ADMA error status register */
49 uint adsaddr; /* ADMA system address register */
51 uint hostver; /* Host controller version register */
52 char reserved3[4]; /* reserved */
53 uint dmaerraddr; /* DMA error address register */
54 char reserved4[4]; /* reserved */
55 uint dmaerrattr; /* DMA error attribute register */
56 char reserved5[4]; /* reserved */
57 uint hostcapblt2; /* Host controller capabilities register 2 */
58 char reserved6[756]; /* reserved */
59 uint esdhcctl; /* eSDHC control register */
62 struct fsl_esdhc_plat {
63 struct mmc_config cfg;
68 * struct fsl_esdhc_priv
70 * @esdhc_regs: registers of the sdhc controller
71 * @sdhc_clk: Current clk of the sdhc controller
72 * @bus_width: bus width, 1bit, 4bit or 8bit
75 * Following is used when Driver Model is enabled for MMC
76 * @dev: pointer for the device
77 * @cd_gpio: gpio for card detection
78 * @wp_gpio: gpio for write protection
80 struct fsl_esdhc_priv {
81 struct fsl_esdhc *esdhc_regs;
82 unsigned int sdhc_clk;
84 #if !CONFIG_IS_ENABLED(DM_MMC)
90 /* Return the XFERTYP flags for a given command and data packet */
91 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
96 xfertyp |= XFERTYP_DPSEL;
97 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
98 xfertyp |= XFERTYP_DMAEN;
100 if (data->blocks > 1) {
101 xfertyp |= XFERTYP_MSBSEL;
102 xfertyp |= XFERTYP_BCEN;
103 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
104 xfertyp |= XFERTYP_AC12EN;
108 if (data->flags & MMC_DATA_READ)
109 xfertyp |= XFERTYP_DTDSEL;
112 if (cmd->resp_type & MMC_RSP_CRC)
113 xfertyp |= XFERTYP_CCCEN;
114 if (cmd->resp_type & MMC_RSP_OPCODE)
115 xfertyp |= XFERTYP_CICEN;
116 if (cmd->resp_type & MMC_RSP_136)
117 xfertyp |= XFERTYP_RSPTYP_136;
118 else if (cmd->resp_type & MMC_RSP_BUSY)
119 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
120 else if (cmd->resp_type & MMC_RSP_PRESENT)
121 xfertyp |= XFERTYP_RSPTYP_48;
123 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
124 xfertyp |= XFERTYP_CMDTYP_ABORT;
126 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
129 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
131 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
133 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
134 struct mmc_data *data)
136 struct fsl_esdhc *regs = priv->esdhc_regs;
144 if (data->flags & MMC_DATA_READ) {
145 blocks = data->blocks;
148 start = get_timer(0);
149 size = data->blocksize;
150 irqstat = esdhc_read32(®s->irqstat);
151 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
152 if (get_timer(start) > PIO_TIMEOUT) {
153 printf("\nData Read Failed in PIO Mode.");
157 while (size && (!(irqstat & IRQSTAT_TC))) {
158 udelay(100); /* Wait before last byte transfer complete */
159 irqstat = esdhc_read32(®s->irqstat);
160 databuf = in_le32(®s->datport);
161 *((uint *)buffer) = databuf;
168 blocks = data->blocks;
169 buffer = (char *)data->src;
171 start = get_timer(0);
172 size = data->blocksize;
173 irqstat = esdhc_read32(®s->irqstat);
174 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
175 if (get_timer(start) > PIO_TIMEOUT) {
176 printf("\nData Write Failed in PIO Mode.");
180 while (size && (!(irqstat & IRQSTAT_TC))) {
181 udelay(100); /* Wait before last byte transfer complete */
182 databuf = *((uint *)buffer);
185 irqstat = esdhc_read32(®s->irqstat);
186 out_le32(®s->datport, databuf);
194 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
195 struct mmc_data *data)
198 struct fsl_esdhc *regs = priv->esdhc_regs;
199 #if defined(CONFIG_FSL_LAYERSCAPE)
204 wml_value = data->blocksize/4;
206 if (data->flags & MMC_DATA_READ) {
207 if (wml_value > WML_RD_WML_MAX)
208 wml_value = WML_RD_WML_MAX_VAL;
210 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
211 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
212 #if defined(CONFIG_FSL_LAYERSCAPE)
213 addr = virt_to_phys((void *)(data->dest));
214 if (upper_32_bits(addr))
215 printf("Error found for upper 32 bits\n");
217 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
219 esdhc_write32(®s->dsaddr, (u32)data->dest);
223 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
224 flush_dcache_range((ulong)data->src,
225 (ulong)data->src+data->blocks
228 if (wml_value > WML_WR_WML_MAX)
229 wml_value = WML_WR_WML_MAX_VAL;
231 if (!(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) {
232 printf("Can not write to locked SD card.\n");
236 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
238 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
239 #if defined(CONFIG_FSL_LAYERSCAPE)
240 addr = virt_to_phys((void *)(data->src));
241 if (upper_32_bits(addr))
242 printf("Error found for upper 32 bits\n");
244 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
246 esdhc_write32(®s->dsaddr, (u32)data->src);
251 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
253 /* Calculate the timeout period for data transactions */
255 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
256 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
257 * So, Number of SD Clock cycles for 0.25sec should be minimum
258 * (SD Clock/sec * 0.25 sec) SD Clock cycles
259 * = (mmc->clock * 1/4) SD Clock cycles
261 * => (2^(timeout+13)) >= mmc->clock * 1/4
262 * Taking log2 both the sides
263 * => timeout + 13 >= log2(mmc->clock/4)
264 * Rounding up to next power of 2
265 * => timeout + 13 = log2(mmc->clock/4) + 1
266 * => timeout + 13 = fls(mmc->clock/4)
268 * However, the MMC spec "It is strongly recommended for hosts to
269 * implement more than 500ms timeout value even if the card
270 * indicates the 250ms maximum busy length." Even the previous
271 * value of 300ms is known to be insufficient for some cards.
273 * => timeout + 13 = fls(mmc->clock/2)
275 timeout = fls(mmc->clock/2);
284 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
285 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
289 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
292 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
297 static void check_and_invalidate_dcache_range
298 (struct mmc_cmd *cmd,
299 struct mmc_data *data) {
302 unsigned size = roundup(ARCH_DMA_MINALIGN,
303 data->blocks*data->blocksize);
304 #if defined(CONFIG_FSL_LAYERSCAPE)
307 addr = virt_to_phys((void *)(data->dest));
308 if (upper_32_bits(addr))
309 printf("Error found for upper 32 bits\n");
311 start = lower_32_bits(addr);
313 start = (unsigned)data->dest;
316 invalidate_dcache_range(start, end);
320 * Sends a command out on the bus. Takes the mmc pointer,
321 * a command pointer, and an optional data pointer.
323 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
324 struct mmc_cmd *cmd, struct mmc_data *data)
329 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
330 struct fsl_esdhc *regs = priv->esdhc_regs;
333 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
334 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
338 esdhc_write32(®s->irqstat, -1);
342 /* Wait for the bus to be idle */
343 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
344 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
347 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
350 /* Wait at least 8 SD clock cycles before the next command */
352 * Note: This is way more than 8 cycles, but 1ms seems to
353 * resolve timing issues with some cards
357 /* Set up for a data transfer if we have one */
359 err = esdhc_setup_data(priv, mmc, data);
363 if (data->flags & MMC_DATA_READ)
364 check_and_invalidate_dcache_range(cmd, data);
367 /* Figure out the transfer arguments */
368 xfertyp = esdhc_xfertyp(cmd, data);
371 esdhc_write32(®s->irqsigen, 0);
373 /* Send the command */
374 esdhc_write32(®s->cmdarg, cmd->cmdarg);
375 esdhc_write32(®s->xfertyp, xfertyp);
377 /* Wait for the command to complete */
378 start = get_timer(0);
379 while (!(esdhc_read32(®s->irqstat) & flags)) {
380 if (get_timer(start) > 1000) {
386 irqstat = esdhc_read32(®s->irqstat);
388 if (irqstat & CMD_ERR) {
393 if (irqstat & IRQSTAT_CTOE) {
398 /* Workaround for ESDHC errata ENGcm03648 */
399 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
402 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
403 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
410 printf("Timeout waiting for DAT0 to go high!\n");
416 /* Copy the response to the response buffer */
417 if (cmd->resp_type & MMC_RSP_136) {
418 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
420 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
421 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
422 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
423 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
424 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
425 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
426 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
427 cmd->response[3] = (cmdrsp0 << 8);
429 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
431 /* Wait until all of the blocks are transferred */
433 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
434 esdhc_pio_read_write(priv, data);
437 irqstat = esdhc_read32(®s->irqstat);
439 if (irqstat & IRQSTAT_DTOE) {
444 if (irqstat & DATA_ERR) {
448 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
451 * Need invalidate the dcache here again to avoid any
452 * cache-fill during the DMA operations such as the
453 * speculative pre-fetching etc.
455 if (data->flags & MMC_DATA_READ) {
456 check_and_invalidate_dcache_range(cmd, data);
462 /* Reset CMD and DATA portions on error */
464 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
466 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
470 esdhc_write32(®s->sysctl,
471 esdhc_read32(®s->sysctl) |
473 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
478 esdhc_write32(®s->irqstat, -1);
483 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
485 struct fsl_esdhc *regs = priv->esdhc_regs;
488 unsigned int sdhc_clk = priv->sdhc_clk;
493 if (clock < mmc->cfg->f_min)
494 clock = mmc->cfg->f_min;
496 while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
499 while (sdhc_clk / (div * pre_div) > clock && div < 16)
505 clk = (pre_div << 8) | (div << 4);
507 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
509 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
512 value = PRSSTAT_SDSTB;
513 while (!(esdhc_read32(®s->prsstat) & value)) {
515 printf("fsl_esdhc: Internal clock never stabilised.\n");
522 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
525 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
526 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
528 struct fsl_esdhc *regs = priv->esdhc_regs;
532 value = esdhc_read32(®s->sysctl);
535 value |= SYSCTL_CKEN;
537 value &= ~SYSCTL_CKEN;
539 esdhc_write32(®s->sysctl, value);
542 value = PRSSTAT_SDSTB;
543 while (!(esdhc_read32(®s->prsstat) & value)) {
545 printf("fsl_esdhc: Internal clock never stabilised.\n");
554 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
556 struct fsl_esdhc *regs = priv->esdhc_regs;
558 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
559 /* Select to use peripheral clock */
560 esdhc_clock_control(priv, false);
561 esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
562 esdhc_clock_control(priv, true);
564 /* Set the clock speed */
565 if (priv->clock != mmc->clock)
566 set_sysctl(priv, mmc, mmc->clock);
568 /* Set the bus width */
569 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
571 if (mmc->bus_width == 4)
572 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
573 else if (mmc->bus_width == 8)
574 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
579 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
581 struct fsl_esdhc *regs = priv->esdhc_regs;
584 /* Reset the entire host controller */
585 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
587 /* Wait until the controller is available */
588 start = get_timer(0);
589 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
590 if (get_timer(start) > 1000)
594 /* Enable cache snooping */
595 esdhc_write32(®s->esdhcctl, 0x00000040);
597 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
599 /* Set the initial clock speed */
600 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
602 /* Disable the BRR and BWR bits in IRQSTAT */
603 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
605 /* Put the PROCTL reg back to the default */
606 esdhc_write32(®s->proctl, PROCTL_INIT);
608 /* Set timout to the maximum value */
609 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
614 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
616 struct fsl_esdhc *regs = priv->esdhc_regs;
619 #ifdef CONFIG_ESDHC_DETECT_QUIRK
620 if (CONFIG_ESDHC_DETECT_QUIRK)
623 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
629 static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
630 struct mmc_config *cfg)
632 struct fsl_esdhc *regs = priv->esdhc_regs;
635 caps = esdhc_read32(®s->hostcapblt);
636 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
637 caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
639 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
640 caps |= HOSTCAPBLT_VS33;
642 if (caps & HOSTCAPBLT_VS18)
643 cfg->voltages |= MMC_VDD_165_195;
644 if (caps & HOSTCAPBLT_VS30)
645 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
646 if (caps & HOSTCAPBLT_VS33)
647 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
649 cfg->name = "FSL_SDHC";
651 if (caps & HOSTCAPBLT_HSS)
652 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
655 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
656 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
659 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
660 void mmc_adapter_card_type_ident(void)
665 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
666 gd->arch.sdhc_adapter = card_id;
669 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
670 value = QIXIS_READ(brdcfg[5]);
671 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
672 QIXIS_WRITE(brdcfg[5], value);
674 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
675 value = QIXIS_READ(pwr_ctl[1]);
676 value |= QIXIS_EVDD_BY_SDHC_VS;
677 QIXIS_WRITE(pwr_ctl[1], value);
679 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
680 value = QIXIS_READ(brdcfg[5]);
681 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
682 QIXIS_WRITE(brdcfg[5], value);
684 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
686 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
688 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
690 case QIXIS_ESDHC_NO_ADAPTER:
698 #ifdef CONFIG_OF_LIBFDT
699 __weak int esdhc_status_fixup(void *blob, const char *compat)
701 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
702 if (!hwconfig("esdhc")) {
703 do_fixup_by_compat(blob, compat, "status", "disabled",
704 sizeof("disabled"), 1);
711 void fdt_fixup_esdhc(void *blob, bd_t *bd)
713 const char *compat = "fsl,esdhc";
715 if (esdhc_status_fixup(blob, compat))
718 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
719 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
720 gd->arch.sdhc_clk, 1);
722 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
723 gd->arch.sdhc_clk, 1);
725 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
726 do_fixup_by_compat_u32(blob, compat, "adapter-type",
727 (u32)(gd->arch.sdhc_adapter), 1);
732 #if !CONFIG_IS_ENABLED(DM_MMC)
733 static int esdhc_getcd(struct mmc *mmc)
735 struct fsl_esdhc_priv *priv = mmc->priv;
737 return esdhc_getcd_common(priv);
740 static int esdhc_init(struct mmc *mmc)
742 struct fsl_esdhc_priv *priv = mmc->priv;
744 return esdhc_init_common(priv, mmc);
747 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
748 struct mmc_data *data)
750 struct fsl_esdhc_priv *priv = mmc->priv;
752 return esdhc_send_cmd_common(priv, mmc, cmd, data);
755 static int esdhc_set_ios(struct mmc *mmc)
757 struct fsl_esdhc_priv *priv = mmc->priv;
759 return esdhc_set_ios_common(priv, mmc);
762 static const struct mmc_ops esdhc_ops = {
763 .getcd = esdhc_getcd,
765 .send_cmd = esdhc_send_cmd,
766 .set_ios = esdhc_set_ios,
769 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
771 struct fsl_esdhc_plat *plat;
772 struct fsl_esdhc_priv *priv;
773 struct mmc_config *mmc_cfg;
779 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
782 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
788 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
789 priv->sdhc_clk = cfg->sdhc_clk;
791 mmc_cfg = &plat->cfg;
793 if (cfg->max_bus_width == 8) {
794 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
796 } else if (cfg->max_bus_width == 4) {
797 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
798 } else if (cfg->max_bus_width == 1) {
799 mmc_cfg->host_caps |= MMC_MODE_1BIT;
801 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
803 printf("No max bus width provided. Assume 8-bit supported.\n");
806 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
807 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
808 mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
810 mmc_cfg->ops = &esdhc_ops;
812 fsl_esdhc_get_cfg_common(priv, mmc_cfg);
814 mmc = mmc_create(mmc_cfg, priv);
822 int fsl_esdhc_mmc_init(bd_t *bis)
824 struct fsl_esdhc_cfg *cfg;
826 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
827 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
828 cfg->sdhc_clk = gd->arch.sdhc_clk;
829 return fsl_esdhc_initialize(bis, cfg);
832 static int fsl_esdhc_probe(struct udevice *dev)
834 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
835 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
836 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
840 addr = dev_read_addr(dev);
841 if (addr == FDT_ADDR_T_NONE)
844 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
846 priv->esdhc_regs = (struct fsl_esdhc *)addr;
850 priv->sdhc_clk = gd->arch.sdhc_clk;
851 if (priv->sdhc_clk <= 0) {
852 dev_err(dev, "Unable to get clk for %s\n", dev->name);
856 fsl_esdhc_get_cfg_common(priv, &plat->cfg);
858 mmc_of_parse(dev, &plat->cfg);
861 mmc->cfg = &plat->cfg;
866 return esdhc_init_common(priv, mmc);
869 static int fsl_esdhc_get_cd(struct udevice *dev)
871 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
872 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
874 if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
877 return esdhc_getcd_common(priv);
880 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
881 struct mmc_data *data)
883 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
884 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
886 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
889 static int fsl_esdhc_set_ios(struct udevice *dev)
891 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
892 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
894 return esdhc_set_ios_common(priv, &plat->mmc);
897 static const struct dm_mmc_ops fsl_esdhc_ops = {
898 .get_cd = fsl_esdhc_get_cd,
899 .send_cmd = fsl_esdhc_send_cmd,
900 .set_ios = fsl_esdhc_set_ios,
901 #ifdef MMC_SUPPORTS_TUNING
902 .execute_tuning = fsl_esdhc_execute_tuning,
906 static const struct udevice_id fsl_esdhc_ids[] = {
907 { .compatible = "fsl,esdhc", },
911 static int fsl_esdhc_bind(struct udevice *dev)
913 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
915 return mmc_bind(dev, &plat->mmc, &plat->cfg);
918 U_BOOT_DRIVER(fsl_esdhc) = {
919 .name = "fsl-esdhc-mmc",
921 .of_match = fsl_esdhc_ids,
922 .ops = &fsl_esdhc_ops,
923 .bind = fsl_esdhc_bind,
924 .probe = fsl_esdhc_probe,
925 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
926 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),