1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012 SAMSUNG Electronics
4 * Jaehoon Chung <jh80.chung@samsung.com>
5 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
18 #include <asm/cache.h>
19 #include <power/regulator.h>
21 #define PAGE_SIZE 4096
23 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
25 unsigned long timeout = 1000;
28 dwmci_writel(host, DWMCI_CTRL, value);
31 ctrl = dwmci_readl(host, DWMCI_CTRL);
32 if (!(ctrl & DWMCI_RESET_ALL))
38 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
39 u32 desc0, u32 desc1, u32 desc2)
41 struct dwmci_idmac *desc = idmac;
46 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
49 static void dwmci_prepare_data(struct dwmci_host *host,
50 struct mmc_data *data,
51 struct dwmci_idmac *cur_idmac,
55 unsigned int i = 0, flags, cnt, blk_cnt;
56 ulong data_start, data_end;
59 blk_cnt = data->blocks;
61 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
63 /* Clear IDMAC interrupt */
64 dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
66 data_start = (ulong)cur_idmac;
67 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
70 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
71 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
73 flags |= DWMCI_IDMAC_LD;
74 cnt = data->blocksize * blk_cnt;
76 cnt = data->blocksize * 8;
78 dwmci_set_idma_desc(cur_idmac, flags, cnt,
79 (ulong)bounce_buffer + (i * PAGE_SIZE));
88 data_end = (ulong)cur_idmac;
89 flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
91 ctrl = dwmci_readl(host, DWMCI_CTRL);
92 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
93 dwmci_writel(host, DWMCI_CTRL, ctrl);
95 ctrl = dwmci_readl(host, DWMCI_BMOD);
96 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
97 dwmci_writel(host, DWMCI_BMOD, ctrl);
99 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
100 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
103 static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len)
107 *len = dwmci_readl(host, DWMCI_STATUS);
108 while (--timeout && (*len & bit)) {
110 *len = dwmci_readl(host, DWMCI_STATUS);
114 debug("%s: FIFO underflow timeout\n", __func__);
121 static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
123 unsigned int timeout;
125 timeout = size * 8; /* counting in bits */
126 timeout *= 10; /* wait 10 times as long */
127 timeout /= mmc->clock;
128 timeout /= mmc->bus_width;
129 timeout /= mmc->ddr_mode ? 2 : 1;
130 timeout *= 1000; /* counting in msec */
131 timeout = (timeout < 1000) ? 1000 : timeout;
136 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
138 struct mmc *mmc = host->mmc;
140 u32 timeout, mask, size, i, len = 0;
142 ulong start = get_timer(0);
143 u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
144 RX_WMARK_SHIFT) + 1) * 2;
146 size = data->blocksize * data->blocks;
147 if (data->flags == MMC_DATA_READ)
148 buf = (unsigned int *)data->dest;
150 buf = (unsigned int *)data->src;
152 timeout = dwmci_get_timeout(mmc, size);
157 mask = dwmci_readl(host, DWMCI_RINTSTS);
158 /* Error during data transfer. */
159 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
160 debug("%s: DATA ERROR!\n", __func__);
165 if (host->fifo_mode && size) {
167 if (data->flags == MMC_DATA_READ &&
168 (mask & DWMCI_INTMSK_RXDR)) {
170 ret = dwmci_fifo_ready(host,
176 len = (len >> DWMCI_FIFO_SHIFT) &
178 len = min(size, len);
179 for (i = 0; i < len; i++)
181 dwmci_readl(host, DWMCI_DATA);
182 size = size > len ? (size - len) : 0;
184 dwmci_writel(host, DWMCI_RINTSTS,
186 } else if (data->flags == MMC_DATA_WRITE &&
187 (mask & DWMCI_INTMSK_TXDR)) {
189 ret = dwmci_fifo_ready(host,
195 len = fifo_depth - ((len >>
198 len = min(size, len);
199 for (i = 0; i < len; i++)
200 dwmci_writel(host, DWMCI_DATA,
202 size = size > len ? (size - len) : 0;
204 dwmci_writel(host, DWMCI_RINTSTS,
209 /* Data arrived correctly. */
210 if (mask & DWMCI_INTMSK_DTO) {
215 /* Check for timeout. */
216 if (get_timer(start) > timeout) {
217 debug("%s: Timeout waiting for data!\n",
224 dwmci_writel(host, DWMCI_RINTSTS, mask);
229 static int dwmci_set_transfer_mode(struct dwmci_host *host,
230 struct mmc_data *data)
234 mode = DWMCI_CMD_DATA_EXP;
235 if (data->flags & MMC_DATA_WRITE)
236 mode |= DWMCI_CMD_RW;
242 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
243 struct mmc_data *data)
245 struct mmc *mmc = mmc_get_mmc_dev(dev);
247 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
248 struct mmc_data *data)
251 struct dwmci_host *host = mmc->priv;
252 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
253 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
254 int ret = 0, flags = 0, i;
255 unsigned int timeout = 500;
258 ulong start = get_timer(0);
259 struct bounce_buffer bbstate;
261 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
262 if (get_timer(start) > timeout) {
263 debug("%s: Timeout on data busy\n", __func__);
268 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
271 if (host->fifo_mode) {
272 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
273 dwmci_writel(host, DWMCI_BYTCNT,
274 data->blocksize * data->blocks);
275 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
277 if (data->flags == MMC_DATA_READ) {
278 ret = bounce_buffer_start(&bbstate,
281 data->blocks, GEN_BB_WRITE);
283 ret = bounce_buffer_start(&bbstate,
286 data->blocks, GEN_BB_READ);
292 dwmci_prepare_data(host, data, cur_idmac,
293 bbstate.bounce_buffer);
297 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
300 flags = dwmci_set_transfer_mode(host, data);
302 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
305 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
306 flags |= DWMCI_CMD_ABORT_STOP;
308 flags |= DWMCI_CMD_PRV_DAT_WAIT;
310 if (cmd->resp_type & MMC_RSP_PRESENT) {
311 flags |= DWMCI_CMD_RESP_EXP;
312 if (cmd->resp_type & MMC_RSP_136)
313 flags |= DWMCI_CMD_RESP_LENGTH;
316 if (cmd->resp_type & MMC_RSP_CRC)
317 flags |= DWMCI_CMD_CHECK_CRC;
319 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
321 debug("Sending CMD%d\n",cmd->cmdidx);
323 dwmci_writel(host, DWMCI_CMD, flags);
325 for (i = 0; i < retry; i++) {
326 mask = dwmci_readl(host, DWMCI_RINTSTS);
327 if (mask & DWMCI_INTMSK_CDONE) {
329 dwmci_writel(host, DWMCI_RINTSTS, mask);
335 debug("%s: Timeout.\n", __func__);
339 if (mask & DWMCI_INTMSK_RTO) {
341 * Timeout here is not necessarily fatal. (e)MMC cards
342 * will splat here when they receive CMD55 as they do
343 * not support this command and that is exactly the way
344 * to tell them apart from SD cards. Thus, this output
345 * below shall be debug(). eMMC cards also do not favor
346 * CMD8, please keep that in mind.
348 debug("%s: Response Timeout.\n", __func__);
350 } else if (mask & DWMCI_INTMSK_RE) {
351 debug("%s: Response Error.\n", __func__);
353 } else if ((cmd->resp_type & MMC_RSP_CRC) &&
354 (mask & DWMCI_INTMSK_RCRC)) {
355 debug("%s: Response CRC Error.\n", __func__);
360 if (cmd->resp_type & MMC_RSP_PRESENT) {
361 if (cmd->resp_type & MMC_RSP_136) {
362 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
363 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
364 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
365 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
367 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
372 ret = dwmci_data_transfer(host, data);
374 /* only dma mode need it */
375 if (!host->fifo_mode) {
376 if (data->flags == MMC_DATA_READ)
377 mask = DWMCI_IDINTEN_RI;
379 mask = DWMCI_IDINTEN_TI;
380 ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
381 mask, true, 1000, false);
383 debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n",
385 /* clear interrupts */
386 dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
388 ctrl = dwmci_readl(host, DWMCI_CTRL);
389 ctrl &= ~(DWMCI_DMA_EN);
390 dwmci_writel(host, DWMCI_CTRL, ctrl);
391 bounce_buffer_stop(&bbstate);
400 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
406 if ((freq == host->clock) || (freq == 0))
409 * If host->get_mmc_clk isn't defined,
410 * then assume that host->bus_hz is source clock value.
411 * host->bus_hz should be set by user.
413 if (host->get_mmc_clk)
414 sclk = host->get_mmc_clk(host, freq);
415 else if (host->bus_hz)
418 debug("%s: Didn't get source clock value.\n", __func__);
423 div = 0; /* bypass mode */
425 div = DIV_ROUND_UP(sclk, 2 * freq);
427 dwmci_writel(host, DWMCI_CLKENA, 0);
428 dwmci_writel(host, DWMCI_CLKSRC, 0);
430 dwmci_writel(host, DWMCI_CLKDIV, div);
431 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
432 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
435 status = dwmci_readl(host, DWMCI_CMD);
437 debug("%s: Timeout!\n", __func__);
440 } while (status & DWMCI_CMD_START);
442 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
443 DWMCI_CLKEN_LOW_PWR);
445 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
446 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
450 status = dwmci_readl(host, DWMCI_CMD);
452 debug("%s: Timeout!\n", __func__);
455 } while (status & DWMCI_CMD_START);
463 static int dwmci_set_ios(struct udevice *dev)
465 struct mmc *mmc = mmc_get_mmc_dev(dev);
467 static int dwmci_set_ios(struct mmc *mmc)
470 struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
473 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
475 dwmci_setup_bus(host, mmc->clock);
476 switch (mmc->bus_width) {
478 ctype = DWMCI_CTYPE_8BIT;
481 ctype = DWMCI_CTYPE_4BIT;
484 ctype = DWMCI_CTYPE_1BIT;
488 dwmci_writel(host, DWMCI_CTYPE, ctype);
490 regs = dwmci_readl(host, DWMCI_UHS_REG);
492 regs |= DWMCI_DDR_MODE;
494 regs &= ~DWMCI_DDR_MODE;
496 dwmci_writel(host, DWMCI_UHS_REG, regs);
501 #if CONFIG_IS_ENABLED(DM_REGULATOR)
502 if (mmc->vqmmc_supply) {
505 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
506 regulator_set_value(mmc->vqmmc_supply, 1800000);
508 regulator_set_value(mmc->vqmmc_supply, 3300000);
510 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
519 static int dwmci_init(struct mmc *mmc)
521 struct dwmci_host *host = mmc->priv;
523 if (host->board_init)
524 host->board_init(host);
526 dwmci_writel(host, DWMCI_PWREN, 1);
528 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
529 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
533 /* Enumerate at 400KHz */
534 dwmci_setup_bus(host, mmc->cfg->f_min);
536 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
537 dwmci_writel(host, DWMCI_INTMASK, 0);
539 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
541 dwmci_writel(host, DWMCI_IDINTEN, 0);
542 dwmci_writel(host, DWMCI_BMOD, 1);
544 if (!host->fifoth_val) {
547 fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
548 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
549 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
550 TX_WMARK(fifo_size / 2);
552 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
554 dwmci_writel(host, DWMCI_CLKENA, 0);
555 dwmci_writel(host, DWMCI_CLKSRC, 0);
557 if (!host->fifo_mode)
558 dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
564 int dwmci_probe(struct udevice *dev)
566 struct mmc *mmc = mmc_get_mmc_dev(dev);
568 return dwmci_init(mmc);
571 const struct dm_mmc_ops dm_dwmci_ops = {
572 .send_cmd = dwmci_send_cmd,
573 .set_ios = dwmci_set_ios,
577 static const struct mmc_ops dwmci_ops = {
578 .send_cmd = dwmci_send_cmd,
579 .set_ios = dwmci_set_ios,
584 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
585 u32 max_clk, u32 min_clk)
587 cfg->name = host->name;
588 #ifndef CONFIG_DM_MMC
589 cfg->ops = &dwmci_ops;
591 cfg->f_min = min_clk;
592 cfg->f_max = max_clk;
594 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
596 cfg->host_caps = host->caps;
598 if (host->buswidth == 8) {
599 cfg->host_caps |= MMC_MODE_8BIT;
600 cfg->host_caps &= ~MMC_MODE_4BIT;
602 cfg->host_caps |= MMC_MODE_4BIT;
603 cfg->host_caps &= ~MMC_MODE_8BIT;
605 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
607 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
611 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
613 return mmc_bind(dev, mmc, cfg);
616 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
618 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
620 host->mmc = mmc_create(&host->cfg, host);
621 if (host->mmc == NULL)