drivers/mmc/dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2012 SAMSUNG Electronics
   4  * Jaehoon Chung <jh80.chung@samsung.com>
   5  * Rajeshawari Shinde <rajeshwari.s@samsung.com>
   6  */
   7
   8 #include <bouncebuf.h>
   9 #include <common.h>
  10 #include <errno.h>
  11 #include <malloc.h>
  12 #include <memalign.h>
  13 #include <mmc.h>
  14 #include <dwmmc.h>
  15 #include <wait_bit.h>
  16 #include <power/regulator.h>
  17
  18 #define PAGE_SIZE 4096
  19
  20 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
  21 {
  22         unsigned long timeout = 1000;
  23         u32 ctrl;
  24
  25         dwmci_writel(host, DWMCI_CTRL, value);
  26
  27         while (timeout--) {
  28                 ctrl = dwmci_readl(host, DWMCI_CTRL);
  29                 if (!(ctrl & DWMCI_RESET_ALL))
  30                         return 1;
  31         }
  32         return 0;
  33 }
  34
  35 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
  36                 u32 desc0, u32 desc1, u32 desc2)
  37 {
  38         struct dwmci_idmac *desc = idmac;
  39
  40         desc->flags = desc0;
  41         desc->cnt = desc1;
  42         desc->addr = desc2;
  43         desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
  44 }
  45
  46 static void dwmci_prepare_data(struct dwmci_host *host,
  47                                struct mmc_data *data,
  48                                struct dwmci_idmac *cur_idmac,
  49                                void *bounce_buffer)
  50 {
  51         unsigned long ctrl;
  52         unsigned int i = 0, flags, cnt, blk_cnt;
  53         ulong data_start, data_end;
  54
  55
  56         blk_cnt = data->blocks;
  57
  58         dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
  59
  60         /* Clear IDMAC interrupt */
  61         dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
  62
  63         data_start = (ulong)cur_idmac;
  64         dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
  65
  66         do {
  67                 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
  68                 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
  69                 if (blk_cnt <= 8) {
  70                         flags |= DWMCI_IDMAC_LD;
  71                         cnt = data->blocksize * blk_cnt;
  72                 } else
  73                         cnt = data->blocksize * 8;
  74
  75                 dwmci_set_idma_desc(cur_idmac, flags, cnt,
  76                                     (ulong)bounce_buffer + (i * PAGE_SIZE));
  77
  78                 cur_idmac++;
  79                 if (blk_cnt <= 8)
  80                         break;
  81                 blk_cnt -= 8;
  82                 i++;
  83         } while(1);
  84
  85         data_end = (ulong)cur_idmac;
  86         flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
  87
  88         ctrl = dwmci_readl(host, DWMCI_CTRL);
  89         ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
  90         dwmci_writel(host, DWMCI_CTRL, ctrl);
  91
  92         ctrl = dwmci_readl(host, DWMCI_BMOD);
  93         ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
  94         dwmci_writel(host, DWMCI_BMOD, ctrl);
  95
  96         dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
  97         dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
  98 }
  99
 100 static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len)
 101 {
 102         u32 timeout = 20000;
 103
 104         *len = dwmci_readl(host, DWMCI_STATUS);
 105         while (--timeout && (*len & bit)) {
 106                 udelay(200);
 107                 *len = dwmci_readl(host, DWMCI_STATUS);
 108         }
 109
 110         if (!timeout) {
 111                 debug("%s: FIFO underflow timeout\n", __func__);
 112                 return -ETIMEDOUT;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
 119 {
 120         unsigned int timeout;
 121
 122         timeout = size * 8;     /* counting in bits */
 123         timeout *= 10;          /* wait 10 times as long */
 124         timeout /= mmc->clock;
 125         timeout /= mmc->bus_width;
 126         timeout /= mmc->ddr_mode ? 2 : 1;
 127         timeout *= 1000;        /* counting in msec */
 128         timeout = (timeout < 1000) ? 1000 : timeout;
 129
 130         return timeout;
 131 }
 132
 133 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
 134 {
 135         struct mmc *mmc = host->mmc;
 136         int ret = 0;
 137         u32 timeout, mask, size, i, len = 0;
 138         u32 *buf = NULL;
 139         ulong start = get_timer(0);
 140         u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
 141                             RX_WMARK_SHIFT) + 1) * 2;
 142
 143         size = data->blocksize * data->blocks;
 144         if (data->flags == MMC_DATA_READ)
 145                 buf = (unsigned int *)data->dest;
 146         else
 147                 buf = (unsigned int *)data->src;
 148
 149         timeout = dwmci_get_timeout(mmc, size);
 150
 151         size /= 4;
 152
 153         for (;;) {
 154                 mask = dwmci_readl(host, DWMCI_RINTSTS);
 155                 /* Error during data transfer. */
 156                 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
 157                         debug("%s: DATA ERROR!\n", __func__);
 158                         ret = -EINVAL;
 159                         break;
 160                 }
 161
 162                 if (host->fifo_mode && size) {
 163                         len = 0;
 164                         if (data->flags == MMC_DATA_READ &&
 165                             (mask & DWMCI_INTMSK_RXDR)) {
 166                                 while (size) {
 167                                         ret = dwmci_fifo_ready(host,
 168                                                         DWMCI_FIFO_EMPTY,
 169                                                         &len);
 170                                         if (ret < 0)
 171                                                 break;
 172
 173                                         len = (len >> DWMCI_FIFO_SHIFT) &
 174                                                     DWMCI_FIFO_MASK;
 175                                         len = min(size, len);
 176                                         for (i = 0; i < len; i++)
 177                                                 *buf++ =
 178                                                 dwmci_readl(host, DWMCI_DATA);
 179                                         size = size > len ? (size - len) : 0;
 180                                 }
 181                                 dwmci_writel(host, DWMCI_RINTSTS,
 182                                              DWMCI_INTMSK_RXDR);
 183                         } else if (data->flags == MMC_DATA_WRITE &&
 184                                    (mask & DWMCI_INTMSK_TXDR)) {
 185                                 while (size) {
 186                                         ret = dwmci_fifo_ready(host,
 187                                                         DWMCI_FIFO_FULL,
 188                                                         &len);
 189                                         if (ret < 0)
 190                                                 break;
 191
 192                                         len = fifo_depth - ((len >>
 193                                                    DWMCI_FIFO_SHIFT) &
 194                                                    DWMCI_FIFO_MASK);
 195                                         len = min(size, len);
 196                                         for (i = 0; i < len; i++)
 197                                                 dwmci_writel(host, DWMCI_DATA,
 198                                                              *buf++);
 199                                         size = size > len ? (size - len) : 0;
 200                                 }
 201                                 dwmci_writel(host, DWMCI_RINTSTS,
 202                                              DWMCI_INTMSK_TXDR);
 203                         }
 204                 }
 205
 206                 /* Data arrived correctly. */
 207                 if (mask & DWMCI_INTMSK_DTO) {
 208                         ret = 0;
 209                         break;
 210                 }
 211
 212                 /* Check for timeout. */
 213                 if (get_timer(start) > timeout) {
 214                         debug("%s: Timeout waiting for data!\n",
 215                               __func__);
 216                         ret = -ETIMEDOUT;
 217                         break;
 218                 }
 219         }
 220
 221         dwmci_writel(host, DWMCI_RINTSTS, mask);
 222
 223         return ret;
 224 }
 225
 226 static int dwmci_set_transfer_mode(struct dwmci_host *host,
 227                 struct mmc_data *data)
 228 {
 229         unsigned long mode;
 230
 231         mode = DWMCI_CMD_DATA_EXP;
 232         if (data->flags & MMC_DATA_WRITE)
 233                 mode |= DWMCI_CMD_RW;
 234
 235         return mode;
 236 }
 237
 238 #ifdef CONFIG_DM_MMC
 239 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 240                    struct mmc_data *data)
 241 {
 242         struct mmc *mmc = mmc_get_mmc_dev(dev);
 243 #else
 244 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 245                 struct mmc_data *data)
 246 {
 247 #endif
 248         struct dwmci_host *host = mmc->priv;
 249         ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
 250                                  data ? DIV_ROUND_UP(data->blocks, 8) : 0);
 251         int ret = 0, flags = 0, i;
 252         unsigned int timeout = 500;
 253         u32 retry = 100000;
 254         u32 mask, ctrl;
 255         ulong start = get_timer(0);
 256         struct bounce_buffer bbstate;
 257
 258         while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
 259                 if (get_timer(start) > timeout) {
 260                         debug("%s: Timeout on data busy\n", __func__);
 261                         return -ETIMEDOUT;
 262                 }
 263         }
 264
 265         dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
 266
 267         if (data) {
 268                 if (host->fifo_mode) {
 269                         dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
 270                         dwmci_writel(host, DWMCI_BYTCNT,
 271                                      data->blocksize * data->blocks);
 272                         dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
 273                 } else {
 274                         if (data->flags == MMC_DATA_READ) {
 275                                 ret = bounce_buffer_start(&bbstate,
 276                                                 (void*)data->dest,
 277                                                 data->blocksize *
 278                                                 data->blocks, GEN_BB_WRITE);
 279                         } else {
 280                                 ret = bounce_buffer_start(&bbstate,
 281                                                 (void*)data->src,
 282                                                 data->blocksize *
 283                                                 data->blocks, GEN_BB_READ);
 284                         }
 285
 286                         if (ret)
 287                                 return ret;
 288
 289                         dwmci_prepare_data(host, data, cur_idmac,
 290                                            bbstate.bounce_buffer);
 291                 }
 292         }
 293
 294         dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
 295
 296         if (data)
 297                 flags = dwmci_set_transfer_mode(host, data);
 298
 299         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 300                 return -1;
 301
 302         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 303                 flags |= DWMCI_CMD_ABORT_STOP;
 304         else
 305                 flags |= DWMCI_CMD_PRV_DAT_WAIT;
 306
 307         if (cmd->resp_type & MMC_RSP_PRESENT) {
 308                 flags |= DWMCI_CMD_RESP_EXP;
 309                 if (cmd->resp_type & MMC_RSP_136)
 310                         flags |= DWMCI_CMD_RESP_LENGTH;
 311         }
 312
 313         if (cmd->resp_type & MMC_RSP_CRC)
 314                 flags |= DWMCI_CMD_CHECK_CRC;
 315
 316         flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
 317
 318         debug("Sending CMD%d\n",cmd->cmdidx);
 319
 320         dwmci_writel(host, DWMCI_CMD, flags);
 321
 322         for (i = 0; i < retry; i++) {
 323                 mask = dwmci_readl(host, DWMCI_RINTSTS);
 324                 if (mask & DWMCI_INTMSK_CDONE) {
 325                         if (!data)
 326                                 dwmci_writel(host, DWMCI_RINTSTS, mask);
 327                         break;
 328                 }
 329         }
 330
 331         if (i == retry) {
 332                 debug("%s: Timeout.\n", __func__);
 333                 return -ETIMEDOUT;
 334         }
 335
 336         if (mask & DWMCI_INTMSK_RTO) {
 337                 /*
 338                  * Timeout here is not necessarily fatal. (e)MMC cards
 339                  * will splat here when they receive CMD55 as they do
 340                  * not support this command and that is exactly the way
 341                  * to tell them apart from SD cards. Thus, this output
 342                  * below shall be debug(). eMMC cards also do not favor
 343                  * CMD8, please keep that in mind.
 344                  */
 345                 debug("%s: Response Timeout.\n", __func__);
 346                 return -ETIMEDOUT;
 347         } else if (mask & DWMCI_INTMSK_RE) {
 348                 debug("%s: Response Error.\n", __func__);
 349                 return -EIO;
 350         } else if ((cmd->resp_type & MMC_RSP_CRC) &&
 351                    (mask & DWMCI_INTMSK_RCRC)) {
 352                 debug("%s: Response CRC Error.\n", __func__);
 353                 return -EIO;
 354         }
 355
 356
 357         if (cmd->resp_type & MMC_RSP_PRESENT) {
 358                 if (cmd->resp_type & MMC_RSP_136) {
 359                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
 360                         cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
 361                         cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
 362                         cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
 363                 } else {
 364                         cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
 365                 }
 366         }
 367
 368         if (data) {
 369                 ret = dwmci_data_transfer(host, data);
 370
 371                 /* only dma mode need it */
 372                 if (!host->fifo_mode) {
 373                         if (data->flags == MMC_DATA_READ)
 374                                 mask = DWMCI_IDINTEN_RI;
 375                         else
 376                                 mask = DWMCI_IDINTEN_TI;
 377                         ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
 378                                                 mask, true, 1000, false);
 379                         if (ret)
 380                                 debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n",
 381                                       __func__, mask);
 382                         /* clear interrupts */
 383                         dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
 384
 385                         ctrl = dwmci_readl(host, DWMCI_CTRL);
 386                         ctrl &= ~(DWMCI_DMA_EN);
 387                         dwmci_writel(host, DWMCI_CTRL, ctrl);
 388                         bounce_buffer_stop(&bbstate);
 389                 }
 390         }
 391
 392         udelay(100);
 393
 394         return ret;
 395 }
 396
 397 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
 398 {
 399         u32 div, status;
 400         int timeout = 10000;
 401         unsigned long sclk;
 402
 403         if ((freq == host->clock) || (freq == 0))
 404                 return 0;
 405         /*
 406          * If host->get_mmc_clk isn't defined,
 407          * then assume that host->bus_hz is source clock value.
 408          * host->bus_hz should be set by user.
 409          */
 410         if (host->get_mmc_clk)
 411                 sclk = host->get_mmc_clk(host, freq);
 412         else if (host->bus_hz)
 413                 sclk = host->bus_hz;
 414         else {
 415                 debug("%s: Didn't get source clock value.\n", __func__);
 416                 return -EINVAL;
 417         }
 418
 419         if (sclk == freq)
 420                 div = 0;        /* bypass mode */
 421         else
 422                 div = DIV_ROUND_UP(sclk, 2 * freq);
 423
 424         dwmci_writel(host, DWMCI_CLKENA, 0);
 425         dwmci_writel(host, DWMCI_CLKSRC, 0);
 426
 427         dwmci_writel(host, DWMCI_CLKDIV, div);
 428         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 429                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 430
 431         do {
 432                 status = dwmci_readl(host, DWMCI_CMD);
 433                 if (timeout-- < 0) {
 434                         debug("%s: Timeout!\n", __func__);
 435                         return -ETIMEDOUT;
 436                 }
 437         } while (status & DWMCI_CMD_START);
 438
 439         dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
 440                         DWMCI_CLKEN_LOW_PWR);
 441
 442         dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
 443                         DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
 444
 445         timeout = 10000;
 446         do {
 447                 status = dwmci_readl(host, DWMCI_CMD);
 448                 if (timeout-- < 0) {
 449                         debug("%s: Timeout!\n", __func__);
 450                         return -ETIMEDOUT;
 451                 }
 452         } while (status & DWMCI_CMD_START);
 453
 454         host->clock = freq;
 455
 456         return 0;
 457 }
 458
 459 #ifdef CONFIG_DM_MMC
 460 static int dwmci_set_ios(struct udevice *dev)
 461 {
 462         struct mmc *mmc = mmc_get_mmc_dev(dev);
 463 #else
 464 static int dwmci_set_ios(struct mmc *mmc)
 465 {
 466 #endif
 467         struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
 468         u32 ctype, regs;
 469
 470         debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
 471
 472         dwmci_setup_bus(host, mmc->clock);
 473         switch (mmc->bus_width) {
 474         case 8:
 475                 ctype = DWMCI_CTYPE_8BIT;
 476                 break;
 477         case 4:
 478                 ctype = DWMCI_CTYPE_4BIT;
 479                 break;
 480         default:
 481                 ctype = DWMCI_CTYPE_1BIT;
 482                 break;
 483         }
 484
 485         dwmci_writel(host, DWMCI_CTYPE, ctype);
 486
 487         regs = dwmci_readl(host, DWMCI_UHS_REG);
 488         if (mmc->ddr_mode)
 489                 regs |= DWMCI_DDR_MODE;
 490         else
 491                 regs &= ~DWMCI_DDR_MODE;
 492
 493         dwmci_writel(host, DWMCI_UHS_REG, regs);
 494
 495         if (host->clksel)
 496                 host->clksel(host);
 497
 498 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 499         if (mmc->vqmmc_supply) {
 500                 int ret;
 501
 502                 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
 503                         regulator_set_value(mmc->vqmmc_supply, 1800000);
 504                 else
 505                         regulator_set_value(mmc->vqmmc_supply, 3300000);
 506
 507                 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
 508                 if (ret)
 509                         return ret;
 510         }
 511 #endif
 512
 513         return 0;
 514 }
 515
 516 static int dwmci_init(struct mmc *mmc)
 517 {
 518         struct dwmci_host *host = mmc->priv;
 519
 520         if (host->board_init)
 521                 host->board_init(host);
 522
 523         dwmci_writel(host, DWMCI_PWREN, 1);
 524
 525         if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
 526                 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
 527                 return -EIO;
 528         }
 529
 530         /* Enumerate at 400KHz */
 531         dwmci_setup_bus(host, mmc->cfg->f_min);
 532
 533         dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
 534         dwmci_writel(host, DWMCI_INTMASK, 0);
 535
 536         dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
 537
 538         dwmci_writel(host, DWMCI_IDINTEN, 0);
 539         dwmci_writel(host, DWMCI_BMOD, 1);
 540
 541         if (!host->fifoth_val) {
 542                 uint32_t fifo_size;
 543
 544                 fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
 545                 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
 546                 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
 547                                 TX_WMARK(fifo_size / 2);
 548         }
 549         dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
 550
 551         dwmci_writel(host, DWMCI_CLKENA, 0);
 552         dwmci_writel(host, DWMCI_CLKSRC, 0);
 553
 554         if (!host->fifo_mode)
 555                 dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
 556
 557         return 0;
 558 }
 559
 560 #ifdef CONFIG_DM_MMC
 561 int dwmci_probe(struct udevice *dev)
 562 {
 563         struct mmc *mmc = mmc_get_mmc_dev(dev);
 564
 565         return dwmci_init(mmc);
 566 }
 567
 568 const struct dm_mmc_ops dm_dwmci_ops = {
 569         .send_cmd       = dwmci_send_cmd,
 570         .set_ios        = dwmci_set_ios,
 571 };
 572
 573 #else
 574 static const struct mmc_ops dwmci_ops = {
 575         .send_cmd       = dwmci_send_cmd,
 576         .set_ios        = dwmci_set_ios,
 577         .init           = dwmci_init,
 578 };
 579 #endif
 580
 581 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
 582                 u32 max_clk, u32 min_clk)
 583 {
 584         cfg->name = host->name;
 585 #ifndef CONFIG_DM_MMC
 586         cfg->ops = &dwmci_ops;
 587 #endif
 588         cfg->f_min = min_clk;
 589         cfg->f_max = max_clk;
 590
 591         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 592
 593         cfg->host_caps = host->caps;
 594
 595         if (host->buswidth == 8) {
 596                 cfg->host_caps |= MMC_MODE_8BIT;
 597                 cfg->host_caps &= ~MMC_MODE_4BIT;
 598         } else {
 599                 cfg->host_caps |= MMC_MODE_4BIT;
 600                 cfg->host_caps &= ~MMC_MODE_8BIT;
 601         }
 602         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
 603
 604         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 605 }
 606
 607 #ifdef CONFIG_BLK
 608 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 609 {
 610         return mmc_bind(dev, mmc, cfg);
 611 }
 612 #else
 613 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 614 {
 615         dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
 616
 617         host->mmc = mmc_create(&host->cfg, host);
 618         if (host->mmc == NULL)
 619                 return -1;
 620
 621         return 0;
 622 }
 623 #endif